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UefiCpuPkg/PiSmmCpuDxeSmm: eliminate "gSmmJmpAddr" and related DBs
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c
1 /** @file
2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
3
4 Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
6
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #include "PiSmmCpuDxeSmm.h"
18
19 //
20 // SMM CPU Private Data structure that contains SMM Configuration Protocol
21 // along its supporting fields.
22 //
23 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = {
24 SMM_CPU_PRIVATE_DATA_SIGNATURE, // Signature
25 NULL, // SmmCpuHandle
26 NULL, // Pointer to ProcessorInfo array
27 NULL, // Pointer to Operation array
28 NULL, // Pointer to CpuSaveStateSize array
29 NULL, // Pointer to CpuSaveState array
30 { {0} }, // SmmReservedSmramRegion
31 {
32 SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp
33 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
34 0, // SmmCoreEntryContext.NumberOfCpus
35 NULL, // SmmCoreEntryContext.CpuSaveStateSize
36 NULL // SmmCoreEntryContext.CpuSaveState
37 },
38 NULL, // SmmCoreEntry
39 {
40 mSmmCpuPrivateData.SmmReservedSmramRegion, // SmmConfiguration.SmramReservedRegions
41 RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry
42 },
43 };
44
45 CPU_HOT_PLUG_DATA mCpuHotPlugData = {
46 CPU_HOT_PLUG_DATA_REVISION_1, // Revision
47 0, // Array Length of SmBase and APIC ID
48 NULL, // Pointer to APIC ID array
49 NULL, // Pointer to SMBASE array
50 0, // Reserved
51 0, // SmrrBase
52 0 // SmrrSize
53 };
54
55 //
56 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
57 //
58 SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate = &mSmmCpuPrivateData;
59
60 //
61 // SMM Relocation variables
62 //
63 volatile BOOLEAN *mRebased;
64 volatile BOOLEAN mIsBsp;
65
66 ///
67 /// Handle for the SMM CPU Protocol
68 ///
69 EFI_HANDLE mSmmCpuHandle = NULL;
70
71 ///
72 /// SMM CPU Protocol instance
73 ///
74 EFI_SMM_CPU_PROTOCOL mSmmCpu = {
75 SmmReadSaveState,
76 SmmWriteSaveState
77 };
78
79 ///
80 /// SMM Memory Attribute Protocol instance
81 ///
82 EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = {
83 EdkiiSmmGetMemoryAttributes,
84 EdkiiSmmSetMemoryAttributes,
85 EdkiiSmmClearMemoryAttributes
86 };
87
88 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];
89
90 //
91 // SMM stack information
92 //
93 UINTN mSmmStackArrayBase;
94 UINTN mSmmStackArrayEnd;
95 UINTN mSmmStackSize;
96
97 UINTN mMaxNumberOfCpus = 1;
98 UINTN mNumberOfCpus = 1;
99
100 //
101 // SMM ready to lock flag
102 //
103 BOOLEAN mSmmReadyToLock = FALSE;
104
105 //
106 // Global used to cache PCD for SMM Code Access Check enable
107 //
108 BOOLEAN mSmmCodeAccessCheckEnable = FALSE;
109
110 //
111 // Global copy of the PcdPteMemoryEncryptionAddressOrMask
112 //
113 UINT64 mAddressEncMask = 0;
114
115 //
116 // Spin lock used to serialize setting of SMM Code Access Check feature
117 //
118 SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;
119
120 //
121 // Saved SMM ranges information
122 //
123 EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
124 UINTN mSmmCpuSmramRangeCount;
125
126 UINT8 mPhysicalAddressBits;
127
128 //
129 // Control register contents saved for SMM S3 resume state initialization.
130 //
131 UINT32 mSmmCr0;
132 UINT32 mSmmCr4;
133
134 /**
135 Initialize IDT to setup exception handlers for SMM.
136
137 **/
138 VOID
139 InitializeSmmIdt (
140 VOID
141 )
142 {
143 EFI_STATUS Status;
144 BOOLEAN InterruptState;
145 IA32_DESCRIPTOR DxeIdtr;
146
147 //
148 // There are 32 (not 255) entries in it since only processor
149 // generated exceptions will be handled.
150 //
151 gcSmiIdtr.Limit = (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;
152 //
153 // Allocate page aligned IDT, because it might be set as read only.
154 //
155 gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr.Limit + 1));
156 ASSERT (gcSmiIdtr.Base != 0);
157 ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1);
158
159 //
160 // Disable Interrupt and save DXE IDT table
161 //
162 InterruptState = SaveAndDisableInterrupts ();
163 AsmReadIdtr (&DxeIdtr);
164 //
165 // Load SMM temporary IDT table
166 //
167 AsmWriteIdtr (&gcSmiIdtr);
168 //
169 // Setup SMM default exception handlers, SMM IDT table
170 // will be updated and saved in gcSmiIdtr
171 //
172 Status = InitializeCpuExceptionHandlers (NULL);
173 ASSERT_EFI_ERROR (Status);
174 //
175 // Restore DXE IDT table and CPU interrupt
176 //
177 AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr);
178 SetInterruptState (InterruptState);
179 }
180
181 /**
182 Search module name by input IP address and output it.
183
184 @param CallerIpAddress Caller instruction pointer.
185
186 **/
187 VOID
188 DumpModuleInfoByIp (
189 IN UINTN CallerIpAddress
190 )
191 {
192 UINTN Pe32Data;
193 VOID *PdbPointer;
194
195 //
196 // Find Image Base
197 //
198 Pe32Data = PeCoffSearchImageBase (CallerIpAddress);
199 if (Pe32Data != 0) {
200 DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *) CallerIpAddress));
201 PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
202 if (PdbPointer != NULL) {
203 DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));
204 }
205 }
206 }
207
208 /**
209 Read information from the CPU save state.
210
211 @param This EFI_SMM_CPU_PROTOCOL instance
212 @param Width The number of bytes to read from the CPU save state.
213 @param Register Specifies the CPU register to read form the save state.
214 @param CpuIndex Specifies the zero-based index of the CPU save state.
215 @param Buffer Upon return, this holds the CPU register value read from the save state.
216
217 @retval EFI_SUCCESS The register was read from Save State
218 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
219 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
220
221 **/
222 EFI_STATUS
223 EFIAPI
224 SmmReadSaveState (
225 IN CONST EFI_SMM_CPU_PROTOCOL *This,
226 IN UINTN Width,
227 IN EFI_SMM_SAVE_STATE_REGISTER Register,
228 IN UINTN CpuIndex,
229 OUT VOID *Buffer
230 )
231 {
232 EFI_STATUS Status;
233
234 //
235 // Retrieve pointer to the specified CPU's SMM Save State buffer
236 //
237 if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
238 return EFI_INVALID_PARAMETER;
239 }
240
241 //
242 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
243 //
244 if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {
245 //
246 // The pseudo-register only supports the 64-bit size specified by Width.
247 //
248 if (Width != sizeof (UINT64)) {
249 return EFI_INVALID_PARAMETER;
250 }
251 //
252 // If the processor is in SMM at the time the SMI occurred,
253 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
254 // Otherwise, EFI_NOT_FOUND is returned.
255 //
256 if (*(mSmmMpSyncData->CpuData[CpuIndex].Present)) {
257 *(UINT64 *)Buffer = gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId;
258 return EFI_SUCCESS;
259 } else {
260 return EFI_NOT_FOUND;
261 }
262 }
263
264 if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {
265 return EFI_INVALID_PARAMETER;
266 }
267
268 Status = SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
269 if (Status == EFI_UNSUPPORTED) {
270 Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
271 }
272 return Status;
273 }
274
275 /**
276 Write data to the CPU save state.
277
278 @param This EFI_SMM_CPU_PROTOCOL instance
279 @param Width The number of bytes to read from the CPU save state.
280 @param Register Specifies the CPU register to write to the save state.
281 @param CpuIndex Specifies the zero-based index of the CPU save state
282 @param Buffer Upon entry, this holds the new CPU register value.
283
284 @retval EFI_SUCCESS The register was written from Save State
285 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
286 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
287
288 **/
289 EFI_STATUS
290 EFIAPI
291 SmmWriteSaveState (
292 IN CONST EFI_SMM_CPU_PROTOCOL *This,
293 IN UINTN Width,
294 IN EFI_SMM_SAVE_STATE_REGISTER Register,
295 IN UINTN CpuIndex,
296 IN CONST VOID *Buffer
297 )
298 {
299 EFI_STATUS Status;
300
301 //
302 // Retrieve pointer to the specified CPU's SMM Save State buffer
303 //
304 if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
305 return EFI_INVALID_PARAMETER;
306 }
307
308 //
309 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
310 //
311 if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {
312 return EFI_SUCCESS;
313 }
314
315 if (!mSmmMpSyncData->CpuData[CpuIndex].Present) {
316 return EFI_INVALID_PARAMETER;
317 }
318
319 Status = SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
320 if (Status == EFI_UNSUPPORTED) {
321 Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
322 }
323 return Status;
324 }
325
326
327 /**
328 C function for SMI handler. To change all processor's SMMBase Register.
329
330 **/
331 VOID
332 EFIAPI
333 SmmInitHandler (
334 VOID
335 )
336 {
337 UINT32 ApicId;
338 UINTN Index;
339
340 //
341 // Update SMM IDT entries' code segment and load IDT
342 //
343 AsmWriteIdtr (&gcSmiIdtr);
344 ApicId = GetApicId ();
345
346 ASSERT (mNumberOfCpus <= mMaxNumberOfCpus);
347
348 for (Index = 0; Index < mNumberOfCpus; Index++) {
349 if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
350 //
351 // Initialize SMM specific features on the currently executing CPU
352 //
353 SmmCpuFeaturesInitializeProcessor (
354 Index,
355 mIsBsp,
356 gSmmCpuPrivate->ProcessorInfo,
357 &mCpuHotPlugData
358 );
359
360 if (!mSmmS3Flag) {
361 //
362 // Check XD and BTS features on each processor on normal boot
363 //
364 CheckFeatureSupported ();
365 }
366
367 if (mIsBsp) {
368 //
369 // BSP rebase is already done above.
370 // Initialize private data during S3 resume
371 //
372 InitializeMpSyncData ();
373 }
374
375 //
376 // Hook return after RSM to set SMM re-based flag
377 //
378 SemaphoreHook (Index, &mRebased[Index]);
379
380 return;
381 }
382 }
383 ASSERT (FALSE);
384 }
385
386 /**
387 Relocate SmmBases for each processor.
388
389 Execute on first boot and all S3 resumes
390
391 **/
392 VOID
393 EFIAPI
394 SmmRelocateBases (
395 VOID
396 )
397 {
398 UINT8 BakBuf[BACK_BUF_SIZE];
399 SMRAM_SAVE_STATE_MAP BakBuf2;
400 SMRAM_SAVE_STATE_MAP *CpuStatePtr;
401 UINT8 *U8Ptr;
402 UINT32 ApicId;
403 UINTN Index;
404 UINTN BspIndex;
405
406 //
407 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
408 //
409 ASSERT (sizeof (BakBuf) >= gcSmmInitSize);
410
411 //
412 // Patch ASM code template with current CR0, CR3, and CR4 values
413 //
414 mSmmCr0 = (UINT32)AsmReadCr0 ();
415 PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4);
416 PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);
417 mSmmCr4 = (UINT32)AsmReadCr4 ();
418 PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);
419
420 //
421 // Patch GDTR for SMM base relocation
422 //
423 gcSmiInitGdtr.Base = gcSmiGdtr.Base;
424 gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;
425
426 U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);
427 CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
428
429 //
430 // Backup original contents at address 0x38000
431 //
432 CopyMem (BakBuf, U8Ptr, sizeof (BakBuf));
433 CopyMem (&BakBuf2, CpuStatePtr, sizeof (BakBuf2));
434
435 //
436 // Load image for relocation
437 //
438 CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize);
439
440 //
441 // Retrieve the local APIC ID of current processor
442 //
443 ApicId = GetApicId ();
444
445 //
446 // Relocate SM bases for all APs
447 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
448 //
449 mIsBsp = FALSE;
450 BspIndex = (UINTN)-1;
451 for (Index = 0; Index < mNumberOfCpus; Index++) {
452 mRebased[Index] = FALSE;
453 if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
454 SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
455 //
456 // Wait for this AP to finish its 1st SMI
457 //
458 while (!mRebased[Index]);
459 } else {
460 //
461 // BSP will be Relocated later
462 //
463 BspIndex = Index;
464 }
465 }
466
467 //
468 // Relocate BSP's SMM base
469 //
470 ASSERT (BspIndex != (UINTN)-1);
471 mIsBsp = TRUE;
472 SendSmiIpi (ApicId);
473 //
474 // Wait for the BSP to finish its 1st SMI
475 //
476 while (!mRebased[BspIndex]);
477
478 //
479 // Restore contents at address 0x38000
480 //
481 CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2));
482 CopyMem (U8Ptr, BakBuf, sizeof (BakBuf));
483 }
484
485 /**
486 SMM Ready To Lock event notification handler.
487
488 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
489 perform additional lock actions that must be performed from SMM on the next SMI.
490
491 @param[in] Protocol Points to the protocol's unique identifier.
492 @param[in] Interface Points to the interface instance.
493 @param[in] Handle The handle on which the interface was installed.
494
495 @retval EFI_SUCCESS Notification handler runs successfully.
496 **/
497 EFI_STATUS
498 EFIAPI
499 SmmReadyToLockEventNotify (
500 IN CONST EFI_GUID *Protocol,
501 IN VOID *Interface,
502 IN EFI_HANDLE Handle
503 )
504 {
505 GetAcpiCpuData ();
506
507 //
508 // Cache a copy of UEFI memory map before we start profiling feature.
509 //
510 GetUefiMemoryMap ();
511
512 //
513 // Set SMM ready to lock flag and return
514 //
515 mSmmReadyToLock = TRUE;
516 return EFI_SUCCESS;
517 }
518
519 /**
520 The module Entry Point of the CPU SMM driver.
521
522 @param ImageHandle The firmware allocated handle for the EFI image.
523 @param SystemTable A pointer to the EFI System Table.
524
525 @retval EFI_SUCCESS The entry point is executed successfully.
526 @retval Other Some error occurs when executing this entry point.
527
528 **/
529 EFI_STATUS
530 EFIAPI
531 PiCpuSmmEntry (
532 IN EFI_HANDLE ImageHandle,
533 IN EFI_SYSTEM_TABLE *SystemTable
534 )
535 {
536 EFI_STATUS Status;
537 EFI_MP_SERVICES_PROTOCOL *MpServices;
538 UINTN NumberOfEnabledProcessors;
539 UINTN Index;
540 VOID *Buffer;
541 UINTN BufferPages;
542 UINTN TileCodeSize;
543 UINTN TileDataSize;
544 UINTN TileSize;
545 UINT8 *Stacks;
546 VOID *Registration;
547 UINT32 RegEax;
548 UINT32 RegEdx;
549 UINTN FamilyId;
550 UINTN ModelId;
551 UINT32 Cr3;
552
553 //
554 // Initialize address fixup
555 //
556 PiSmmCpuSmmInitFixupAddress ();
557 PiSmmCpuSmiEntryFixupAddress ();
558
559 //
560 // Initialize Debug Agent to support source level debug in SMM code
561 //
562 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL);
563
564 //
565 // Report the start of CPU SMM initialization.
566 //
567 REPORT_STATUS_CODE (
568 EFI_PROGRESS_CODE,
569 EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT
570 );
571
572 //
573 // Find out SMRR Base and SMRR Size
574 //
575 FindSmramInfo (&mCpuHotPlugData.SmrrBase, &mCpuHotPlugData.SmrrSize);
576
577 //
578 // Get MP Services Protocol
579 //
580 Status = SystemTable->BootServices->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices);
581 ASSERT_EFI_ERROR (Status);
582
583 //
584 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
585 //
586 Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus, &NumberOfEnabledProcessors);
587 ASSERT_EFI_ERROR (Status);
588 ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
589
590 //
591 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
592 // A constant BSP index makes no sense because it may be hot removed.
593 //
594 DEBUG_CODE (
595 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
596
597 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));
598 }
599 );
600
601 //
602 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
603 //
604 mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable);
605 DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));
606
607 //
608 // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.
609 // Make sure AddressEncMask is contained to smallest supported address field.
610 //
611 mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
612 DEBUG ((EFI_D_INFO, "mAddressEncMask = 0x%lx\n", mAddressEncMask));
613
614 //
615 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
616 //
617 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
618 mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
619 } else {
620 mMaxNumberOfCpus = mNumberOfCpus;
621 }
622 gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;
623
624 //
625 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
626 // allocated buffer. The minimum size of this buffer for a uniprocessor system
627 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
628 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
629 // then the SMI entry point and the CPU save state areas can be tiles to minimize
630 // the total amount SMRAM required for all the CPUs. The tile size can be computed
631 // by adding the // CPU save state size, any extra CPU specific context, and
632 // the size of code that must be placed at the SMI entry point to transfer
633 // control to a C function in the native SMM execution mode. This size is
634 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
635 // The total amount of memory required is the maximum number of CPUs that
636 // platform supports times the tile size. The picture below shows the tiling,
637 // where m is the number of tiles that fit in 32KB.
638 //
639 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
640 // | CPU m+1 Save State |
641 // +-----------------------------+
642 // | CPU m+1 Extra Data |
643 // +-----------------------------+
644 // | Padding |
645 // +-----------------------------+
646 // | CPU 2m SMI Entry |
647 // +#############################+ <-- Base of allocated buffer + 64 KB
648 // | CPU m-1 Save State |
649 // +-----------------------------+
650 // | CPU m-1 Extra Data |
651 // +-----------------------------+
652 // | Padding |
653 // +-----------------------------+
654 // | CPU 2m-1 SMI Entry |
655 // +=============================+ <-- 2^n offset from Base of allocated buffer
656 // | . . . . . . . . . . . . |
657 // +=============================+ <-- 2^n offset from Base of allocated buffer
658 // | CPU 2 Save State |
659 // +-----------------------------+
660 // | CPU 2 Extra Data |
661 // +-----------------------------+
662 // | Padding |
663 // +-----------------------------+
664 // | CPU m+1 SMI Entry |
665 // +=============================+ <-- Base of allocated buffer + 32 KB
666 // | CPU 1 Save State |
667 // +-----------------------------+
668 // | CPU 1 Extra Data |
669 // +-----------------------------+
670 // | Padding |
671 // +-----------------------------+
672 // | CPU m SMI Entry |
673 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
674 // | CPU 0 Save State |
675 // +-----------------------------+
676 // | CPU 0 Extra Data |
677 // +-----------------------------+
678 // | Padding |
679 // +-----------------------------+
680 // | CPU m-1 SMI Entry |
681 // +=============================+ <-- 2^n offset from Base of allocated buffer
682 // | . . . . . . . . . . . . |
683 // +=============================+ <-- 2^n offset from Base of allocated buffer
684 // | Padding |
685 // +-----------------------------+
686 // | CPU 1 SMI Entry |
687 // +=============================+ <-- 2^n offset from Base of allocated buffer
688 // | Padding |
689 // +-----------------------------+
690 // | CPU 0 SMI Entry |
691 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
692 //
693
694 //
695 // Retrieve CPU Family
696 //
697 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
698 FamilyId = (RegEax >> 8) & 0xf;
699 ModelId = (RegEax >> 4) & 0xf;
700 if (FamilyId == 0x06 || FamilyId == 0x0f) {
701 ModelId = ModelId | ((RegEax >> 12) & 0xf0);
702 }
703
704 RegEdx = 0;
705 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
706 if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
707 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
708 }
709 //
710 // Determine the mode of the CPU at the time an SMI occurs
711 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
712 // Volume 3C, Section 34.4.1.1
713 //
714 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
715 if ((RegEdx & BIT29) != 0) {
716 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
717 }
718 if (FamilyId == 0x06) {
719 if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) {
720 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
721 }
722 }
723
724 //
725 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
726 // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
727 // This size is rounded up to nearest power of 2.
728 //
729 TileCodeSize = GetSmiHandlerSize ();
730 TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
731 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
732 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
733 TileSize = TileDataSize + TileCodeSize - 1;
734 TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
735 DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
736
737 //
738 // If the TileSize is larger than space available for the SMI Handler of
739 // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save
740 // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then
741 // the SMI Handler size must be reduced or the size of the extra CPU specific
742 // context must be reduced.
743 //
744 ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));
745
746 //
747 // Allocate buffer for all of the tiles.
748 //
749 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
750 // Volume 3C, Section 34.11 SMBASE Relocation
751 // For Pentium and Intel486 processors, the SMBASE values must be
752 // aligned on a 32-KByte boundary or the processor will enter shutdown
753 // state during the execution of a RSM instruction.
754 //
755 // Intel486 processors: FamilyId is 4
756 // Pentium processors : FamilyId is 5
757 //
758 BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1));
759 if ((FamilyId == 4) || (FamilyId == 5)) {
760 Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB);
761 } else {
762 Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);
763 }
764 ASSERT (Buffer != NULL);
765 DEBUG ((EFI_D_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages)));
766
767 //
768 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
769 //
770 gSmmCpuPrivate->ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus);
771 ASSERT (gSmmCpuPrivate->ProcessorInfo != NULL);
772
773 gSmmCpuPrivate->Operation = (SMM_CPU_OPERATION *)AllocatePool (sizeof (SMM_CPU_OPERATION) * mMaxNumberOfCpus);
774 ASSERT (gSmmCpuPrivate->Operation != NULL);
775
776 gSmmCpuPrivate->CpuSaveStateSize = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);
777 ASSERT (gSmmCpuPrivate->CpuSaveStateSize != NULL);
778
779 gSmmCpuPrivate->CpuSaveState = (VOID **)AllocatePool (sizeof (VOID *) * mMaxNumberOfCpus);
780 ASSERT (gSmmCpuPrivate->CpuSaveState != NULL);
781
782 mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize;
783 mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState = gSmmCpuPrivate->CpuSaveState;
784
785 //
786 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
787 //
788 mCpuHotPlugData.ApicId = (UINT64 *)AllocatePool (sizeof (UINT64) * mMaxNumberOfCpus);
789 ASSERT (mCpuHotPlugData.ApicId != NULL);
790 mCpuHotPlugData.SmBase = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);
791 ASSERT (mCpuHotPlugData.SmBase != NULL);
792 mCpuHotPlugData.ArrayLength = (UINT32)mMaxNumberOfCpus;
793
794 //
795 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
796 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
797 // size for each CPU in the platform
798 //
799 for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
800 mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
801 gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP);
802 gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);
803 gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
804
805 if (Index < mNumberOfCpus) {
806 Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]);
807 ASSERT_EFI_ERROR (Status);
808 mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;
809
810 DEBUG ((EFI_D_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
811 Index,
812 (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,
813 mCpuHotPlugData.SmBase[Index],
814 gSmmCpuPrivate->CpuSaveState[Index],
815 gSmmCpuPrivate->CpuSaveStateSize[Index]
816 ));
817 } else {
818 gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID;
819 mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID;
820 }
821 }
822
823 //
824 // Allocate SMI stacks for all processors.
825 //
826 if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
827 //
828 // 2 more pages is allocated for each processor.
829 // one is guard page and the other is known good stack.
830 //
831 // +-------------------------------------------+-----+-------------------------------------------+
832 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
833 // +-------------------------------------------+-----+-------------------------------------------+
834 // | | | |
835 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
836 //
837 mSmmStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2);
838 Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2));
839 ASSERT (Stacks != NULL);
840 mSmmStackArrayBase = (UINTN)Stacks;
841 mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize - 1;
842 } else {
843 mSmmStackSize = PcdGet32 (PcdCpuSmmStackSize);
844 Stacks = (UINT8 *) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize));
845 ASSERT (Stacks != NULL);
846 }
847
848 //
849 // Set SMI stack for SMM base relocation
850 //
851 gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));
852
853 //
854 // Initialize IDT
855 //
856 InitializeSmmIdt ();
857
858 //
859 // Relocate SMM Base addresses to the ones allocated from SMRAM
860 //
861 mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus);
862 ASSERT (mRebased != NULL);
863 SmmRelocateBases ();
864
865 //
866 // Call hook for BSP to perform extra actions in normal mode after all
867 // SMM base addresses have been relocated on all CPUs
868 //
869 SmmCpuFeaturesSmmRelocationComplete ();
870
871 DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported));
872
873 //
874 // SMM Time initialization
875 //
876 InitializeSmmTimer ();
877
878 //
879 // Initialize MP globals
880 //
881 Cr3 = InitializeMpServiceData (Stacks, mSmmStackSize);
882
883 //
884 // Fill in SMM Reserved Regions
885 //
886 gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0;
887 gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize = 0;
888
889 //
890 // Install the SMM Configuration Protocol onto a new handle on the handle database.
891 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
892 // to an SMRAM address will be present in the handle database
893 //
894 Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (
895 &gSmmCpuPrivate->SmmCpuHandle,
896 &gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration,
897 NULL
898 );
899 ASSERT_EFI_ERROR (Status);
900
901 //
902 // Install the SMM CPU Protocol into SMM protocol database
903 //
904 Status = gSmst->SmmInstallProtocolInterface (
905 &mSmmCpuHandle,
906 &gEfiSmmCpuProtocolGuid,
907 EFI_NATIVE_INTERFACE,
908 &mSmmCpu
909 );
910 ASSERT_EFI_ERROR (Status);
911
912 //
913 // Install the SMM Memory Attribute Protocol into SMM protocol database
914 //
915 Status = gSmst->SmmInstallProtocolInterface (
916 &mSmmCpuHandle,
917 &gEdkiiSmmMemoryAttributeProtocolGuid,
918 EFI_NATIVE_INTERFACE,
919 &mSmmMemoryAttribute
920 );
921 ASSERT_EFI_ERROR (Status);
922
923 //
924 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
925 //
926 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
927 Status = PcdSet64S (PcdCpuHotPlugDataAddress, (UINT64)(UINTN)&mCpuHotPlugData);
928 ASSERT_EFI_ERROR (Status);
929 }
930
931 //
932 // Initialize SMM CPU Services Support
933 //
934 Status = InitializeSmmCpuServices (mSmmCpuHandle);
935 ASSERT_EFI_ERROR (Status);
936
937 //
938 // register SMM Ready To Lock Protocol notification
939 //
940 Status = gSmst->SmmRegisterProtocolNotify (
941 &gEfiSmmReadyToLockProtocolGuid,
942 SmmReadyToLockEventNotify,
943 &Registration
944 );
945 ASSERT_EFI_ERROR (Status);
946
947 //
948 // Initialize SMM Profile feature
949 //
950 InitSmmProfile (Cr3);
951
952 GetAcpiS3EnableFlag ();
953 InitSmmS3ResumeState (Cr3);
954
955 DEBUG ((EFI_D_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
956
957 return EFI_SUCCESS;
958 }
959
960 /**
961
962 Find out SMRAM information including SMRR base and SMRR size.
963
964 @param SmrrBase SMRR base
965 @param SmrrSize SMRR size
966
967 **/
968 VOID
969 FindSmramInfo (
970 OUT UINT32 *SmrrBase,
971 OUT UINT32 *SmrrSize
972 )
973 {
974 EFI_STATUS Status;
975 UINTN Size;
976 EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
977 EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;
978 UINTN Index;
979 UINT64 MaxSize;
980 BOOLEAN Found;
981
982 //
983 // Get SMM Access Protocol
984 //
985 Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);
986 ASSERT_EFI_ERROR (Status);
987
988 //
989 // Get SMRAM information
990 //
991 Size = 0;
992 Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);
993 ASSERT (Status == EFI_BUFFER_TOO_SMALL);
994
995 mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
996 ASSERT (mSmmCpuSmramRanges != NULL);
997
998 Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRanges);
999 ASSERT_EFI_ERROR (Status);
1000
1001 mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
1002
1003 //
1004 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
1005 //
1006 CurrentSmramRange = NULL;
1007 for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCpuSmramRangeCount; Index++) {
1008 //
1009 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
1010 //
1011 if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
1012 continue;
1013 }
1014
1015 if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {
1016 if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {
1017 if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {
1018 MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;
1019 CurrentSmramRange = &mSmmCpuSmramRanges[Index];
1020 }
1021 }
1022 }
1023 }
1024
1025 ASSERT (CurrentSmramRange != NULL);
1026
1027 *SmrrBase = (UINT32)CurrentSmramRange->CpuStart;
1028 *SmrrSize = (UINT32)CurrentSmramRange->PhysicalSize;
1029
1030 do {
1031 Found = FALSE;
1032 for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
1033 if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&
1034 *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) {
1035 *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;
1036 *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
1037 Found = TRUE;
1038 } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) {
1039 *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
1040 Found = TRUE;
1041 }
1042 }
1043 } while (Found);
1044
1045 DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));
1046 }
1047
1048 /**
1049 Configure SMM Code Access Check feature on an AP.
1050 SMM Feature Control MSR will be locked after configuration.
1051
1052 @param[in,out] Buffer Pointer to private data buffer.
1053 **/
1054 VOID
1055 EFIAPI
1056 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1057 IN OUT VOID *Buffer
1058 )
1059 {
1060 UINTN CpuIndex;
1061 UINT64 SmmFeatureControlMsr;
1062 UINT64 NewSmmFeatureControlMsr;
1063
1064 //
1065 // Retrieve the CPU Index from the context passed in
1066 //
1067 CpuIndex = *(UINTN *)Buffer;
1068
1069 //
1070 // Get the current SMM Feature Control MSR value
1071 //
1072 SmmFeatureControlMsr = SmmCpuFeaturesGetSmmRegister (CpuIndex, SmmRegFeatureControl);
1073
1074 //
1075 // Compute the new SMM Feature Control MSR value
1076 //
1077 NewSmmFeatureControlMsr = SmmFeatureControlMsr;
1078 if (mSmmCodeAccessCheckEnable) {
1079 NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT;
1080 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {
1081 NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT;
1082 }
1083 }
1084
1085 //
1086 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1087 //
1088 if (NewSmmFeatureControlMsr != SmmFeatureControlMsr) {
1089 SmmCpuFeaturesSetSmmRegister (CpuIndex, SmmRegFeatureControl, NewSmmFeatureControlMsr);
1090 }
1091
1092 //
1093 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1094 //
1095 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
1096 }
1097
1098 /**
1099 Configure SMM Code Access Check feature for all processors.
1100 SMM Feature Control MSR will be locked after configuration.
1101 **/
1102 VOID
1103 ConfigSmmCodeAccessCheck (
1104 VOID
1105 )
1106 {
1107 UINTN Index;
1108 EFI_STATUS Status;
1109
1110 //
1111 // Check to see if the Feature Control MSR is supported on this CPU
1112 //
1113 Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
1114 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) {
1115 mSmmCodeAccessCheckEnable = FALSE;
1116 return;
1117 }
1118
1119 //
1120 // Check to see if the CPU supports the SMM Code Access Check feature
1121 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1122 //
1123 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) {
1124 mSmmCodeAccessCheckEnable = FALSE;
1125 return;
1126 }
1127
1128 //
1129 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1130 //
1131 InitializeSpinLock (mConfigSmmCodeAccessCheckLock);
1132
1133 //
1134 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1135 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1136 //
1137 AcquireSpinLock (mConfigSmmCodeAccessCheckLock);
1138
1139 //
1140 // Enable SMM Code Access Check feature on the BSP.
1141 //
1142 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index);
1143
1144 //
1145 // Enable SMM Code Access Check feature for the APs.
1146 //
1147 for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
1148 if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {
1149 if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
1150 //
1151 // If this processor does not exist
1152 //
1153 continue;
1154 }
1155 //
1156 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1157 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1158 //
1159 AcquireSpinLock (mConfigSmmCodeAccessCheckLock);
1160
1161 //
1162 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1163 //
1164 Status = gSmst->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor, Index, &Index);
1165 ASSERT_EFI_ERROR (Status);
1166
1167 //
1168 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1169 //
1170 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock)) {
1171 CpuPause ();
1172 }
1173
1174 //
1175 // Release the Config SMM Code Access Check spin lock.
1176 //
1177 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
1178 }
1179 }
1180 }
1181
1182 /**
1183 This API provides a way to allocate memory for page table.
1184
1185 This API can be called more once to allocate memory for page tables.
1186
1187 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
1188 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
1189 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
1190 returned.
1191
1192 @param Pages The number of 4 KB pages to allocate.
1193
1194 @return A pointer to the allocated buffer or NULL if allocation fails.
1195
1196 **/
1197 VOID *
1198 AllocatePageTableMemory (
1199 IN UINTN Pages
1200 )
1201 {
1202 VOID *Buffer;
1203
1204 Buffer = SmmCpuFeaturesAllocatePageTableMemory (Pages);
1205 if (Buffer != NULL) {
1206 return Buffer;
1207 }
1208 return AllocatePages (Pages);
1209 }
1210
1211 /**
1212 Allocate pages for code.
1213
1214 @param[in] Pages Number of pages to be allocated.
1215
1216 @return Allocated memory.
1217 **/
1218 VOID *
1219 AllocateCodePages (
1220 IN UINTN Pages
1221 )
1222 {
1223 EFI_STATUS Status;
1224 EFI_PHYSICAL_ADDRESS Memory;
1225
1226 if (Pages == 0) {
1227 return NULL;
1228 }
1229
1230 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);
1231 if (EFI_ERROR (Status)) {
1232 return NULL;
1233 }
1234 return (VOID *) (UINTN) Memory;
1235 }
1236
1237 /**
1238 Allocate aligned pages for code.
1239
1240 @param[in] Pages Number of pages to be allocated.
1241 @param[in] Alignment The requested alignment of the allocation.
1242 Must be a power of two.
1243 If Alignment is zero, then byte alignment is used.
1244
1245 @return Allocated memory.
1246 **/
1247 VOID *
1248 AllocateAlignedCodePages (
1249 IN UINTN Pages,
1250 IN UINTN Alignment
1251 )
1252 {
1253 EFI_STATUS Status;
1254 EFI_PHYSICAL_ADDRESS Memory;
1255 UINTN AlignedMemory;
1256 UINTN AlignmentMask;
1257 UINTN UnalignedPages;
1258 UINTN RealPages;
1259
1260 //
1261 // Alignment must be a power of two or zero.
1262 //
1263 ASSERT ((Alignment & (Alignment - 1)) == 0);
1264
1265 if (Pages == 0) {
1266 return NULL;
1267 }
1268 if (Alignment > EFI_PAGE_SIZE) {
1269 //
1270 // Calculate the total number of pages since alignment is larger than page size.
1271 //
1272 AlignmentMask = Alignment - 1;
1273 RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
1274 //
1275 // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
1276 //
1277 ASSERT (RealPages > Pages);
1278
1279 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory);
1280 if (EFI_ERROR (Status)) {
1281 return NULL;
1282 }
1283 AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
1284 UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
1285 if (UnalignedPages > 0) {
1286 //
1287 // Free first unaligned page(s).
1288 //
1289 Status = gSmst->SmmFreePages (Memory, UnalignedPages);
1290 ASSERT_EFI_ERROR (Status);
1291 }
1292 Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);
1293 UnalignedPages = RealPages - Pages - UnalignedPages;
1294 if (UnalignedPages > 0) {
1295 //
1296 // Free last unaligned page(s).
1297 //
1298 Status = gSmst->SmmFreePages (Memory, UnalignedPages);
1299 ASSERT_EFI_ERROR (Status);
1300 }
1301 } else {
1302 //
1303 // Do not over-allocate pages in this case.
1304 //
1305 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);
1306 if (EFI_ERROR (Status)) {
1307 return NULL;
1308 }
1309 AlignedMemory = (UINTN) Memory;
1310 }
1311 return (VOID *) AlignedMemory;
1312 }
1313
1314 /**
1315 Perform the remaining tasks.
1316
1317 **/
1318 VOID
1319 PerformRemainingTasks (
1320 VOID
1321 )
1322 {
1323 if (mSmmReadyToLock) {
1324 //
1325 // Start SMM Profile feature
1326 //
1327 if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
1328 SmmProfileStart ();
1329 }
1330 //
1331 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1332 //
1333 InitPaging ();
1334
1335 //
1336 // Mark critical region to be read-only in page table
1337 //
1338 SetMemMapAttributes ();
1339
1340 //
1341 // For outside SMRAM, we only map SMM communication buffer or MMIO.
1342 //
1343 SetUefiMemMapAttributes ();
1344
1345 //
1346 // Set page table itself to be read-only
1347 //
1348 SetPageTableAttributes ();
1349
1350 //
1351 // Configure SMM Code Access Check feature if available.
1352 //
1353 ConfigSmmCodeAccessCheck ();
1354
1355 SmmCpuFeaturesCompleteSmmReadyToLock ();
1356
1357 //
1358 // Clean SMM ready to lock flag
1359 //
1360 mSmmReadyToLock = FALSE;
1361 }
1362 }
1363
1364 /**
1365 Perform the pre tasks.
1366
1367 **/
1368 VOID
1369 PerformPreTasks (
1370 VOID
1371 )
1372 {
1373 RestoreSmmConfigurationInS3 ();
1374 }
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