2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include "PiSmmCpuDxeSmm.h"
20 // SMM CPU Private Data structure that contains SMM Configuration Protocol
21 // along its supporting fields.
23 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData
= {
24 SMM_CPU_PRIVATE_DATA_SIGNATURE
, // Signature
26 NULL
, // Pointer to ProcessorInfo array
27 NULL
, // Pointer to Operation array
28 NULL
, // Pointer to CpuSaveStateSize array
29 NULL
, // Pointer to CpuSaveState array
30 { {0} }, // SmmReservedSmramRegion
32 SmmStartupThisAp
, // SmmCoreEntryContext.SmmStartupThisAp
33 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
34 0, // SmmCoreEntryContext.NumberOfCpus
35 NULL
, // SmmCoreEntryContext.CpuSaveStateSize
36 NULL
// SmmCoreEntryContext.CpuSaveState
40 mSmmCpuPrivateData
.SmmReservedSmramRegion
, // SmmConfiguration.SmramReservedRegions
41 RegisterSmmEntry
// SmmConfiguration.RegisterSmmEntry
45 CPU_HOT_PLUG_DATA mCpuHotPlugData
= {
46 CPU_HOT_PLUG_DATA_REVISION_1
, // Revision
47 0, // Array Length of SmBase and APIC ID
48 NULL
, // Pointer to APIC ID array
49 NULL
, // Pointer to SMBASE array
56 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
58 SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
= &mSmmCpuPrivateData
;
61 // SMM Relocation variables
63 volatile BOOLEAN
*mRebased
;
64 volatile BOOLEAN mIsBsp
;
67 /// Handle for the SMM CPU Protocol
69 EFI_HANDLE mSmmCpuHandle
= NULL
;
72 /// SMM CPU Protocol instance
74 EFI_SMM_CPU_PROTOCOL mSmmCpu
= {
79 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable
[EXCEPTION_VECTOR_NUMBER
];
82 // SMM stack information
84 UINTN mSmmStackArrayBase
;
85 UINTN mSmmStackArrayEnd
;
88 UINTN mMaxNumberOfCpus
= 1;
89 UINTN mNumberOfCpus
= 1;
92 // SMM ready to lock flag
94 BOOLEAN mSmmReadyToLock
= FALSE
;
97 // Global used to cache PCD for SMM Code Access Check enable
99 BOOLEAN mSmmCodeAccessCheckEnable
= FALSE
;
102 // Global copy of the PcdPteMemoryEncryptionAddressOrMask
104 UINT64 mAddressEncMask
= 0;
107 // Spin lock used to serialize setting of SMM Code Access Check feature
109 SPIN_LOCK
*mConfigSmmCodeAccessCheckLock
= NULL
;
112 // Saved SMM ranges information
114 EFI_SMRAM_DESCRIPTOR
*mSmmCpuSmramRanges
;
115 UINTN mSmmCpuSmramRangeCount
;
117 UINT8 mPhysicalAddressBits
;
120 Initialize IDT to setup exception handlers for SMM.
129 BOOLEAN InterruptState
;
130 IA32_DESCRIPTOR DxeIdtr
;
133 // There are 32 (not 255) entries in it since only processor
134 // generated exceptions will be handled.
136 gcSmiIdtr
.Limit
= (sizeof(IA32_IDT_GATE_DESCRIPTOR
) * 32) - 1;
138 // Allocate page aligned IDT, because it might be set as read only.
140 gcSmiIdtr
.Base
= (UINTN
)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr
.Limit
+ 1));
141 ASSERT (gcSmiIdtr
.Base
!= 0);
142 ZeroMem ((VOID
*)gcSmiIdtr
.Base
, gcSmiIdtr
.Limit
+ 1);
145 // Disable Interrupt and save DXE IDT table
147 InterruptState
= SaveAndDisableInterrupts ();
148 AsmReadIdtr (&DxeIdtr
);
150 // Load SMM temporary IDT table
152 AsmWriteIdtr (&gcSmiIdtr
);
154 // Setup SMM default exception handlers, SMM IDT table
155 // will be updated and saved in gcSmiIdtr
157 Status
= InitializeCpuExceptionHandlers (NULL
);
158 ASSERT_EFI_ERROR (Status
);
160 // Restore DXE IDT table and CPU interrupt
162 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &DxeIdtr
);
163 SetInterruptState (InterruptState
);
167 Search module name by input IP address and output it.
169 @param CallerIpAddress Caller instruction pointer.
174 IN UINTN CallerIpAddress
183 Pe32Data
= PeCoffSearchImageBase (CallerIpAddress
);
185 DEBUG ((DEBUG_ERROR
, "It is invoked from the instruction before IP(0x%p)", (VOID
*) CallerIpAddress
));
186 PdbPointer
= PeCoffLoaderGetPdbPointer ((VOID
*) Pe32Data
);
187 if (PdbPointer
!= NULL
) {
188 DEBUG ((DEBUG_ERROR
, " in module (%a)\n", PdbPointer
));
194 Read information from the CPU save state.
196 @param This EFI_SMM_CPU_PROTOCOL instance
197 @param Width The number of bytes to read from the CPU save state.
198 @param Register Specifies the CPU register to read form the save state.
199 @param CpuIndex Specifies the zero-based index of the CPU save state.
200 @param Buffer Upon return, this holds the CPU register value read from the save state.
202 @retval EFI_SUCCESS The register was read from Save State
203 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
204 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
210 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
212 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
220 // Retrieve pointer to the specified CPU's SMM Save State buffer
222 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
223 return EFI_INVALID_PARAMETER
;
227 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
229 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
231 // The pseudo-register only supports the 64-bit size specified by Width.
233 if (Width
!= sizeof (UINT64
)) {
234 return EFI_INVALID_PARAMETER
;
237 // If the processor is in SMM at the time the SMI occurred,
238 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
239 // Otherwise, EFI_NOT_FOUND is returned.
241 if (*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
)) {
242 *(UINT64
*)Buffer
= gSmmCpuPrivate
->ProcessorInfo
[CpuIndex
].ProcessorId
;
245 return EFI_NOT_FOUND
;
249 if (!(*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
))) {
250 return EFI_INVALID_PARAMETER
;
253 Status
= SmmCpuFeaturesReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
254 if (Status
== EFI_UNSUPPORTED
) {
255 Status
= ReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
261 Write data to the CPU save state.
263 @param This EFI_SMM_CPU_PROTOCOL instance
264 @param Width The number of bytes to read from the CPU save state.
265 @param Register Specifies the CPU register to write to the save state.
266 @param CpuIndex Specifies the zero-based index of the CPU save state
267 @param Buffer Upon entry, this holds the new CPU register value.
269 @retval EFI_SUCCESS The register was written from Save State
270 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
271 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
277 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
279 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
281 IN CONST VOID
*Buffer
287 // Retrieve pointer to the specified CPU's SMM Save State buffer
289 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
290 return EFI_INVALID_PARAMETER
;
294 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
296 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
300 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
301 return EFI_INVALID_PARAMETER
;
304 Status
= SmmCpuFeaturesWriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
305 if (Status
== EFI_UNSUPPORTED
) {
306 Status
= WriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
313 C function for SMI handler. To change all processor's SMMBase Register.
326 // Update SMM IDT entries' code segment and load IDT
328 AsmWriteIdtr (&gcSmiIdtr
);
329 ApicId
= GetApicId ();
331 ASSERT (mNumberOfCpus
<= mMaxNumberOfCpus
);
333 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
334 if (ApicId
== (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
336 // Initialize SMM specific features on the currently executing CPU
338 SmmCpuFeaturesInitializeProcessor (
341 gSmmCpuPrivate
->ProcessorInfo
,
347 // Check XD and BTS features on each processor on normal boot
349 CheckFeatureSupported ();
354 // BSP rebase is already done above.
355 // Initialize private data during S3 resume
357 InitializeMpSyncData ();
361 // Hook return after RSM to set SMM re-based flag
363 SemaphoreHook (Index
, &mRebased
[Index
]);
372 Relocate SmmBases for each processor.
374 Execute on first boot and all S3 resumes
383 UINT8 BakBuf
[BACK_BUF_SIZE
];
384 SMRAM_SAVE_STATE_MAP BakBuf2
;
385 SMRAM_SAVE_STATE_MAP
*CpuStatePtr
;
392 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
394 ASSERT (sizeof (BakBuf
) >= gcSmmInitSize
);
397 // Patch ASM code template with current CR0, CR3, and CR4 values
399 gSmmCr0
= (UINT32
)AsmReadCr0 ();
400 gSmmCr3
= (UINT32
)AsmReadCr3 ();
401 gSmmCr4
= (UINT32
)AsmReadCr4 ();
404 // Patch GDTR for SMM base relocation
406 gcSmiInitGdtr
.Base
= gcSmiGdtr
.Base
;
407 gcSmiInitGdtr
.Limit
= gcSmiGdtr
.Limit
;
409 U8Ptr
= (UINT8
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMM_HANDLER_OFFSET
);
410 CpuStatePtr
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
413 // Backup original contents at address 0x38000
415 CopyMem (BakBuf
, U8Ptr
, sizeof (BakBuf
));
416 CopyMem (&BakBuf2
, CpuStatePtr
, sizeof (BakBuf2
));
419 // Load image for relocation
421 CopyMem (U8Ptr
, gcSmmInitTemplate
, gcSmmInitSize
);
424 // Retrieve the local APIC ID of current processor
426 ApicId
= GetApicId ();
429 // Relocate SM bases for all APs
430 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
433 BspIndex
= (UINTN
)-1;
434 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
435 mRebased
[Index
] = FALSE
;
436 if (ApicId
!= (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
437 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
439 // Wait for this AP to finish its 1st SMI
441 while (!mRebased
[Index
]);
444 // BSP will be Relocated later
451 // Relocate BSP's SMM base
453 ASSERT (BspIndex
!= (UINTN
)-1);
457 // Wait for the BSP to finish its 1st SMI
459 while (!mRebased
[BspIndex
]);
462 // Restore contents at address 0x38000
464 CopyMem (CpuStatePtr
, &BakBuf2
, sizeof (BakBuf2
));
465 CopyMem (U8Ptr
, BakBuf
, sizeof (BakBuf
));
469 SMM Ready To Lock event notification handler.
471 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
472 perform additional lock actions that must be performed from SMM on the next SMI.
474 @param[in] Protocol Points to the protocol's unique identifier.
475 @param[in] Interface Points to the interface instance.
476 @param[in] Handle The handle on which the interface was installed.
478 @retval EFI_SUCCESS Notification handler runs successfully.
482 SmmReadyToLockEventNotify (
483 IN CONST EFI_GUID
*Protocol
,
491 // Cache a copy of UEFI memory map before we start profiling feature.
496 // Set SMM ready to lock flag and return
498 mSmmReadyToLock
= TRUE
;
503 The module Entry Point of the CPU SMM driver.
505 @param ImageHandle The firmware allocated handle for the EFI image.
506 @param SystemTable A pointer to the EFI System Table.
508 @retval EFI_SUCCESS The entry point is executed successfully.
509 @retval Other Some error occurs when executing this entry point.
515 IN EFI_HANDLE ImageHandle
,
516 IN EFI_SYSTEM_TABLE
*SystemTable
520 EFI_MP_SERVICES_PROTOCOL
*MpServices
;
521 UINTN NumberOfEnabledProcessors
;
537 // Initialize Debug Agent to support source level debug in SMM code
539 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM
, NULL
, NULL
);
542 // Report the start of CPU SMM initialization.
546 EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_INIT
550 // Fix segment address of the long-mode-switch jump
552 if (sizeof (UINTN
) == sizeof (UINT64
)) {
553 gSmmJmpAddr
.Segment
= LONG_MODE_CODE_SEGMENT
;
557 // Find out SMRR Base and SMRR Size
559 FindSmramInfo (&mCpuHotPlugData
.SmrrBase
, &mCpuHotPlugData
.SmrrSize
);
562 // Get MP Services Protocol
564 Status
= SystemTable
->BootServices
->LocateProtocol (&gEfiMpServiceProtocolGuid
, NULL
, (VOID
**)&MpServices
);
565 ASSERT_EFI_ERROR (Status
);
568 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
570 Status
= MpServices
->GetNumberOfProcessors (MpServices
, &mNumberOfCpus
, &NumberOfEnabledProcessors
);
571 ASSERT_EFI_ERROR (Status
);
572 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
575 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
576 // A constant BSP index makes no sense because it may be hot removed.
579 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
581 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection
));
586 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
588 mSmmCodeAccessCheckEnable
= PcdGetBool (PcdCpuSmmCodeAccessCheckEnable
);
589 DEBUG ((EFI_D_INFO
, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable
));
592 // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.
593 // Make sure AddressEncMask is contained to smallest supported address field.
595 mAddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
596 DEBUG ((EFI_D_INFO
, "mAddressEncMask = 0x%lx\n", mAddressEncMask
));
599 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
601 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
602 mMaxNumberOfCpus
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
604 mMaxNumberOfCpus
= mNumberOfCpus
;
606 gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
= mMaxNumberOfCpus
;
609 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
610 // allocated buffer. The minimum size of this buffer for a uniprocessor system
611 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
612 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
613 // then the SMI entry point and the CPU save state areas can be tiles to minimize
614 // the total amount SMRAM required for all the CPUs. The tile size can be computed
615 // by adding the // CPU save state size, any extra CPU specific context, and
616 // the size of code that must be placed at the SMI entry point to transfer
617 // control to a C function in the native SMM execution mode. This size is
618 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
619 // The total amount of memory required is the maximum number of CPUs that
620 // platform supports times the tile size. The picture below shows the tiling,
621 // where m is the number of tiles that fit in 32KB.
623 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
624 // | CPU m+1 Save State |
625 // +-----------------------------+
626 // | CPU m+1 Extra Data |
627 // +-----------------------------+
629 // +-----------------------------+
630 // | CPU 2m SMI Entry |
631 // +#############################+ <-- Base of allocated buffer + 64 KB
632 // | CPU m-1 Save State |
633 // +-----------------------------+
634 // | CPU m-1 Extra Data |
635 // +-----------------------------+
637 // +-----------------------------+
638 // | CPU 2m-1 SMI Entry |
639 // +=============================+ <-- 2^n offset from Base of allocated buffer
640 // | . . . . . . . . . . . . |
641 // +=============================+ <-- 2^n offset from Base of allocated buffer
642 // | CPU 2 Save State |
643 // +-----------------------------+
644 // | CPU 2 Extra Data |
645 // +-----------------------------+
647 // +-----------------------------+
648 // | CPU m+1 SMI Entry |
649 // +=============================+ <-- Base of allocated buffer + 32 KB
650 // | CPU 1 Save State |
651 // +-----------------------------+
652 // | CPU 1 Extra Data |
653 // +-----------------------------+
655 // +-----------------------------+
656 // | CPU m SMI Entry |
657 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
658 // | CPU 0 Save State |
659 // +-----------------------------+
660 // | CPU 0 Extra Data |
661 // +-----------------------------+
663 // +-----------------------------+
664 // | CPU m-1 SMI Entry |
665 // +=============================+ <-- 2^n offset from Base of allocated buffer
666 // | . . . . . . . . . . . . |
667 // +=============================+ <-- 2^n offset from Base of allocated buffer
669 // +-----------------------------+
670 // | CPU 1 SMI Entry |
671 // +=============================+ <-- 2^n offset from Base of allocated buffer
673 // +-----------------------------+
674 // | CPU 0 SMI Entry |
675 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
679 // Retrieve CPU Family
681 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, NULL
);
682 FamilyId
= (RegEax
>> 8) & 0xf;
683 ModelId
= (RegEax
>> 4) & 0xf;
684 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
685 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
689 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
690 if (RegEax
>= CPUID_EXTENDED_CPU_SIG
) {
691 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
694 // Determine the mode of the CPU at the time an SMI occurs
695 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
696 // Volume 3C, Section 34.4.1.1
698 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
;
699 if ((RegEdx
& BIT29
) != 0) {
700 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
702 if (FamilyId
== 0x06) {
703 if (ModelId
== 0x17 || ModelId
== 0x0f || ModelId
== 0x1c) {
704 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
709 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
710 // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
711 // This size is rounded up to nearest power of 2.
713 TileCodeSize
= GetSmiHandlerSize ();
714 TileCodeSize
= ALIGN_VALUE(TileCodeSize
, SIZE_4KB
);
715 TileDataSize
= (SMRAM_SAVE_STATE_MAP_OFFSET
- SMM_PSD_OFFSET
) + sizeof (SMRAM_SAVE_STATE_MAP
);
716 TileDataSize
= ALIGN_VALUE(TileDataSize
, SIZE_4KB
);
717 TileSize
= TileDataSize
+ TileCodeSize
- 1;
718 TileSize
= 2 * GetPowerOfTwo32 ((UINT32
)TileSize
);
719 DEBUG ((EFI_D_INFO
, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize
, TileCodeSize
, TileDataSize
));
722 // If the TileSize is larger than space available for the SMI Handler of
723 // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save
724 // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then
725 // the SMI Handler size must be reduced or the size of the extra CPU specific
726 // context must be reduced.
728 ASSERT (TileSize
<= (SMRAM_SAVE_STATE_MAP_OFFSET
+ sizeof (SMRAM_SAVE_STATE_MAP
) - SMM_HANDLER_OFFSET
));
731 // Allocate buffer for all of the tiles.
733 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
734 // Volume 3C, Section 34.11 SMBASE Relocation
735 // For Pentium and Intel486 processors, the SMBASE values must be
736 // aligned on a 32-KByte boundary or the processor will enter shutdown
737 // state during the execution of a RSM instruction.
739 // Intel486 processors: FamilyId is 4
740 // Pentium processors : FamilyId is 5
742 BufferPages
= EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1));
743 if ((FamilyId
== 4) || (FamilyId
== 5)) {
744 Buffer
= AllocateAlignedCodePages (BufferPages
, SIZE_32KB
);
746 Buffer
= AllocateAlignedCodePages (BufferPages
, SIZE_4KB
);
748 ASSERT (Buffer
!= NULL
);
749 DEBUG ((EFI_D_INFO
, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer
, EFI_PAGES_TO_SIZE(BufferPages
)));
752 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
754 gSmmCpuPrivate
->ProcessorInfo
= (EFI_PROCESSOR_INFORMATION
*)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION
) * mMaxNumberOfCpus
);
755 ASSERT (gSmmCpuPrivate
->ProcessorInfo
!= NULL
);
757 gSmmCpuPrivate
->Operation
= (SMM_CPU_OPERATION
*)AllocatePool (sizeof (SMM_CPU_OPERATION
) * mMaxNumberOfCpus
);
758 ASSERT (gSmmCpuPrivate
->Operation
!= NULL
);
760 gSmmCpuPrivate
->CpuSaveStateSize
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
761 ASSERT (gSmmCpuPrivate
->CpuSaveStateSize
!= NULL
);
763 gSmmCpuPrivate
->CpuSaveState
= (VOID
**)AllocatePool (sizeof (VOID
*) * mMaxNumberOfCpus
);
764 ASSERT (gSmmCpuPrivate
->CpuSaveState
!= NULL
);
766 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveStateSize
= gSmmCpuPrivate
->CpuSaveStateSize
;
767 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveState
= gSmmCpuPrivate
->CpuSaveState
;
770 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
772 mCpuHotPlugData
.ApicId
= (UINT64
*)AllocatePool (sizeof (UINT64
) * mMaxNumberOfCpus
);
773 ASSERT (mCpuHotPlugData
.ApicId
!= NULL
);
774 mCpuHotPlugData
.SmBase
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
775 ASSERT (mCpuHotPlugData
.SmBase
!= NULL
);
776 mCpuHotPlugData
.ArrayLength
= (UINT32
)mMaxNumberOfCpus
;
779 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
780 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
781 // size for each CPU in the platform
783 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
784 mCpuHotPlugData
.SmBase
[Index
] = (UINTN
)Buffer
+ Index
* TileSize
- SMM_HANDLER_OFFSET
;
785 gSmmCpuPrivate
->CpuSaveStateSize
[Index
] = sizeof(SMRAM_SAVE_STATE_MAP
);
786 gSmmCpuPrivate
->CpuSaveState
[Index
] = (VOID
*)(mCpuHotPlugData
.SmBase
[Index
] + SMRAM_SAVE_STATE_MAP_OFFSET
);
787 gSmmCpuPrivate
->Operation
[Index
] = SmmCpuNone
;
789 if (Index
< mNumberOfCpus
) {
790 Status
= MpServices
->GetProcessorInfo (MpServices
, Index
, &gSmmCpuPrivate
->ProcessorInfo
[Index
]);
791 ASSERT_EFI_ERROR (Status
);
792 mCpuHotPlugData
.ApicId
[Index
] = gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
;
794 DEBUG ((EFI_D_INFO
, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
796 (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
,
797 mCpuHotPlugData
.SmBase
[Index
],
798 gSmmCpuPrivate
->CpuSaveState
[Index
],
799 gSmmCpuPrivate
->CpuSaveStateSize
[Index
]
802 gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
= INVALID_APIC_ID
;
803 mCpuHotPlugData
.ApicId
[Index
] = INVALID_APIC_ID
;
808 // Allocate SMI stacks for all processors.
810 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
812 // 2 more pages is allocated for each processor.
813 // one is guard page and the other is known good stack.
815 // +-------------------------------------------+-----+-------------------------------------------+
816 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
817 // +-------------------------------------------+-----+-------------------------------------------+
819 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
821 mSmmStackSize
= EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2);
822 Stacks
= (UINT8
*) AllocatePages (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2));
823 ASSERT (Stacks
!= NULL
);
824 mSmmStackArrayBase
= (UINTN
)Stacks
;
825 mSmmStackArrayEnd
= mSmmStackArrayBase
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
- 1;
827 mSmmStackSize
= PcdGet32 (PcdCpuSmmStackSize
);
828 Stacks
= (UINT8
*) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
));
829 ASSERT (Stacks
!= NULL
);
833 // Set SMI stack for SMM base relocation
835 gSmmInitStack
= (UINTN
) (Stacks
+ mSmmStackSize
- sizeof (UINTN
));
843 // Relocate SMM Base addresses to the ones allocated from SMRAM
845 mRebased
= (BOOLEAN
*)AllocateZeroPool (sizeof (BOOLEAN
) * mMaxNumberOfCpus
);
846 ASSERT (mRebased
!= NULL
);
850 // Call hook for BSP to perform extra actions in normal mode after all
851 // SMM base addresses have been relocated on all CPUs
853 SmmCpuFeaturesSmmRelocationComplete ();
855 DEBUG ((DEBUG_INFO
, "mXdSupported - 0x%x\n", mXdSupported
));
858 // SMM Time initialization
860 InitializeSmmTimer ();
863 // Initialize MP globals
865 Cr3
= InitializeMpServiceData (Stacks
, mSmmStackSize
);
868 // Fill in SMM Reserved Regions
870 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedStart
= 0;
871 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedSize
= 0;
874 // Install the SMM Configuration Protocol onto a new handle on the handle database.
875 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
876 // to an SMRAM address will be present in the handle database
878 Status
= SystemTable
->BootServices
->InstallMultipleProtocolInterfaces (
879 &gSmmCpuPrivate
->SmmCpuHandle
,
880 &gEfiSmmConfigurationProtocolGuid
, &gSmmCpuPrivate
->SmmConfiguration
,
883 ASSERT_EFI_ERROR (Status
);
886 // Install the SMM CPU Protocol into SMM protocol database
888 Status
= gSmst
->SmmInstallProtocolInterface (
890 &gEfiSmmCpuProtocolGuid
,
891 EFI_NATIVE_INTERFACE
,
894 ASSERT_EFI_ERROR (Status
);
897 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
899 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
900 Status
= PcdSet64S (PcdCpuHotPlugDataAddress
, (UINT64
)(UINTN
)&mCpuHotPlugData
);
901 ASSERT_EFI_ERROR (Status
);
905 // Initialize SMM CPU Services Support
907 Status
= InitializeSmmCpuServices (mSmmCpuHandle
);
908 ASSERT_EFI_ERROR (Status
);
911 // register SMM Ready To Lock Protocol notification
913 Status
= gSmst
->SmmRegisterProtocolNotify (
914 &gEfiSmmReadyToLockProtocolGuid
,
915 SmmReadyToLockEventNotify
,
918 ASSERT_EFI_ERROR (Status
);
921 // Initialize SMM Profile feature
923 InitSmmProfile (Cr3
);
925 GetAcpiS3EnableFlag ();
926 InitSmmS3ResumeState (Cr3
);
928 DEBUG ((EFI_D_INFO
, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
935 Find out SMRAM information including SMRR base and SMRR size.
937 @param SmrrBase SMRR base
938 @param SmrrSize SMRR size
943 OUT UINT32
*SmrrBase
,
949 EFI_SMM_ACCESS2_PROTOCOL
*SmmAccess
;
950 EFI_SMRAM_DESCRIPTOR
*CurrentSmramRange
;
956 // Get SMM Access Protocol
958 Status
= gBS
->LocateProtocol (&gEfiSmmAccess2ProtocolGuid
, NULL
, (VOID
**)&SmmAccess
);
959 ASSERT_EFI_ERROR (Status
);
962 // Get SMRAM information
965 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, NULL
);
966 ASSERT (Status
== EFI_BUFFER_TOO_SMALL
);
968 mSmmCpuSmramRanges
= (EFI_SMRAM_DESCRIPTOR
*)AllocatePool (Size
);
969 ASSERT (mSmmCpuSmramRanges
!= NULL
);
971 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, mSmmCpuSmramRanges
);
972 ASSERT_EFI_ERROR (Status
);
974 mSmmCpuSmramRangeCount
= Size
/ sizeof (EFI_SMRAM_DESCRIPTOR
);
977 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
979 CurrentSmramRange
= NULL
;
980 for (Index
= 0, MaxSize
= SIZE_256KB
- EFI_PAGE_SIZE
; Index
< mSmmCpuSmramRangeCount
; Index
++) {
982 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
984 if ((mSmmCpuSmramRanges
[Index
].RegionState
& (EFI_ALLOCATED
| EFI_NEEDS_TESTING
| EFI_NEEDS_ECC_INITIALIZATION
)) != 0) {
988 if (mSmmCpuSmramRanges
[Index
].CpuStart
>= BASE_1MB
) {
989 if ((mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
) <= SMRR_MAX_ADDRESS
) {
990 if (mSmmCpuSmramRanges
[Index
].PhysicalSize
>= MaxSize
) {
991 MaxSize
= mSmmCpuSmramRanges
[Index
].PhysicalSize
;
992 CurrentSmramRange
= &mSmmCpuSmramRanges
[Index
];
998 ASSERT (CurrentSmramRange
!= NULL
);
1000 *SmrrBase
= (UINT32
)CurrentSmramRange
->CpuStart
;
1001 *SmrrSize
= (UINT32
)CurrentSmramRange
->PhysicalSize
;
1005 for (Index
= 0; Index
< mSmmCpuSmramRangeCount
; Index
++) {
1006 if (mSmmCpuSmramRanges
[Index
].CpuStart
< *SmrrBase
&&
1007 *SmrrBase
== (mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
)) {
1008 *SmrrBase
= (UINT32
)mSmmCpuSmramRanges
[Index
].CpuStart
;
1009 *SmrrSize
= (UINT32
)(*SmrrSize
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
);
1011 } else if ((*SmrrBase
+ *SmrrSize
) == mSmmCpuSmramRanges
[Index
].CpuStart
&& mSmmCpuSmramRanges
[Index
].PhysicalSize
> 0) {
1012 *SmrrSize
= (UINT32
)(*SmrrSize
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
);
1018 DEBUG ((EFI_D_INFO
, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase
, *SmrrSize
));
1022 Configure SMM Code Access Check feature on an AP.
1023 SMM Feature Control MSR will be locked after configuration.
1025 @param[in,out] Buffer Pointer to private data buffer.
1029 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1034 UINT64 SmmFeatureControlMsr
;
1035 UINT64 NewSmmFeatureControlMsr
;
1038 // Retrieve the CPU Index from the context passed in
1040 CpuIndex
= *(UINTN
*)Buffer
;
1043 // Get the current SMM Feature Control MSR value
1045 SmmFeatureControlMsr
= SmmCpuFeaturesGetSmmRegister (CpuIndex
, SmmRegFeatureControl
);
1048 // Compute the new SMM Feature Control MSR value
1050 NewSmmFeatureControlMsr
= SmmFeatureControlMsr
;
1051 if (mSmmCodeAccessCheckEnable
) {
1052 NewSmmFeatureControlMsr
|= SMM_CODE_CHK_EN_BIT
;
1053 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1054 NewSmmFeatureControlMsr
|= SMM_FEATURE_CONTROL_LOCK_BIT
;
1059 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1061 if (NewSmmFeatureControlMsr
!= SmmFeatureControlMsr
) {
1062 SmmCpuFeaturesSetSmmRegister (CpuIndex
, SmmRegFeatureControl
, NewSmmFeatureControlMsr
);
1066 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1068 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1072 Configure SMM Code Access Check feature for all processors.
1073 SMM Feature Control MSR will be locked after configuration.
1076 ConfigSmmCodeAccessCheck (
1084 // Check to see if the Feature Control MSR is supported on this CPU
1086 Index
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1087 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index
, SmmRegFeatureControl
)) {
1088 mSmmCodeAccessCheckEnable
= FALSE
;
1093 // Check to see if the CPU supports the SMM Code Access Check feature
1094 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1096 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP
) & SMM_CODE_ACCESS_CHK_BIT
) == 0) {
1097 mSmmCodeAccessCheckEnable
= FALSE
;
1102 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1104 InitializeSpinLock (mConfigSmmCodeAccessCheckLock
);
1107 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1108 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1110 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1113 // Enable SMM Code Access Check feature on the BSP.
1115 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index
);
1118 // Enable SMM Code Access Check feature for the APs.
1120 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1121 if (Index
!= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
) {
1122 if (gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
== INVALID_APIC_ID
) {
1124 // If this processor does not exist
1129 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1130 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1132 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1135 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1137 Status
= gSmst
->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor
, Index
, &Index
);
1138 ASSERT_EFI_ERROR (Status
);
1141 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1143 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock
)) {
1148 // Release the Config SMM Code Access Check spin lock.
1150 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1156 This API provides a way to allocate memory for page table.
1158 This API can be called more once to allocate memory for page tables.
1160 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
1161 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
1162 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
1165 @param Pages The number of 4 KB pages to allocate.
1167 @return A pointer to the allocated buffer or NULL if allocation fails.
1171 AllocatePageTableMemory (
1177 Buffer
= SmmCpuFeaturesAllocatePageTableMemory (Pages
);
1178 if (Buffer
!= NULL
) {
1181 return AllocatePages (Pages
);
1185 Allocate pages for code.
1187 @param[in] Pages Number of pages to be allocated.
1189 @return Allocated memory.
1197 EFI_PHYSICAL_ADDRESS Memory
;
1203 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, Pages
, &Memory
);
1204 if (EFI_ERROR (Status
)) {
1207 return (VOID
*) (UINTN
) Memory
;
1211 Allocate aligned pages for code.
1213 @param[in] Pages Number of pages to be allocated.
1214 @param[in] Alignment The requested alignment of the allocation.
1215 Must be a power of two.
1216 If Alignment is zero, then byte alignment is used.
1218 @return Allocated memory.
1221 AllocateAlignedCodePages (
1227 EFI_PHYSICAL_ADDRESS Memory
;
1228 UINTN AlignedMemory
;
1229 UINTN AlignmentMask
;
1230 UINTN UnalignedPages
;
1234 // Alignment must be a power of two or zero.
1236 ASSERT ((Alignment
& (Alignment
- 1)) == 0);
1241 if (Alignment
> EFI_PAGE_SIZE
) {
1243 // Calculate the total number of pages since alignment is larger than page size.
1245 AlignmentMask
= Alignment
- 1;
1246 RealPages
= Pages
+ EFI_SIZE_TO_PAGES (Alignment
);
1248 // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
1250 ASSERT (RealPages
> Pages
);
1252 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, RealPages
, &Memory
);
1253 if (EFI_ERROR (Status
)) {
1256 AlignedMemory
= ((UINTN
) Memory
+ AlignmentMask
) & ~AlignmentMask
;
1257 UnalignedPages
= EFI_SIZE_TO_PAGES (AlignedMemory
- (UINTN
) Memory
);
1258 if (UnalignedPages
> 0) {
1260 // Free first unaligned page(s).
1262 Status
= gSmst
->SmmFreePages (Memory
, UnalignedPages
);
1263 ASSERT_EFI_ERROR (Status
);
1265 Memory
= AlignedMemory
+ EFI_PAGES_TO_SIZE (Pages
);
1266 UnalignedPages
= RealPages
- Pages
- UnalignedPages
;
1267 if (UnalignedPages
> 0) {
1269 // Free last unaligned page(s).
1271 Status
= gSmst
->SmmFreePages (Memory
, UnalignedPages
);
1272 ASSERT_EFI_ERROR (Status
);
1276 // Do not over-allocate pages in this case.
1278 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, Pages
, &Memory
);
1279 if (EFI_ERROR (Status
)) {
1282 AlignedMemory
= (UINTN
) Memory
;
1284 return (VOID
*) AlignedMemory
;
1288 Perform the remaining tasks.
1292 PerformRemainingTasks (
1296 if (mSmmReadyToLock
) {
1298 // Start SMM Profile feature
1300 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1304 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1309 // Mark critical region to be read-only in page table
1311 SetMemMapAttributes ();
1314 // For outside SMRAM, we only map SMM communication buffer or MMIO.
1316 SetUefiMemMapAttributes ();
1319 // Set page table itself to be read-only
1321 SetPageTableAttributes ();
1324 // Configure SMM Code Access Check feature if available.
1326 ConfigSmmCodeAccessCheck ();
1328 SmmCpuFeaturesCompleteSmmReadyToLock ();
1331 // Clean SMM ready to lock flag
1333 mSmmReadyToLock
= FALSE
;
1338 Perform the pre tasks.
1346 RestoreSmmConfigurationInS3 ();