2d6b572b4e3f3b482cf5218c4eee72e1d477760e
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c
1 /** @file
2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
3
4 Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
6
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #include "PiSmmCpuDxeSmm.h"
18
19 //
20 // SMM CPU Private Data structure that contains SMM Configuration Protocol
21 // along its supporting fields.
22 //
23 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = {
24 SMM_CPU_PRIVATE_DATA_SIGNATURE, // Signature
25 NULL, // SmmCpuHandle
26 NULL, // Pointer to ProcessorInfo array
27 NULL, // Pointer to Operation array
28 NULL, // Pointer to CpuSaveStateSize array
29 NULL, // Pointer to CpuSaveState array
30 { {0} }, // SmmReservedSmramRegion
31 {
32 SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp
33 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
34 0, // SmmCoreEntryContext.NumberOfCpus
35 NULL, // SmmCoreEntryContext.CpuSaveStateSize
36 NULL // SmmCoreEntryContext.CpuSaveState
37 },
38 NULL, // SmmCoreEntry
39 {
40 mSmmCpuPrivateData.SmmReservedSmramRegion, // SmmConfiguration.SmramReservedRegions
41 RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry
42 },
43 };
44
45 CPU_HOT_PLUG_DATA mCpuHotPlugData = {
46 CPU_HOT_PLUG_DATA_REVISION_1, // Revision
47 0, // Array Length of SmBase and APIC ID
48 NULL, // Pointer to APIC ID array
49 NULL, // Pointer to SMBASE array
50 0, // Reserved
51 0, // SmrrBase
52 0 // SmrrSize
53 };
54
55 //
56 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
57 //
58 SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate = &mSmmCpuPrivateData;
59
60 //
61 // SMM Relocation variables
62 //
63 volatile BOOLEAN *mRebased;
64 volatile BOOLEAN mIsBsp;
65
66 ///
67 /// Handle for the SMM CPU Protocol
68 ///
69 EFI_HANDLE mSmmCpuHandle = NULL;
70
71 ///
72 /// SMM CPU Protocol instance
73 ///
74 EFI_SMM_CPU_PROTOCOL mSmmCpu = {
75 SmmReadSaveState,
76 SmmWriteSaveState
77 };
78
79 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];
80
81 //
82 // SMM stack information
83 //
84 UINTN mSmmStackArrayBase;
85 UINTN mSmmStackArrayEnd;
86 UINTN mSmmStackSize;
87
88 UINTN mMaxNumberOfCpus = 1;
89 UINTN mNumberOfCpus = 1;
90
91 //
92 // SMM ready to lock flag
93 //
94 BOOLEAN mSmmReadyToLock = FALSE;
95
96 //
97 // Global used to cache PCD for SMM Code Access Check enable
98 //
99 BOOLEAN mSmmCodeAccessCheckEnable = FALSE;
100
101 //
102 // Global copy of the PcdPteMemoryEncryptionAddressOrMask
103 //
104 UINT64 mAddressEncMask = 0;
105
106 //
107 // Spin lock used to serialize setting of SMM Code Access Check feature
108 //
109 SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;
110
111 //
112 // Saved SMM ranges information
113 //
114 EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
115 UINTN mSmmCpuSmramRangeCount;
116
117 /**
118 Initialize IDT to setup exception handlers for SMM.
119
120 **/
121 VOID
122 InitializeSmmIdt (
123 VOID
124 )
125 {
126 EFI_STATUS Status;
127 BOOLEAN InterruptState;
128 IA32_DESCRIPTOR DxeIdtr;
129
130 //
131 // There are 32 (not 255) entries in it since only processor
132 // generated exceptions will be handled.
133 //
134 gcSmiIdtr.Limit = (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;
135 //
136 // Allocate page aligned IDT, because it might be set as read only.
137 //
138 gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr.Limit + 1));
139 ASSERT (gcSmiIdtr.Base != 0);
140 ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1);
141
142 //
143 // Disable Interrupt and save DXE IDT table
144 //
145 InterruptState = SaveAndDisableInterrupts ();
146 AsmReadIdtr (&DxeIdtr);
147 //
148 // Load SMM temporary IDT table
149 //
150 AsmWriteIdtr (&gcSmiIdtr);
151 //
152 // Setup SMM default exception handlers, SMM IDT table
153 // will be updated and saved in gcSmiIdtr
154 //
155 Status = InitializeCpuExceptionHandlers (NULL);
156 ASSERT_EFI_ERROR (Status);
157 //
158 // Restore DXE IDT table and CPU interrupt
159 //
160 AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr);
161 SetInterruptState (InterruptState);
162 }
163
164 /**
165 Search module name by input IP address and output it.
166
167 @param CallerIpAddress Caller instruction pointer.
168
169 **/
170 VOID
171 DumpModuleInfoByIp (
172 IN UINTN CallerIpAddress
173 )
174 {
175 UINTN Pe32Data;
176 VOID *PdbPointer;
177
178 //
179 // Find Image Base
180 //
181 Pe32Data = PeCoffSearchImageBase (CallerIpAddress);
182 if (Pe32Data != 0) {
183 DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *) CallerIpAddress));
184 PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
185 if (PdbPointer != NULL) {
186 DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));
187 }
188 }
189 }
190
191 /**
192 Read information from the CPU save state.
193
194 @param This EFI_SMM_CPU_PROTOCOL instance
195 @param Width The number of bytes to read from the CPU save state.
196 @param Register Specifies the CPU register to read form the save state.
197 @param CpuIndex Specifies the zero-based index of the CPU save state.
198 @param Buffer Upon return, this holds the CPU register value read from the save state.
199
200 @retval EFI_SUCCESS The register was read from Save State
201 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
202 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
203
204 **/
205 EFI_STATUS
206 EFIAPI
207 SmmReadSaveState (
208 IN CONST EFI_SMM_CPU_PROTOCOL *This,
209 IN UINTN Width,
210 IN EFI_SMM_SAVE_STATE_REGISTER Register,
211 IN UINTN CpuIndex,
212 OUT VOID *Buffer
213 )
214 {
215 EFI_STATUS Status;
216
217 //
218 // Retrieve pointer to the specified CPU's SMM Save State buffer
219 //
220 if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
221 return EFI_INVALID_PARAMETER;
222 }
223
224 //
225 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
226 //
227 if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {
228 //
229 // The pseudo-register only supports the 64-bit size specified by Width.
230 //
231 if (Width != sizeof (UINT64)) {
232 return EFI_INVALID_PARAMETER;
233 }
234 //
235 // If the processor is in SMM at the time the SMI occurred,
236 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
237 // Otherwise, EFI_NOT_FOUND is returned.
238 //
239 if (*(mSmmMpSyncData->CpuData[CpuIndex].Present)) {
240 *(UINT64 *)Buffer = gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId;
241 return EFI_SUCCESS;
242 } else {
243 return EFI_NOT_FOUND;
244 }
245 }
246
247 if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {
248 return EFI_INVALID_PARAMETER;
249 }
250
251 Status = SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
252 if (Status == EFI_UNSUPPORTED) {
253 Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
254 }
255 return Status;
256 }
257
258 /**
259 Write data to the CPU save state.
260
261 @param This EFI_SMM_CPU_PROTOCOL instance
262 @param Width The number of bytes to read from the CPU save state.
263 @param Register Specifies the CPU register to write to the save state.
264 @param CpuIndex Specifies the zero-based index of the CPU save state
265 @param Buffer Upon entry, this holds the new CPU register value.
266
267 @retval EFI_SUCCESS The register was written from Save State
268 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
269 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
270
271 **/
272 EFI_STATUS
273 EFIAPI
274 SmmWriteSaveState (
275 IN CONST EFI_SMM_CPU_PROTOCOL *This,
276 IN UINTN Width,
277 IN EFI_SMM_SAVE_STATE_REGISTER Register,
278 IN UINTN CpuIndex,
279 IN CONST VOID *Buffer
280 )
281 {
282 EFI_STATUS Status;
283
284 //
285 // Retrieve pointer to the specified CPU's SMM Save State buffer
286 //
287 if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
288 return EFI_INVALID_PARAMETER;
289 }
290
291 //
292 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
293 //
294 if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {
295 return EFI_SUCCESS;
296 }
297
298 if (!mSmmMpSyncData->CpuData[CpuIndex].Present) {
299 return EFI_INVALID_PARAMETER;
300 }
301
302 Status = SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
303 if (Status == EFI_UNSUPPORTED) {
304 Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
305 }
306 return Status;
307 }
308
309
310 /**
311 C function for SMI handler. To change all processor's SMMBase Register.
312
313 **/
314 VOID
315 EFIAPI
316 SmmInitHandler (
317 VOID
318 )
319 {
320 UINT32 ApicId;
321 UINTN Index;
322
323 //
324 // Update SMM IDT entries' code segment and load IDT
325 //
326 AsmWriteIdtr (&gcSmiIdtr);
327 ApicId = GetApicId ();
328
329 ASSERT (mNumberOfCpus <= mMaxNumberOfCpus);
330
331 for (Index = 0; Index < mNumberOfCpus; Index++) {
332 if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
333 //
334 // Initialize SMM specific features on the currently executing CPU
335 //
336 SmmCpuFeaturesInitializeProcessor (
337 Index,
338 mIsBsp,
339 gSmmCpuPrivate->ProcessorInfo,
340 &mCpuHotPlugData
341 );
342
343 if (!mSmmS3Flag) {
344 //
345 // Check XD and BTS features on each processor on normal boot
346 //
347 CheckFeatureSupported ();
348 }
349
350 if (mIsBsp) {
351 //
352 // BSP rebase is already done above.
353 // Initialize private data during S3 resume
354 //
355 InitializeMpSyncData ();
356 }
357
358 //
359 // Hook return after RSM to set SMM re-based flag
360 //
361 SemaphoreHook (Index, &mRebased[Index]);
362
363 return;
364 }
365 }
366 ASSERT (FALSE);
367 }
368
369 /**
370 Relocate SmmBases for each processor.
371
372 Execute on first boot and all S3 resumes
373
374 **/
375 VOID
376 EFIAPI
377 SmmRelocateBases (
378 VOID
379 )
380 {
381 UINT8 BakBuf[BACK_BUF_SIZE];
382 SMRAM_SAVE_STATE_MAP BakBuf2;
383 SMRAM_SAVE_STATE_MAP *CpuStatePtr;
384 UINT8 *U8Ptr;
385 UINT32 ApicId;
386 UINTN Index;
387 UINTN BspIndex;
388
389 //
390 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
391 //
392 ASSERT (sizeof (BakBuf) >= gcSmmInitSize);
393
394 //
395 // Patch ASM code template with current CR0, CR3, and CR4 values
396 //
397 gSmmCr0 = (UINT32)AsmReadCr0 ();
398 gSmmCr3 = (UINT32)AsmReadCr3 ();
399 gSmmCr4 = (UINT32)AsmReadCr4 ();
400
401 //
402 // Patch GDTR for SMM base relocation
403 //
404 gcSmiInitGdtr.Base = gcSmiGdtr.Base;
405 gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;
406
407 U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);
408 CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
409
410 //
411 // Backup original contents at address 0x38000
412 //
413 CopyMem (BakBuf, U8Ptr, sizeof (BakBuf));
414 CopyMem (&BakBuf2, CpuStatePtr, sizeof (BakBuf2));
415
416 //
417 // Load image for relocation
418 //
419 CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize);
420
421 //
422 // Retrieve the local APIC ID of current processor
423 //
424 ApicId = GetApicId ();
425
426 //
427 // Relocate SM bases for all APs
428 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
429 //
430 mIsBsp = FALSE;
431 BspIndex = (UINTN)-1;
432 for (Index = 0; Index < mNumberOfCpus; Index++) {
433 mRebased[Index] = FALSE;
434 if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
435 SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
436 //
437 // Wait for this AP to finish its 1st SMI
438 //
439 while (!mRebased[Index]);
440 } else {
441 //
442 // BSP will be Relocated later
443 //
444 BspIndex = Index;
445 }
446 }
447
448 //
449 // Relocate BSP's SMM base
450 //
451 ASSERT (BspIndex != (UINTN)-1);
452 mIsBsp = TRUE;
453 SendSmiIpi (ApicId);
454 //
455 // Wait for the BSP to finish its 1st SMI
456 //
457 while (!mRebased[BspIndex]);
458
459 //
460 // Restore contents at address 0x38000
461 //
462 CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2));
463 CopyMem (U8Ptr, BakBuf, sizeof (BakBuf));
464 }
465
466 /**
467 SMM Ready To Lock event notification handler.
468
469 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
470 perform additional lock actions that must be performed from SMM on the next SMI.
471
472 @param[in] Protocol Points to the protocol's unique identifier.
473 @param[in] Interface Points to the interface instance.
474 @param[in] Handle The handle on which the interface was installed.
475
476 @retval EFI_SUCCESS Notification handler runs successfully.
477 **/
478 EFI_STATUS
479 EFIAPI
480 SmmReadyToLockEventNotify (
481 IN CONST EFI_GUID *Protocol,
482 IN VOID *Interface,
483 IN EFI_HANDLE Handle
484 )
485 {
486 GetAcpiCpuData ();
487
488 //
489 // Cache a copy of UEFI memory map before we start profiling feature.
490 //
491 GetUefiMemoryMap ();
492
493 //
494 // Set SMM ready to lock flag and return
495 //
496 mSmmReadyToLock = TRUE;
497 return EFI_SUCCESS;
498 }
499
500 /**
501 The module Entry Point of the CPU SMM driver.
502
503 @param ImageHandle The firmware allocated handle for the EFI image.
504 @param SystemTable A pointer to the EFI System Table.
505
506 @retval EFI_SUCCESS The entry point is executed successfully.
507 @retval Other Some error occurs when executing this entry point.
508
509 **/
510 EFI_STATUS
511 EFIAPI
512 PiCpuSmmEntry (
513 IN EFI_HANDLE ImageHandle,
514 IN EFI_SYSTEM_TABLE *SystemTable
515 )
516 {
517 EFI_STATUS Status;
518 EFI_MP_SERVICES_PROTOCOL *MpServices;
519 UINTN NumberOfEnabledProcessors;
520 UINTN Index;
521 VOID *Buffer;
522 UINTN BufferPages;
523 UINTN TileCodeSize;
524 UINTN TileDataSize;
525 UINTN TileSize;
526 UINT8 *Stacks;
527 VOID *Registration;
528 UINT32 RegEax;
529 UINT32 RegEdx;
530 UINTN FamilyId;
531 UINTN ModelId;
532 UINT32 Cr3;
533
534 //
535 // Initialize Debug Agent to support source level debug in SMM code
536 //
537 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL);
538
539 //
540 // Report the start of CPU SMM initialization.
541 //
542 REPORT_STATUS_CODE (
543 EFI_PROGRESS_CODE,
544 EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT
545 );
546
547 //
548 // Fix segment address of the long-mode-switch jump
549 //
550 if (sizeof (UINTN) == sizeof (UINT64)) {
551 gSmmJmpAddr.Segment = LONG_MODE_CODE_SEGMENT;
552 }
553
554 //
555 // Find out SMRR Base and SMRR Size
556 //
557 FindSmramInfo (&mCpuHotPlugData.SmrrBase, &mCpuHotPlugData.SmrrSize);
558
559 //
560 // Get MP Services Protocol
561 //
562 Status = SystemTable->BootServices->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices);
563 ASSERT_EFI_ERROR (Status);
564
565 //
566 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
567 //
568 Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus, &NumberOfEnabledProcessors);
569 ASSERT_EFI_ERROR (Status);
570 ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
571
572 //
573 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
574 // A constant BSP index makes no sense because it may be hot removed.
575 //
576 DEBUG_CODE (
577 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
578
579 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));
580 }
581 );
582
583 //
584 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
585 //
586 mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable);
587 DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));
588
589 //
590 // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.
591 // Make sure AddressEncMask is contained to smallest supported address field.
592 //
593 mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
594 DEBUG ((EFI_D_INFO, "mAddressEncMask = 0x%lx\n", mAddressEncMask));
595
596 //
597 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
598 //
599 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
600 mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
601 } else {
602 mMaxNumberOfCpus = mNumberOfCpus;
603 }
604 gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;
605
606 //
607 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
608 // allocated buffer. The minimum size of this buffer for a uniprocessor system
609 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
610 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
611 // then the SMI entry point and the CPU save state areas can be tiles to minimize
612 // the total amount SMRAM required for all the CPUs. The tile size can be computed
613 // by adding the // CPU save state size, any extra CPU specific context, and
614 // the size of code that must be placed at the SMI entry point to transfer
615 // control to a C function in the native SMM execution mode. This size is
616 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
617 // The total amount of memory required is the maximum number of CPUs that
618 // platform supports times the tile size. The picture below shows the tiling,
619 // where m is the number of tiles that fit in 32KB.
620 //
621 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
622 // | CPU m+1 Save State |
623 // +-----------------------------+
624 // | CPU m+1 Extra Data |
625 // +-----------------------------+
626 // | Padding |
627 // +-----------------------------+
628 // | CPU 2m SMI Entry |
629 // +#############################+ <-- Base of allocated buffer + 64 KB
630 // | CPU m-1 Save State |
631 // +-----------------------------+
632 // | CPU m-1 Extra Data |
633 // +-----------------------------+
634 // | Padding |
635 // +-----------------------------+
636 // | CPU 2m-1 SMI Entry |
637 // +=============================+ <-- 2^n offset from Base of allocated buffer
638 // | . . . . . . . . . . . . |
639 // +=============================+ <-- 2^n offset from Base of allocated buffer
640 // | CPU 2 Save State |
641 // +-----------------------------+
642 // | CPU 2 Extra Data |
643 // +-----------------------------+
644 // | Padding |
645 // +-----------------------------+
646 // | CPU m+1 SMI Entry |
647 // +=============================+ <-- Base of allocated buffer + 32 KB
648 // | CPU 1 Save State |
649 // +-----------------------------+
650 // | CPU 1 Extra Data |
651 // +-----------------------------+
652 // | Padding |
653 // +-----------------------------+
654 // | CPU m SMI Entry |
655 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
656 // | CPU 0 Save State |
657 // +-----------------------------+
658 // | CPU 0 Extra Data |
659 // +-----------------------------+
660 // | Padding |
661 // +-----------------------------+
662 // | CPU m-1 SMI Entry |
663 // +=============================+ <-- 2^n offset from Base of allocated buffer
664 // | . . . . . . . . . . . . |
665 // +=============================+ <-- 2^n offset from Base of allocated buffer
666 // | Padding |
667 // +-----------------------------+
668 // | CPU 1 SMI Entry |
669 // +=============================+ <-- 2^n offset from Base of allocated buffer
670 // | Padding |
671 // +-----------------------------+
672 // | CPU 0 SMI Entry |
673 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
674 //
675
676 //
677 // Retrieve CPU Family
678 //
679 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
680 FamilyId = (RegEax >> 8) & 0xf;
681 ModelId = (RegEax >> 4) & 0xf;
682 if (FamilyId == 0x06 || FamilyId == 0x0f) {
683 ModelId = ModelId | ((RegEax >> 12) & 0xf0);
684 }
685
686 RegEdx = 0;
687 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
688 if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
689 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
690 }
691 //
692 // Determine the mode of the CPU at the time an SMI occurs
693 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
694 // Volume 3C, Section 34.4.1.1
695 //
696 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
697 if ((RegEdx & BIT29) != 0) {
698 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
699 }
700 if (FamilyId == 0x06) {
701 if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) {
702 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
703 }
704 }
705
706 //
707 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
708 // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
709 // This size is rounded up to nearest power of 2.
710 //
711 TileCodeSize = GetSmiHandlerSize ();
712 TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
713 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
714 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
715 TileSize = TileDataSize + TileCodeSize - 1;
716 TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
717 DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
718
719 //
720 // If the TileSize is larger than space available for the SMI Handler of
721 // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save
722 // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then
723 // the SMI Handler size must be reduced or the size of the extra CPU specific
724 // context must be reduced.
725 //
726 ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));
727
728 //
729 // Allocate buffer for all of the tiles.
730 //
731 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
732 // Volume 3C, Section 34.11 SMBASE Relocation
733 // For Pentium and Intel486 processors, the SMBASE values must be
734 // aligned on a 32-KByte boundary or the processor will enter shutdown
735 // state during the execution of a RSM instruction.
736 //
737 // Intel486 processors: FamilyId is 4
738 // Pentium processors : FamilyId is 5
739 //
740 BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1));
741 if ((FamilyId == 4) || (FamilyId == 5)) {
742 Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB);
743 } else {
744 Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);
745 }
746 ASSERT (Buffer != NULL);
747 DEBUG ((EFI_D_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages)));
748
749 //
750 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
751 //
752 gSmmCpuPrivate->ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus);
753 ASSERT (gSmmCpuPrivate->ProcessorInfo != NULL);
754
755 gSmmCpuPrivate->Operation = (SMM_CPU_OPERATION *)AllocatePool (sizeof (SMM_CPU_OPERATION) * mMaxNumberOfCpus);
756 ASSERT (gSmmCpuPrivate->Operation != NULL);
757
758 gSmmCpuPrivate->CpuSaveStateSize = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);
759 ASSERT (gSmmCpuPrivate->CpuSaveStateSize != NULL);
760
761 gSmmCpuPrivate->CpuSaveState = (VOID **)AllocatePool (sizeof (VOID *) * mMaxNumberOfCpus);
762 ASSERT (gSmmCpuPrivate->CpuSaveState != NULL);
763
764 mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize;
765 mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState = gSmmCpuPrivate->CpuSaveState;
766
767 //
768 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
769 //
770 mCpuHotPlugData.ApicId = (UINT64 *)AllocatePool (sizeof (UINT64) * mMaxNumberOfCpus);
771 ASSERT (mCpuHotPlugData.ApicId != NULL);
772 mCpuHotPlugData.SmBase = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);
773 ASSERT (mCpuHotPlugData.SmBase != NULL);
774 mCpuHotPlugData.ArrayLength = (UINT32)mMaxNumberOfCpus;
775
776 //
777 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
778 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
779 // size for each CPU in the platform
780 //
781 for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
782 mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
783 gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP);
784 gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);
785 gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
786
787 if (Index < mNumberOfCpus) {
788 Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]);
789 ASSERT_EFI_ERROR (Status);
790 mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;
791
792 DEBUG ((EFI_D_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
793 Index,
794 (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,
795 mCpuHotPlugData.SmBase[Index],
796 gSmmCpuPrivate->CpuSaveState[Index],
797 gSmmCpuPrivate->CpuSaveStateSize[Index]
798 ));
799 } else {
800 gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID;
801 mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID;
802 }
803 }
804
805 //
806 // Allocate SMI stacks for all processors.
807 //
808 if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
809 //
810 // 2 more pages is allocated for each processor.
811 // one is guard page and the other is known good stack.
812 //
813 // +-------------------------------------------+-----+-------------------------------------------+
814 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
815 // +-------------------------------------------+-----+-------------------------------------------+
816 // | | | |
817 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
818 //
819 mSmmStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2);
820 Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2));
821 ASSERT (Stacks != NULL);
822 mSmmStackArrayBase = (UINTN)Stacks;
823 mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize - 1;
824 } else {
825 mSmmStackSize = PcdGet32 (PcdCpuSmmStackSize);
826 Stacks = (UINT8 *) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize));
827 ASSERT (Stacks != NULL);
828 }
829
830 //
831 // Set SMI stack for SMM base relocation
832 //
833 gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));
834
835 //
836 // Initialize IDT
837 //
838 InitializeSmmIdt ();
839
840 //
841 // Relocate SMM Base addresses to the ones allocated from SMRAM
842 //
843 mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus);
844 ASSERT (mRebased != NULL);
845 SmmRelocateBases ();
846
847 //
848 // Call hook for BSP to perform extra actions in normal mode after all
849 // SMM base addresses have been relocated on all CPUs
850 //
851 SmmCpuFeaturesSmmRelocationComplete ();
852
853 DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported));
854
855 //
856 // SMM Time initialization
857 //
858 InitializeSmmTimer ();
859
860 //
861 // Initialize MP globals
862 //
863 Cr3 = InitializeMpServiceData (Stacks, mSmmStackSize);
864
865 //
866 // Fill in SMM Reserved Regions
867 //
868 gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0;
869 gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize = 0;
870
871 //
872 // Install the SMM Configuration Protocol onto a new handle on the handle database.
873 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
874 // to an SMRAM address will be present in the handle database
875 //
876 Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (
877 &gSmmCpuPrivate->SmmCpuHandle,
878 &gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration,
879 NULL
880 );
881 ASSERT_EFI_ERROR (Status);
882
883 //
884 // Install the SMM CPU Protocol into SMM protocol database
885 //
886 Status = gSmst->SmmInstallProtocolInterface (
887 &mSmmCpuHandle,
888 &gEfiSmmCpuProtocolGuid,
889 EFI_NATIVE_INTERFACE,
890 &mSmmCpu
891 );
892 ASSERT_EFI_ERROR (Status);
893
894 //
895 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
896 //
897 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
898 Status = PcdSet64S (PcdCpuHotPlugDataAddress, (UINT64)(UINTN)&mCpuHotPlugData);
899 ASSERT_EFI_ERROR (Status);
900 }
901
902 //
903 // Initialize SMM CPU Services Support
904 //
905 Status = InitializeSmmCpuServices (mSmmCpuHandle);
906 ASSERT_EFI_ERROR (Status);
907
908 //
909 // register SMM Ready To Lock Protocol notification
910 //
911 Status = gSmst->SmmRegisterProtocolNotify (
912 &gEfiSmmReadyToLockProtocolGuid,
913 SmmReadyToLockEventNotify,
914 &Registration
915 );
916 ASSERT_EFI_ERROR (Status);
917
918 //
919 // Initialize SMM Profile feature
920 //
921 InitSmmProfile (Cr3);
922
923 GetAcpiS3EnableFlag ();
924 InitSmmS3ResumeState (Cr3);
925
926 DEBUG ((EFI_D_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
927
928 return EFI_SUCCESS;
929 }
930
931 /**
932
933 Find out SMRAM information including SMRR base and SMRR size.
934
935 @param SmrrBase SMRR base
936 @param SmrrSize SMRR size
937
938 **/
939 VOID
940 FindSmramInfo (
941 OUT UINT32 *SmrrBase,
942 OUT UINT32 *SmrrSize
943 )
944 {
945 EFI_STATUS Status;
946 UINTN Size;
947 EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
948 EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;
949 UINTN Index;
950 UINT64 MaxSize;
951 BOOLEAN Found;
952
953 //
954 // Get SMM Access Protocol
955 //
956 Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);
957 ASSERT_EFI_ERROR (Status);
958
959 //
960 // Get SMRAM information
961 //
962 Size = 0;
963 Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);
964 ASSERT (Status == EFI_BUFFER_TOO_SMALL);
965
966 mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
967 ASSERT (mSmmCpuSmramRanges != NULL);
968
969 Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRanges);
970 ASSERT_EFI_ERROR (Status);
971
972 mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
973
974 //
975 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
976 //
977 CurrentSmramRange = NULL;
978 for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCpuSmramRangeCount; Index++) {
979 //
980 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
981 //
982 if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
983 continue;
984 }
985
986 if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {
987 if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {
988 if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {
989 MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;
990 CurrentSmramRange = &mSmmCpuSmramRanges[Index];
991 }
992 }
993 }
994 }
995
996 ASSERT (CurrentSmramRange != NULL);
997
998 *SmrrBase = (UINT32)CurrentSmramRange->CpuStart;
999 *SmrrSize = (UINT32)CurrentSmramRange->PhysicalSize;
1000
1001 do {
1002 Found = FALSE;
1003 for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
1004 if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&
1005 *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) {
1006 *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;
1007 *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
1008 Found = TRUE;
1009 } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) {
1010 *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
1011 Found = TRUE;
1012 }
1013 }
1014 } while (Found);
1015
1016 DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));
1017 }
1018
1019 /**
1020 Configure SMM Code Access Check feature on an AP.
1021 SMM Feature Control MSR will be locked after configuration.
1022
1023 @param[in,out] Buffer Pointer to private data buffer.
1024 **/
1025 VOID
1026 EFIAPI
1027 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1028 IN OUT VOID *Buffer
1029 )
1030 {
1031 UINTN CpuIndex;
1032 UINT64 SmmFeatureControlMsr;
1033 UINT64 NewSmmFeatureControlMsr;
1034
1035 //
1036 // Retrieve the CPU Index from the context passed in
1037 //
1038 CpuIndex = *(UINTN *)Buffer;
1039
1040 //
1041 // Get the current SMM Feature Control MSR value
1042 //
1043 SmmFeatureControlMsr = SmmCpuFeaturesGetSmmRegister (CpuIndex, SmmRegFeatureControl);
1044
1045 //
1046 // Compute the new SMM Feature Control MSR value
1047 //
1048 NewSmmFeatureControlMsr = SmmFeatureControlMsr;
1049 if (mSmmCodeAccessCheckEnable) {
1050 NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT;
1051 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {
1052 NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT;
1053 }
1054 }
1055
1056 //
1057 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1058 //
1059 if (NewSmmFeatureControlMsr != SmmFeatureControlMsr) {
1060 SmmCpuFeaturesSetSmmRegister (CpuIndex, SmmRegFeatureControl, NewSmmFeatureControlMsr);
1061 }
1062
1063 //
1064 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1065 //
1066 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
1067 }
1068
1069 /**
1070 Configure SMM Code Access Check feature for all processors.
1071 SMM Feature Control MSR will be locked after configuration.
1072 **/
1073 VOID
1074 ConfigSmmCodeAccessCheck (
1075 VOID
1076 )
1077 {
1078 UINTN Index;
1079 EFI_STATUS Status;
1080
1081 //
1082 // Check to see if the Feature Control MSR is supported on this CPU
1083 //
1084 Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
1085 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) {
1086 mSmmCodeAccessCheckEnable = FALSE;
1087 return;
1088 }
1089
1090 //
1091 // Check to see if the CPU supports the SMM Code Access Check feature
1092 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1093 //
1094 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) {
1095 mSmmCodeAccessCheckEnable = FALSE;
1096 return;
1097 }
1098
1099 //
1100 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1101 //
1102 InitializeSpinLock (mConfigSmmCodeAccessCheckLock);
1103
1104 //
1105 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1106 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1107 //
1108 AcquireSpinLock (mConfigSmmCodeAccessCheckLock);
1109
1110 //
1111 // Enable SMM Code Access Check feature on the BSP.
1112 //
1113 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index);
1114
1115 //
1116 // Enable SMM Code Access Check feature for the APs.
1117 //
1118 for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
1119 if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {
1120
1121 //
1122 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1123 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1124 //
1125 AcquireSpinLock (mConfigSmmCodeAccessCheckLock);
1126
1127 //
1128 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1129 //
1130 Status = gSmst->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor, Index, &Index);
1131 ASSERT_EFI_ERROR (Status);
1132
1133 //
1134 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1135 //
1136 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock)) {
1137 CpuPause ();
1138 }
1139
1140 //
1141 // Release the Config SMM Code Access Check spin lock.
1142 //
1143 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
1144 }
1145 }
1146 }
1147
1148 /**
1149 This API provides a way to allocate memory for page table.
1150
1151 This API can be called more once to allocate memory for page tables.
1152
1153 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
1154 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
1155 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
1156 returned.
1157
1158 @param Pages The number of 4 KB pages to allocate.
1159
1160 @return A pointer to the allocated buffer or NULL if allocation fails.
1161
1162 **/
1163 VOID *
1164 AllocatePageTableMemory (
1165 IN UINTN Pages
1166 )
1167 {
1168 VOID *Buffer;
1169
1170 Buffer = SmmCpuFeaturesAllocatePageTableMemory (Pages);
1171 if (Buffer != NULL) {
1172 return Buffer;
1173 }
1174 return AllocatePages (Pages);
1175 }
1176
1177 /**
1178 Allocate pages for code.
1179
1180 @param[in] Pages Number of pages to be allocated.
1181
1182 @return Allocated memory.
1183 **/
1184 VOID *
1185 AllocateCodePages (
1186 IN UINTN Pages
1187 )
1188 {
1189 EFI_STATUS Status;
1190 EFI_PHYSICAL_ADDRESS Memory;
1191
1192 if (Pages == 0) {
1193 return NULL;
1194 }
1195
1196 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);
1197 if (EFI_ERROR (Status)) {
1198 return NULL;
1199 }
1200 return (VOID *) (UINTN) Memory;
1201 }
1202
1203 /**
1204 Allocate aligned pages for code.
1205
1206 @param[in] Pages Number of pages to be allocated.
1207 @param[in] Alignment The requested alignment of the allocation.
1208 Must be a power of two.
1209 If Alignment is zero, then byte alignment is used.
1210
1211 @return Allocated memory.
1212 **/
1213 VOID *
1214 AllocateAlignedCodePages (
1215 IN UINTN Pages,
1216 IN UINTN Alignment
1217 )
1218 {
1219 EFI_STATUS Status;
1220 EFI_PHYSICAL_ADDRESS Memory;
1221 UINTN AlignedMemory;
1222 UINTN AlignmentMask;
1223 UINTN UnalignedPages;
1224 UINTN RealPages;
1225
1226 //
1227 // Alignment must be a power of two or zero.
1228 //
1229 ASSERT ((Alignment & (Alignment - 1)) == 0);
1230
1231 if (Pages == 0) {
1232 return NULL;
1233 }
1234 if (Alignment > EFI_PAGE_SIZE) {
1235 //
1236 // Calculate the total number of pages since alignment is larger than page size.
1237 //
1238 AlignmentMask = Alignment - 1;
1239 RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
1240 //
1241 // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
1242 //
1243 ASSERT (RealPages > Pages);
1244
1245 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory);
1246 if (EFI_ERROR (Status)) {
1247 return NULL;
1248 }
1249 AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
1250 UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
1251 if (UnalignedPages > 0) {
1252 //
1253 // Free first unaligned page(s).
1254 //
1255 Status = gSmst->SmmFreePages (Memory, UnalignedPages);
1256 ASSERT_EFI_ERROR (Status);
1257 }
1258 Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);
1259 UnalignedPages = RealPages - Pages - UnalignedPages;
1260 if (UnalignedPages > 0) {
1261 //
1262 // Free last unaligned page(s).
1263 //
1264 Status = gSmst->SmmFreePages (Memory, UnalignedPages);
1265 ASSERT_EFI_ERROR (Status);
1266 }
1267 } else {
1268 //
1269 // Do not over-allocate pages in this case.
1270 //
1271 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);
1272 if (EFI_ERROR (Status)) {
1273 return NULL;
1274 }
1275 AlignedMemory = (UINTN) Memory;
1276 }
1277 return (VOID *) AlignedMemory;
1278 }
1279
1280 /**
1281 Perform the remaining tasks.
1282
1283 **/
1284 VOID
1285 PerformRemainingTasks (
1286 VOID
1287 )
1288 {
1289 if (mSmmReadyToLock) {
1290 //
1291 // Start SMM Profile feature
1292 //
1293 if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
1294 SmmProfileStart ();
1295 }
1296 //
1297 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1298 //
1299 InitPaging ();
1300
1301 //
1302 // Mark critical region to be read-only in page table
1303 //
1304 SetMemMapAttributes ();
1305
1306 //
1307 // For outside SMRAM, we only map SMM communication buffer or MMIO.
1308 //
1309 SetUefiMemMapAttributes ();
1310
1311 //
1312 // Set page table itself to be read-only
1313 //
1314 SetPageTableAttributes ();
1315
1316 //
1317 // Configure SMM Code Access Check feature if available.
1318 //
1319 ConfigSmmCodeAccessCheck ();
1320
1321 SmmCpuFeaturesCompleteSmmReadyToLock ();
1322
1323 //
1324 // Clean SMM ready to lock flag
1325 //
1326 mSmmReadyToLock = FALSE;
1327 }
1328 }
1329
1330 /**
1331 Perform the pre tasks.
1332
1333 **/
1334 VOID
1335 PerformPreTasks (
1336 VOID
1337 )
1338 {
1339 RestoreSmmConfigurationInS3 ();
1340 }