2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PiSmmCpuDxeSmm.h"
18 // SMM CPU Private Data structure that contains SMM Configuration Protocol
19 // along its supporting fields.
21 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData
= {
22 SMM_CPU_PRIVATE_DATA_SIGNATURE
, // Signature
24 NULL
, // Pointer to ProcessorInfo array
25 NULL
, // Pointer to Operation array
26 NULL
, // Pointer to CpuSaveStateSize array
27 NULL
, // Pointer to CpuSaveState array
28 { {0} }, // SmmReservedSmramRegion
30 SmmStartupThisAp
, // SmmCoreEntryContext.SmmStartupThisAp
31 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
32 0, // SmmCoreEntryContext.NumberOfCpus
33 NULL
, // SmmCoreEntryContext.CpuSaveStateSize
34 NULL
// SmmCoreEntryContext.CpuSaveState
38 mSmmCpuPrivateData
.SmmReservedSmramRegion
, // SmmConfiguration.SmramReservedRegions
39 RegisterSmmEntry
// SmmConfiguration.RegisterSmmEntry
43 CPU_HOT_PLUG_DATA mCpuHotPlugData
= {
44 CPU_HOT_PLUG_DATA_REVISION_1
, // Revision
45 0, // Array Length of SmBase and APIC ID
46 NULL
, // Pointer to APIC ID array
47 NULL
, // Pointer to SMBASE array
54 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
56 SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
= &mSmmCpuPrivateData
;
59 // SMM Relocation variables
61 volatile BOOLEAN
*mRebased
;
62 volatile BOOLEAN mIsBsp
;
65 /// Handle for the SMM CPU Protocol
67 EFI_HANDLE mSmmCpuHandle
= NULL
;
70 /// SMM CPU Protocol instance
72 EFI_SMM_CPU_PROTOCOL mSmmCpu
= {
77 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable
[EXCEPTION_VECTOR_NUMBER
];
80 // SMM stack information
82 UINTN mSmmStackArrayBase
;
83 UINTN mSmmStackArrayEnd
;
86 UINTN mMaxNumberOfCpus
= 1;
87 UINTN mNumberOfCpus
= 1;
90 // SMM ready to lock flag
92 BOOLEAN mSmmReadyToLock
= FALSE
;
95 // Global used to cache PCD for SMM Code Access Check enable
97 BOOLEAN mSmmCodeAccessCheckEnable
= FALSE
;
100 // Spin lock used to serialize setting of SMM Code Access Check feature
102 SPIN_LOCK
*mConfigSmmCodeAccessCheckLock
= NULL
;
105 Initialize IDT to setup exception handlers for SMM.
114 BOOLEAN InterruptState
;
115 IA32_DESCRIPTOR DxeIdtr
;
118 // There are 32 (not 255) entries in it since only processor
119 // generated exceptions will be handled.
121 gcSmiIdtr
.Limit
= (sizeof(IA32_IDT_GATE_DESCRIPTOR
) * 32) - 1;
123 // Allocate page aligned IDT, because it might be set as read only.
125 gcSmiIdtr
.Base
= (UINTN
)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr
.Limit
+ 1));
126 ASSERT (gcSmiIdtr
.Base
!= 0);
127 ZeroMem ((VOID
*)gcSmiIdtr
.Base
, gcSmiIdtr
.Limit
+ 1);
130 // Disable Interrupt and save DXE IDT table
132 InterruptState
= SaveAndDisableInterrupts ();
133 AsmReadIdtr (&DxeIdtr
);
135 // Load SMM temporary IDT table
137 AsmWriteIdtr (&gcSmiIdtr
);
139 // Setup SMM default exception handlers, SMM IDT table
140 // will be updated and saved in gcSmiIdtr
142 Status
= InitializeCpuExceptionHandlers (NULL
);
143 ASSERT_EFI_ERROR (Status
);
145 // Restore DXE IDT table and CPU interrupt
147 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &DxeIdtr
);
148 SetInterruptState (InterruptState
);
152 Search module name by input IP address and output it.
154 @param CallerIpAddress Caller instruction pointer.
159 IN UINTN CallerIpAddress
163 EFI_IMAGE_DOS_HEADER
*DosHdr
;
164 EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr
;
166 UINT64 DumpIpAddress
;
171 Pe32Data
= CallerIpAddress
& ~(SIZE_4KB
- 1);
172 while (Pe32Data
!= 0) {
173 DosHdr
= (EFI_IMAGE_DOS_HEADER
*) Pe32Data
;
174 if (DosHdr
->e_magic
== EFI_IMAGE_DOS_SIGNATURE
) {
176 // DOS image header is present, so read the PE header after the DOS image header.
178 Hdr
.Pe32
= (EFI_IMAGE_NT_HEADERS32
*)(Pe32Data
+ (UINTN
) ((DosHdr
->e_lfanew
) & 0x0ffff));
180 // Make sure PE header address does not overflow and is less than the initial address.
182 if (((UINTN
)Hdr
.Pe32
> Pe32Data
) && ((UINTN
)Hdr
.Pe32
< CallerIpAddress
)) {
183 if (Hdr
.Pe32
->Signature
== EFI_IMAGE_NT_SIGNATURE
) {
193 // Not found the image base, check the previous aligned address
195 Pe32Data
-= SIZE_4KB
;
198 DumpIpAddress
= CallerIpAddress
;
199 DEBUG ((EFI_D_ERROR
, "It is invoked from the instruction before IP(0x%lx)", DumpIpAddress
));
202 PdbPointer
= PeCoffLoaderGetPdbPointer ((VOID
*) Pe32Data
);
203 if (PdbPointer
!= NULL
) {
204 DEBUG ((EFI_D_ERROR
, " in module (%a)", PdbPointer
));
210 Read information from the CPU save state.
212 @param This EFI_SMM_CPU_PROTOCOL instance
213 @param Width The number of bytes to read from the CPU save state.
214 @param Register Specifies the CPU register to read form the save state.
215 @param CpuIndex Specifies the zero-based index of the CPU save state.
216 @param Buffer Upon return, this holds the CPU register value read from the save state.
218 @retval EFI_SUCCESS The register was read from Save State
219 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
220 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
226 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
228 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
236 // Retrieve pointer to the specified CPU's SMM Save State buffer
238 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
239 return EFI_INVALID_PARAMETER
;
243 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
245 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
247 // The pseudo-register only supports the 64-bit size specified by Width.
249 if (Width
!= sizeof (UINT64
)) {
250 return EFI_INVALID_PARAMETER
;
253 // If the processor is in SMM at the time the SMI occurred,
254 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
255 // Otherwise, EFI_NOT_FOUND is returned.
257 if (*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
)) {
258 *(UINT64
*)Buffer
= gSmmCpuPrivate
->ProcessorInfo
[CpuIndex
].ProcessorId
;
261 return EFI_NOT_FOUND
;
265 if (!(*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
))) {
266 return EFI_INVALID_PARAMETER
;
269 Status
= SmmCpuFeaturesReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
270 if (Status
== EFI_UNSUPPORTED
) {
271 Status
= ReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
277 Write data to the CPU save state.
279 @param This EFI_SMM_CPU_PROTOCOL instance
280 @param Width The number of bytes to read from the CPU save state.
281 @param Register Specifies the CPU register to write to the save state.
282 @param CpuIndex Specifies the zero-based index of the CPU save state
283 @param Buffer Upon entry, this holds the new CPU register value.
285 @retval EFI_SUCCESS The register was written from Save State
286 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
287 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
293 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
295 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
297 IN CONST VOID
*Buffer
303 // Retrieve pointer to the specified CPU's SMM Save State buffer
305 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
306 return EFI_INVALID_PARAMETER
;
310 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
312 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
316 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
317 return EFI_INVALID_PARAMETER
;
320 Status
= SmmCpuFeaturesWriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
321 if (Status
== EFI_UNSUPPORTED
) {
322 Status
= WriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
329 C function for SMI handler. To change all processor's SMMBase Register.
342 // Update SMM IDT entries' code segment and load IDT
344 AsmWriteIdtr (&gcSmiIdtr
);
345 ApicId
= GetApicId ();
347 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
349 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
350 if (ApicId
== (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
352 // Initialize SMM specific features on the currently executing CPU
354 SmmCpuFeaturesInitializeProcessor (
357 gSmmCpuPrivate
->ProcessorInfo
,
363 // Check XD and BTS features on each processor on normal boot
365 CheckFeatureSupported ();
370 // BSP rebase is already done above.
371 // Initialize private data during S3 resume
373 InitializeMpSyncData ();
377 // Hook return after RSM to set SMM re-based flag
379 SemaphoreHook (Index
, &mRebased
[Index
]);
388 Relocate SmmBases for each processor.
390 Execute on first boot and all S3 resumes
399 UINT8 BakBuf
[BACK_BUF_SIZE
];
400 SMRAM_SAVE_STATE_MAP BakBuf2
;
401 SMRAM_SAVE_STATE_MAP
*CpuStatePtr
;
408 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
410 ASSERT (sizeof (BakBuf
) >= gcSmmInitSize
);
413 // Patch ASM code template with current CR0, CR3, and CR4 values
415 gSmmCr0
= (UINT32
)AsmReadCr0 ();
416 gSmmCr3
= (UINT32
)AsmReadCr3 ();
417 gSmmCr4
= (UINT32
)AsmReadCr4 ();
420 // Patch GDTR for SMM base relocation
422 gcSmiInitGdtr
.Base
= gcSmiGdtr
.Base
;
423 gcSmiInitGdtr
.Limit
= gcSmiGdtr
.Limit
;
425 U8Ptr
= (UINT8
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMM_HANDLER_OFFSET
);
426 CpuStatePtr
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
429 // Backup original contents at address 0x38000
431 CopyMem (BakBuf
, U8Ptr
, sizeof (BakBuf
));
432 CopyMem (&BakBuf2
, CpuStatePtr
, sizeof (BakBuf2
));
435 // Load image for relocation
437 CopyMem (U8Ptr
, gcSmmInitTemplate
, gcSmmInitSize
);
440 // Retrieve the local APIC ID of current processor
442 ApicId
= GetApicId ();
445 // Relocate SM bases for all APs
446 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
449 BspIndex
= (UINTN
)-1;
450 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
451 mRebased
[Index
] = FALSE
;
452 if (ApicId
!= (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
453 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
455 // Wait for this AP to finish its 1st SMI
457 while (!mRebased
[Index
]);
460 // BSP will be Relocated later
467 // Relocate BSP's SMM base
469 ASSERT (BspIndex
!= (UINTN
)-1);
473 // Wait for the BSP to finish its 1st SMI
475 while (!mRebased
[BspIndex
]);
478 // Restore contents at address 0x38000
480 CopyMem (CpuStatePtr
, &BakBuf2
, sizeof (BakBuf2
));
481 CopyMem (U8Ptr
, BakBuf
, sizeof (BakBuf
));
485 SMM Ready To Lock event notification handler.
487 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
488 perform additional lock actions that must be performed from SMM on the next SMI.
490 @param[in] Protocol Points to the protocol's unique identifier.
491 @param[in] Interface Points to the interface instance.
492 @param[in] Handle The handle on which the interface was installed.
494 @retval EFI_SUCCESS Notification handler runs successfully.
498 SmmReadyToLockEventNotify (
499 IN CONST EFI_GUID
*Protocol
,
507 // Set SMM ready to lock flag and return
509 mSmmReadyToLock
= TRUE
;
514 The module Entry Point of the CPU SMM driver.
516 @param ImageHandle The firmware allocated handle for the EFI image.
517 @param SystemTable A pointer to the EFI System Table.
519 @retval EFI_SUCCESS The entry point is executed successfully.
520 @retval Other Some error occurs when executing this entry point.
526 IN EFI_HANDLE ImageHandle
,
527 IN EFI_SYSTEM_TABLE
*SystemTable
531 EFI_MP_SERVICES_PROTOCOL
*MpServices
;
532 UINTN NumberOfEnabledProcessors
;
548 // Initialize Debug Agent to support source level debug in SMM code
550 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM
, NULL
, NULL
);
553 // Report the start of CPU SMM initialization.
557 EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_INIT
561 // Fix segment address of the long-mode-switch jump
563 if (sizeof (UINTN
) == sizeof (UINT64
)) {
564 gSmmJmpAddr
.Segment
= LONG_MODE_CODE_SEGMENT
;
568 // Find out SMRR Base and SMRR Size
570 FindSmramInfo (&mCpuHotPlugData
.SmrrBase
, &mCpuHotPlugData
.SmrrSize
);
573 // Get MP Services Protocol
575 Status
= SystemTable
->BootServices
->LocateProtocol (&gEfiMpServiceProtocolGuid
, NULL
, (VOID
**)&MpServices
);
576 ASSERT_EFI_ERROR (Status
);
579 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
581 Status
= MpServices
->GetNumberOfProcessors (MpServices
, &mNumberOfCpus
, &NumberOfEnabledProcessors
);
582 ASSERT_EFI_ERROR (Status
);
583 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
586 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
587 // A constant BSP index makes no sense because it may be hot removed.
590 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
592 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection
));
597 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
599 mSmmCodeAccessCheckEnable
= PcdGetBool (PcdCpuSmmCodeAccessCheckEnable
);
600 DEBUG ((EFI_D_INFO
, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable
));
603 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
605 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
606 mMaxNumberOfCpus
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
608 mMaxNumberOfCpus
= mNumberOfCpus
;
610 gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
= mMaxNumberOfCpus
;
613 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
614 // allocated buffer. The minimum size of this buffer for a uniprocessor system
615 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
616 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
617 // then the SMI entry point and the CPU save state areas can be tiles to minimize
618 // the total amount SMRAM required for all the CPUs. The tile size can be computed
619 // by adding the // CPU save state size, any extra CPU specific context, and
620 // the size of code that must be placed at the SMI entry point to transfer
621 // control to a C function in the native SMM execution mode. This size is
622 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
623 // The total amount of memory required is the maximum number of CPUs that
624 // platform supports times the tile size. The picture below shows the tiling,
625 // where m is the number of tiles that fit in 32KB.
627 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
628 // | CPU m+1 Save State |
629 // +-----------------------------+
630 // | CPU m+1 Extra Data |
631 // +-----------------------------+
633 // +-----------------------------+
634 // | CPU 2m SMI Entry |
635 // +#############################+ <-- Base of allocated buffer + 64 KB
636 // | CPU m-1 Save State |
637 // +-----------------------------+
638 // | CPU m-1 Extra Data |
639 // +-----------------------------+
641 // +-----------------------------+
642 // | CPU 2m-1 SMI Entry |
643 // +=============================+ <-- 2^n offset from Base of allocated buffer
644 // | . . . . . . . . . . . . |
645 // +=============================+ <-- 2^n offset from Base of allocated buffer
646 // | CPU 2 Save State |
647 // +-----------------------------+
648 // | CPU 2 Extra Data |
649 // +-----------------------------+
651 // +-----------------------------+
652 // | CPU m+1 SMI Entry |
653 // +=============================+ <-- Base of allocated buffer + 32 KB
654 // | CPU 1 Save State |
655 // +-----------------------------+
656 // | CPU 1 Extra Data |
657 // +-----------------------------+
659 // +-----------------------------+
660 // | CPU m SMI Entry |
661 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
662 // | CPU 0 Save State |
663 // +-----------------------------+
664 // | CPU 0 Extra Data |
665 // +-----------------------------+
667 // +-----------------------------+
668 // | CPU m-1 SMI Entry |
669 // +=============================+ <-- 2^n offset from Base of allocated buffer
670 // | . . . . . . . . . . . . |
671 // +=============================+ <-- 2^n offset from Base of allocated buffer
673 // +-----------------------------+
674 // | CPU 1 SMI Entry |
675 // +=============================+ <-- 2^n offset from Base of allocated buffer
677 // +-----------------------------+
678 // | CPU 0 SMI Entry |
679 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
683 // Retrieve CPU Family
685 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, NULL
);
686 FamilyId
= (RegEax
>> 8) & 0xf;
687 ModelId
= (RegEax
>> 4) & 0xf;
688 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
689 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
693 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
694 if (RegEax
>= CPUID_EXTENDED_CPU_SIG
) {
695 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
698 // Determine the mode of the CPU at the time an SMI occurs
699 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
700 // Volume 3C, Section 34.4.1.1
702 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
;
703 if ((RegEdx
& BIT29
) != 0) {
704 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
706 if (FamilyId
== 0x06) {
707 if (ModelId
== 0x17 || ModelId
== 0x0f || ModelId
== 0x1c) {
708 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
713 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
714 // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size
715 // is rounded up to nearest power of 2.
717 TileCodeSize
= GetSmiHandlerSize ();
718 TileCodeSize
= ALIGN_VALUE(TileCodeSize
, SIZE_4KB
);
719 TileDataSize
= sizeof (SMRAM_SAVE_STATE_MAP
) + sizeof (PROCESSOR_SMM_DESCRIPTOR
);
720 TileDataSize
= ALIGN_VALUE(TileDataSize
, SIZE_4KB
);
721 TileSize
= TileDataSize
+ TileCodeSize
- 1;
722 TileSize
= 2 * GetPowerOfTwo32 ((UINT32
)TileSize
);
723 DEBUG ((EFI_D_INFO
, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize
, TileCodeSize
, TileDataSize
));
726 // If the TileSize is larger than space available for the SMI Handler of CPU[i],
727 // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],
728 // the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be
731 ASSERT (TileSize
<= (SMRAM_SAVE_STATE_MAP_OFFSET
+ sizeof (SMRAM_SAVE_STATE_MAP
) - SMM_HANDLER_OFFSET
));
734 // Allocate buffer for all of the tiles.
736 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
737 // Volume 3C, Section 34.11 SMBASE Relocation
738 // For Pentium and Intel486 processors, the SMBASE values must be
739 // aligned on a 32-KByte boundary or the processor will enter shutdown
740 // state during the execution of a RSM instruction.
742 // Intel486 processors: FamilyId is 4
743 // Pentium processors : FamilyId is 5
745 BufferPages
= EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1));
746 if ((FamilyId
== 4) || (FamilyId
== 5)) {
747 Buffer
= AllocateAlignedCodePages (BufferPages
, SIZE_32KB
);
749 Buffer
= AllocateAlignedCodePages (BufferPages
, SIZE_4KB
);
751 ASSERT (Buffer
!= NULL
);
752 DEBUG ((EFI_D_INFO
, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer
, EFI_PAGES_TO_SIZE(BufferPages
)));
755 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
757 gSmmCpuPrivate
->ProcessorInfo
= (EFI_PROCESSOR_INFORMATION
*)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION
) * mMaxNumberOfCpus
);
758 ASSERT (gSmmCpuPrivate
->ProcessorInfo
!= NULL
);
760 gSmmCpuPrivate
->Operation
= (SMM_CPU_OPERATION
*)AllocatePool (sizeof (SMM_CPU_OPERATION
) * mMaxNumberOfCpus
);
761 ASSERT (gSmmCpuPrivate
->Operation
!= NULL
);
763 gSmmCpuPrivate
->CpuSaveStateSize
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
764 ASSERT (gSmmCpuPrivate
->CpuSaveStateSize
!= NULL
);
766 gSmmCpuPrivate
->CpuSaveState
= (VOID
**)AllocatePool (sizeof (VOID
*) * mMaxNumberOfCpus
);
767 ASSERT (gSmmCpuPrivate
->CpuSaveState
!= NULL
);
769 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveStateSize
= gSmmCpuPrivate
->CpuSaveStateSize
;
770 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveState
= gSmmCpuPrivate
->CpuSaveState
;
773 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
775 mCpuHotPlugData
.ApicId
= (UINT64
*)AllocatePool (sizeof (UINT64
) * mMaxNumberOfCpus
);
776 ASSERT (mCpuHotPlugData
.ApicId
!= NULL
);
777 mCpuHotPlugData
.SmBase
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
778 ASSERT (mCpuHotPlugData
.SmBase
!= NULL
);
779 mCpuHotPlugData
.ArrayLength
= (UINT32
)mMaxNumberOfCpus
;
782 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
783 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
784 // size for each CPU in the platform
786 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
787 mCpuHotPlugData
.SmBase
[Index
] = (UINTN
)Buffer
+ Index
* TileSize
- SMM_HANDLER_OFFSET
;
788 gSmmCpuPrivate
->CpuSaveStateSize
[Index
] = sizeof(SMRAM_SAVE_STATE_MAP
);
789 gSmmCpuPrivate
->CpuSaveState
[Index
] = (VOID
*)(mCpuHotPlugData
.SmBase
[Index
] + SMRAM_SAVE_STATE_MAP_OFFSET
);
790 gSmmCpuPrivate
->Operation
[Index
] = SmmCpuNone
;
792 if (Index
< mNumberOfCpus
) {
793 Status
= MpServices
->GetProcessorInfo (MpServices
, Index
, &gSmmCpuPrivate
->ProcessorInfo
[Index
]);
794 ASSERT_EFI_ERROR (Status
);
795 mCpuHotPlugData
.ApicId
[Index
] = gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
;
797 DEBUG ((EFI_D_INFO
, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
799 (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
,
800 mCpuHotPlugData
.SmBase
[Index
],
801 gSmmCpuPrivate
->CpuSaveState
[Index
],
802 gSmmCpuPrivate
->CpuSaveStateSize
[Index
]
805 gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
= INVALID_APIC_ID
;
806 mCpuHotPlugData
.ApicId
[Index
] = INVALID_APIC_ID
;
811 // Allocate SMI stacks for all processors.
813 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
815 // 2 more pages is allocated for each processor.
816 // one is guard page and the other is known good stack.
818 // +-------------------------------------------+-----+-------------------------------------------+
819 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
820 // +-------------------------------------------+-----+-------------------------------------------+
822 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
824 mSmmStackSize
= EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2);
825 Stacks
= (UINT8
*) AllocatePages (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2));
826 ASSERT (Stacks
!= NULL
);
827 mSmmStackArrayBase
= (UINTN
)Stacks
;
828 mSmmStackArrayEnd
= mSmmStackArrayBase
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
- 1;
830 mSmmStackSize
= PcdGet32 (PcdCpuSmmStackSize
);
831 Stacks
= (UINT8
*) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
));
832 ASSERT (Stacks
!= NULL
);
836 // Set SMI stack for SMM base relocation
838 gSmmInitStack
= (UINTN
) (Stacks
+ mSmmStackSize
- sizeof (UINTN
));
846 // Relocate SMM Base addresses to the ones allocated from SMRAM
848 mRebased
= (BOOLEAN
*)AllocateZeroPool (sizeof (BOOLEAN
) * mMaxNumberOfCpus
);
849 ASSERT (mRebased
!= NULL
);
853 // Call hook for BSP to perform extra actions in normal mode after all
854 // SMM base addresses have been relocated on all CPUs
856 SmmCpuFeaturesSmmRelocationComplete ();
858 DEBUG ((DEBUG_INFO
, "mXdSupported - 0x%x\n", mXdSupported
));
861 // SMM Time initialization
863 InitializeSmmTimer ();
866 // Initialize MP globals
868 Cr3
= InitializeMpServiceData (Stacks
, mSmmStackSize
);
871 // Fill in SMM Reserved Regions
873 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedStart
= 0;
874 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedSize
= 0;
877 // Install the SMM Configuration Protocol onto a new handle on the handle database.
878 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
879 // to an SMRAM address will be present in the handle database
881 Status
= SystemTable
->BootServices
->InstallMultipleProtocolInterfaces (
882 &gSmmCpuPrivate
->SmmCpuHandle
,
883 &gEfiSmmConfigurationProtocolGuid
, &gSmmCpuPrivate
->SmmConfiguration
,
886 ASSERT_EFI_ERROR (Status
);
889 // Install the SMM CPU Protocol into SMM protocol database
891 Status
= gSmst
->SmmInstallProtocolInterface (
893 &gEfiSmmCpuProtocolGuid
,
894 EFI_NATIVE_INTERFACE
,
897 ASSERT_EFI_ERROR (Status
);
900 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
902 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
903 Status
= PcdSet64S (PcdCpuHotPlugDataAddress
, (UINT64
)(UINTN
)&mCpuHotPlugData
);
904 ASSERT_EFI_ERROR (Status
);
908 // Initialize SMM CPU Services Support
910 Status
= InitializeSmmCpuServices (mSmmCpuHandle
);
911 ASSERT_EFI_ERROR (Status
);
914 // register SMM Ready To Lock Protocol notification
916 Status
= gSmst
->SmmRegisterProtocolNotify (
917 &gEfiSmmReadyToLockProtocolGuid
,
918 SmmReadyToLockEventNotify
,
921 ASSERT_EFI_ERROR (Status
);
924 // Initialize SMM Profile feature
926 InitSmmProfile (Cr3
);
928 GetAcpiS3EnableFlag ();
929 InitSmmS3ResumeState (Cr3
);
931 DEBUG ((EFI_D_INFO
, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
938 Find out SMRAM information including SMRR base and SMRR size.
940 @param SmrrBase SMRR base
941 @param SmrrSize SMRR size
946 OUT UINT32
*SmrrBase
,
952 EFI_SMM_ACCESS2_PROTOCOL
*SmmAccess
;
953 EFI_SMRAM_DESCRIPTOR
*CurrentSmramRange
;
954 EFI_SMRAM_DESCRIPTOR
*SmramRanges
;
955 UINTN SmramRangeCount
;
961 // Get SMM Access Protocol
963 Status
= gBS
->LocateProtocol (&gEfiSmmAccess2ProtocolGuid
, NULL
, (VOID
**)&SmmAccess
);
964 ASSERT_EFI_ERROR (Status
);
967 // Get SMRAM information
970 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, NULL
);
971 ASSERT (Status
== EFI_BUFFER_TOO_SMALL
);
973 SmramRanges
= (EFI_SMRAM_DESCRIPTOR
*)AllocatePool (Size
);
974 ASSERT (SmramRanges
!= NULL
);
976 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, SmramRanges
);
977 ASSERT_EFI_ERROR (Status
);
979 SmramRangeCount
= Size
/ sizeof (EFI_SMRAM_DESCRIPTOR
);
982 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
984 CurrentSmramRange
= NULL
;
985 for (Index
= 0, MaxSize
= SIZE_256KB
- EFI_PAGE_SIZE
; Index
< SmramRangeCount
; Index
++) {
987 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
989 if ((SmramRanges
[Index
].RegionState
& (EFI_ALLOCATED
| EFI_NEEDS_TESTING
| EFI_NEEDS_ECC_INITIALIZATION
)) != 0) {
993 if (SmramRanges
[Index
].CpuStart
>= BASE_1MB
) {
994 if ((SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
) <= BASE_4GB
) {
995 if (SmramRanges
[Index
].PhysicalSize
>= MaxSize
) {
996 MaxSize
= SmramRanges
[Index
].PhysicalSize
;
997 CurrentSmramRange
= &SmramRanges
[Index
];
1003 ASSERT (CurrentSmramRange
!= NULL
);
1005 *SmrrBase
= (UINT32
)CurrentSmramRange
->CpuStart
;
1006 *SmrrSize
= (UINT32
)CurrentSmramRange
->PhysicalSize
;
1010 for (Index
= 0; Index
< SmramRangeCount
; Index
++) {
1011 if (SmramRanges
[Index
].CpuStart
< *SmrrBase
&& *SmrrBase
== (SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
)) {
1012 *SmrrBase
= (UINT32
)SmramRanges
[Index
].CpuStart
;
1013 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1015 } else if ((*SmrrBase
+ *SmrrSize
) == SmramRanges
[Index
].CpuStart
&& SmramRanges
[Index
].PhysicalSize
> 0) {
1016 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1022 FreePool (SmramRanges
);
1023 DEBUG ((EFI_D_INFO
, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase
, *SmrrSize
));
1027 Configure SMM Code Access Check feature on an AP.
1028 SMM Feature Control MSR will be locked after configuration.
1030 @param[in,out] Buffer Pointer to private data buffer.
1034 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1039 UINT64 SmmFeatureControlMsr
;
1040 UINT64 NewSmmFeatureControlMsr
;
1043 // Retrieve the CPU Index from the context passed in
1045 CpuIndex
= *(UINTN
*)Buffer
;
1048 // Get the current SMM Feature Control MSR value
1050 SmmFeatureControlMsr
= SmmCpuFeaturesGetSmmRegister (CpuIndex
, SmmRegFeatureControl
);
1053 // Compute the new SMM Feature Control MSR value
1055 NewSmmFeatureControlMsr
= SmmFeatureControlMsr
;
1056 if (mSmmCodeAccessCheckEnable
) {
1057 NewSmmFeatureControlMsr
|= SMM_CODE_CHK_EN_BIT
;
1058 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1059 NewSmmFeatureControlMsr
|= SMM_FEATURE_CONTROL_LOCK_BIT
;
1064 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1066 if (NewSmmFeatureControlMsr
!= SmmFeatureControlMsr
) {
1067 SmmCpuFeaturesSetSmmRegister (CpuIndex
, SmmRegFeatureControl
, NewSmmFeatureControlMsr
);
1071 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1073 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1077 Configure SMM Code Access Check feature for all processors.
1078 SMM Feature Control MSR will be locked after configuration.
1081 ConfigSmmCodeAccessCheck (
1089 // Check to see if the Feature Control MSR is supported on this CPU
1091 Index
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1092 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index
, SmmRegFeatureControl
)) {
1093 mSmmCodeAccessCheckEnable
= FALSE
;
1098 // Check to see if the CPU supports the SMM Code Access Check feature
1099 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1101 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP
) & SMM_CODE_ACCESS_CHK_BIT
) == 0) {
1102 mSmmCodeAccessCheckEnable
= FALSE
;
1107 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1109 InitializeSpinLock (mConfigSmmCodeAccessCheckLock
);
1112 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1113 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1115 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1118 // Enable SMM Code Access Check feature on the BSP.
1120 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index
);
1123 // Enable SMM Code Access Check feature for the APs.
1125 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1126 if (Index
!= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
) {
1129 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1130 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1132 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1135 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1137 Status
= gSmst
->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor
, Index
, &Index
);
1138 ASSERT_EFI_ERROR (Status
);
1141 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1143 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock
)) {
1148 // Release the Config SMM Code Access Check spin lock.
1150 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1156 Set code region to be read only and data region to be execute disable.
1159 SetRegionAttributes (
1163 SetMemMapAttributes ();
1167 This API provides a way to allocate memory for page table.
1169 This API can be called more once to allocate memory for page tables.
1171 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
1172 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
1173 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
1176 @param Pages The number of 4 KB pages to allocate.
1178 @return A pointer to the allocated buffer or NULL if allocation fails.
1182 AllocatePageTableMemory (
1188 Buffer
= SmmCpuFeaturesAllocatePageTableMemory (Pages
);
1189 if (Buffer
!= NULL
) {
1192 return AllocatePages (Pages
);
1196 Allocate pages for code.
1198 @param[in] Pages Number of pages to be allocated.
1200 @return Allocated memory.
1208 EFI_PHYSICAL_ADDRESS Memory
;
1214 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, Pages
, &Memory
);
1215 if (EFI_ERROR (Status
)) {
1218 return (VOID
*) (UINTN
) Memory
;
1222 Allocate aligned pages for code.
1224 @param[in] Pages Number of pages to be allocated.
1225 @param[in] Alignment The requested alignment of the allocation.
1226 Must be a power of two.
1227 If Alignment is zero, then byte alignment is used.
1229 @return Allocated memory.
1232 AllocateAlignedCodePages (
1238 EFI_PHYSICAL_ADDRESS Memory
;
1239 UINTN AlignedMemory
;
1240 UINTN AlignmentMask
;
1241 UINTN UnalignedPages
;
1245 // Alignment must be a power of two or zero.
1247 ASSERT ((Alignment
& (Alignment
- 1)) == 0);
1252 if (Alignment
> EFI_PAGE_SIZE
) {
1254 // Calculate the total number of pages since alignment is larger than page size.
1256 AlignmentMask
= Alignment
- 1;
1257 RealPages
= Pages
+ EFI_SIZE_TO_PAGES (Alignment
);
1259 // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
1261 ASSERT (RealPages
> Pages
);
1263 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, RealPages
, &Memory
);
1264 if (EFI_ERROR (Status
)) {
1267 AlignedMemory
= ((UINTN
) Memory
+ AlignmentMask
) & ~AlignmentMask
;
1268 UnalignedPages
= EFI_SIZE_TO_PAGES (AlignedMemory
- (UINTN
) Memory
);
1269 if (UnalignedPages
> 0) {
1271 // Free first unaligned page(s).
1273 Status
= gSmst
->SmmFreePages (Memory
, UnalignedPages
);
1274 ASSERT_EFI_ERROR (Status
);
1276 Memory
= (EFI_PHYSICAL_ADDRESS
) (AlignedMemory
+ EFI_PAGES_TO_SIZE (Pages
));
1277 UnalignedPages
= RealPages
- Pages
- UnalignedPages
;
1278 if (UnalignedPages
> 0) {
1280 // Free last unaligned page(s).
1282 Status
= gSmst
->SmmFreePages (Memory
, UnalignedPages
);
1283 ASSERT_EFI_ERROR (Status
);
1287 // Do not over-allocate pages in this case.
1289 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, Pages
, &Memory
);
1290 if (EFI_ERROR (Status
)) {
1293 AlignedMemory
= (UINTN
) Memory
;
1295 return (VOID
*) AlignedMemory
;
1299 Perform the remaining tasks.
1303 PerformRemainingTasks (
1307 if (mSmmReadyToLock
) {
1309 // Start SMM Profile feature
1311 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1315 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1320 // Mark critical region to be read-only in page table
1322 SetRegionAttributes ();
1325 // Set page table itself to be read-only
1327 SetPageTableAttributes ();
1330 // Configure SMM Code Access Check feature if available.
1332 ConfigSmmCodeAccessCheck ();
1334 SmmCpuFeaturesCompleteSmmReadyToLock ();
1337 // Clean SMM ready to lock flag
1339 mSmmReadyToLock
= FALSE
;
1344 Perform the pre tasks.
1352 RestoreSmmConfigurationInS3 ();