2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
11 #include "PiSmmCpuDxeSmm.h"
14 // SMM CPU Private Data structure that contains SMM Configuration Protocol
15 // along its supporting fields.
17 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData
= {
18 SMM_CPU_PRIVATE_DATA_SIGNATURE
, // Signature
20 NULL
, // Pointer to ProcessorInfo array
21 NULL
, // Pointer to Operation array
22 NULL
, // Pointer to CpuSaveStateSize array
23 NULL
, // Pointer to CpuSaveState array
26 }, // SmmReservedSmramRegion
28 SmmStartupThisAp
, // SmmCoreEntryContext.SmmStartupThisAp
29 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
30 0, // SmmCoreEntryContext.NumberOfCpus
31 NULL
, // SmmCoreEntryContext.CpuSaveStateSize
32 NULL
// SmmCoreEntryContext.CpuSaveState
36 mSmmCpuPrivateData
.SmmReservedSmramRegion
, // SmmConfiguration.SmramReservedRegions
37 RegisterSmmEntry
// SmmConfiguration.RegisterSmmEntry
39 NULL
, // pointer to Ap Wrapper Func array
40 { NULL
, NULL
}, // List_Entry for Tokens.
43 CPU_HOT_PLUG_DATA mCpuHotPlugData
= {
44 CPU_HOT_PLUG_DATA_REVISION_1
, // Revision
45 0, // Array Length of SmBase and APIC ID
46 NULL
, // Pointer to APIC ID array
47 NULL
, // Pointer to SMBASE array
54 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
56 SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
= &mSmmCpuPrivateData
;
59 // SMM Relocation variables
61 volatile BOOLEAN
*mRebased
;
62 volatile BOOLEAN mIsBsp
;
65 /// Handle for the SMM CPU Protocol
67 EFI_HANDLE mSmmCpuHandle
= NULL
;
70 /// SMM CPU Protocol instance
72 EFI_SMM_CPU_PROTOCOL mSmmCpu
= {
78 /// SMM Memory Attribute Protocol instance
80 EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute
= {
81 EdkiiSmmGetMemoryAttributes
,
82 EdkiiSmmSetMemoryAttributes
,
83 EdkiiSmmClearMemoryAttributes
86 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable
[EXCEPTION_VECTOR_NUMBER
];
89 // SMM stack information
91 UINTN mSmmStackArrayBase
;
92 UINTN mSmmStackArrayEnd
;
95 UINTN mSmmShadowStackSize
;
96 BOOLEAN mCetSupported
= TRUE
;
98 UINTN mMaxNumberOfCpus
= 1;
99 UINTN mNumberOfCpus
= 1;
102 // SMM ready to lock flag
104 BOOLEAN mSmmReadyToLock
= FALSE
;
107 // Global used to cache PCD for SMM Code Access Check enable
109 BOOLEAN mSmmCodeAccessCheckEnable
= FALSE
;
112 // Global copy of the PcdPteMemoryEncryptionAddressOrMask
114 UINT64 mAddressEncMask
= 0;
117 // Spin lock used to serialize setting of SMM Code Access Check feature
119 SPIN_LOCK
*mConfigSmmCodeAccessCheckLock
= NULL
;
122 // Saved SMM ranges information
124 EFI_SMRAM_DESCRIPTOR
*mSmmCpuSmramRanges
;
125 UINTN mSmmCpuSmramRangeCount
;
127 UINT8 mPhysicalAddressBits
;
130 // Control register contents saved for SMM S3 resume state initialization.
136 Initialize IDT to setup exception handlers for SMM.
145 BOOLEAN InterruptState
;
146 IA32_DESCRIPTOR DxeIdtr
;
149 // There are 32 (not 255) entries in it since only processor
150 // generated exceptions will be handled.
152 gcSmiIdtr
.Limit
= (sizeof (IA32_IDT_GATE_DESCRIPTOR
) * 32) - 1;
154 // Allocate page aligned IDT, because it might be set as read only.
156 gcSmiIdtr
.Base
= (UINTN
)AllocateCodePages (EFI_SIZE_TO_PAGES (gcSmiIdtr
.Limit
+ 1));
157 ASSERT (gcSmiIdtr
.Base
!= 0);
158 ZeroMem ((VOID
*)gcSmiIdtr
.Base
, gcSmiIdtr
.Limit
+ 1);
161 // Disable Interrupt and save DXE IDT table
163 InterruptState
= SaveAndDisableInterrupts ();
164 AsmReadIdtr (&DxeIdtr
);
166 // Load SMM temporary IDT table
168 AsmWriteIdtr (&gcSmiIdtr
);
170 // Setup SMM default exception handlers, SMM IDT table
171 // will be updated and saved in gcSmiIdtr
173 Status
= InitializeCpuExceptionHandlers (NULL
);
174 ASSERT_EFI_ERROR (Status
);
176 // Restore DXE IDT table and CPU interrupt
178 AsmWriteIdtr ((IA32_DESCRIPTOR
*)&DxeIdtr
);
179 SetInterruptState (InterruptState
);
183 Search module name by input IP address and output it.
185 @param CallerIpAddress Caller instruction pointer.
190 IN UINTN CallerIpAddress
199 Pe32Data
= PeCoffSearchImageBase (CallerIpAddress
);
201 DEBUG ((DEBUG_ERROR
, "It is invoked from the instruction before IP(0x%p)", (VOID
*)CallerIpAddress
));
202 PdbPointer
= PeCoffLoaderGetPdbPointer ((VOID
*)Pe32Data
);
203 if (PdbPointer
!= NULL
) {
204 DEBUG ((DEBUG_ERROR
, " in module (%a)\n", PdbPointer
));
210 Read information from the CPU save state.
212 @param This EFI_SMM_CPU_PROTOCOL instance
213 @param Width The number of bytes to read from the CPU save state.
214 @param Register Specifies the CPU register to read form the save state.
215 @param CpuIndex Specifies the zero-based index of the CPU save state.
216 @param Buffer Upon return, this holds the CPU register value read from the save state.
218 @retval EFI_SUCCESS The register was read from Save State
219 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
220 @retval EFI_INVALID_PARAMETER This or Buffer is NULL.
226 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
228 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
236 // Retrieve pointer to the specified CPU's SMM Save State buffer
238 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
239 return EFI_INVALID_PARAMETER
;
243 // The SpeculationBarrier() call here is to ensure the above check for the
244 // CpuIndex has been completed before the execution of subsequent codes.
246 SpeculationBarrier ();
249 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
251 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
253 // The pseudo-register only supports the 64-bit size specified by Width.
255 if (Width
!= sizeof (UINT64
)) {
256 return EFI_INVALID_PARAMETER
;
260 // If the processor is in SMM at the time the SMI occurred,
261 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
262 // Otherwise, EFI_NOT_FOUND is returned.
264 if (*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
)) {
265 *(UINT64
*)Buffer
= gSmmCpuPrivate
->ProcessorInfo
[CpuIndex
].ProcessorId
;
268 return EFI_NOT_FOUND
;
272 if (!(*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
))) {
273 return EFI_INVALID_PARAMETER
;
276 Status
= SmmCpuFeaturesReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
277 if (Status
== EFI_UNSUPPORTED
) {
278 Status
= ReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
285 Write data to the CPU save state.
287 @param This EFI_SMM_CPU_PROTOCOL instance
288 @param Width The number of bytes to read from the CPU save state.
289 @param Register Specifies the CPU register to write to the save state.
290 @param CpuIndex Specifies the zero-based index of the CPU save state
291 @param Buffer Upon entry, this holds the new CPU register value.
293 @retval EFI_SUCCESS The register was written from Save State
294 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
295 @retval EFI_INVALID_PARAMETER ProcessorIndex or Width is not correct
301 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
303 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
305 IN CONST VOID
*Buffer
311 // Retrieve pointer to the specified CPU's SMM Save State buffer
313 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
314 return EFI_INVALID_PARAMETER
;
318 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
320 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
324 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
325 return EFI_INVALID_PARAMETER
;
328 Status
= SmmCpuFeaturesWriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
329 if (Status
== EFI_UNSUPPORTED
) {
330 Status
= WriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
337 C function for SMI handler. To change all processor's SMMBase Register.
350 // Update SMM IDT entries' code segment and load IDT
352 AsmWriteIdtr (&gcSmiIdtr
);
353 ApicId
= GetApicId ();
355 ASSERT (mNumberOfCpus
<= mMaxNumberOfCpus
);
357 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
358 if (ApicId
== (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
360 // Initialize SMM specific features on the currently executing CPU
362 SmmCpuFeaturesInitializeProcessor (
365 gSmmCpuPrivate
->ProcessorInfo
,
371 // Check XD and BTS features on each processor on normal boot
373 CheckFeatureSupported ();
378 // BSP rebase is already done above.
379 // Initialize private data during S3 resume
381 InitializeMpSyncData ();
385 // Hook return after RSM to set SMM re-based flag
387 SemaphoreHook (Index
, &mRebased
[Index
]);
397 Relocate SmmBases for each processor.
399 Execute on first boot and all S3 resumes
408 UINT8 BakBuf
[BACK_BUF_SIZE
];
409 SMRAM_SAVE_STATE_MAP BakBuf2
;
410 SMRAM_SAVE_STATE_MAP
*CpuStatePtr
;
417 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
419 ASSERT (sizeof (BakBuf
) >= gcSmmInitSize
);
422 // Patch ASM code template with current CR0, CR3, and CR4 values
424 mSmmCr0
= (UINT32
)AsmReadCr0 ();
425 PatchInstructionX86 (gPatchSmmCr0
, mSmmCr0
, 4);
426 PatchInstructionX86 (gPatchSmmCr3
, AsmReadCr3 (), 4);
427 mSmmCr4
= (UINT32
)AsmReadCr4 ();
428 PatchInstructionX86 (gPatchSmmCr4
, mSmmCr4
& (~CR4_CET_ENABLE
), 4);
431 // Patch GDTR for SMM base relocation
433 gcSmiInitGdtr
.Base
= gcSmiGdtr
.Base
;
434 gcSmiInitGdtr
.Limit
= gcSmiGdtr
.Limit
;
436 U8Ptr
= (UINT8
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMM_HANDLER_OFFSET
);
437 CpuStatePtr
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
440 // Backup original contents at address 0x38000
442 CopyMem (BakBuf
, U8Ptr
, sizeof (BakBuf
));
443 CopyMem (&BakBuf2
, CpuStatePtr
, sizeof (BakBuf2
));
446 // Load image for relocation
448 CopyMem (U8Ptr
, gcSmmInitTemplate
, gcSmmInitSize
);
451 // Retrieve the local APIC ID of current processor
453 ApicId
= GetApicId ();
456 // Relocate SM bases for all APs
457 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
460 BspIndex
= (UINTN
)-1;
461 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
462 mRebased
[Index
] = FALSE
;
463 if (ApicId
!= (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
464 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
466 // Wait for this AP to finish its 1st SMI
468 while (!mRebased
[Index
]) {
472 // BSP will be Relocated later
479 // Relocate BSP's SMM base
481 ASSERT (BspIndex
!= (UINTN
)-1);
485 // Wait for the BSP to finish its 1st SMI
487 while (!mRebased
[BspIndex
]) {
491 // Restore contents at address 0x38000
493 CopyMem (CpuStatePtr
, &BakBuf2
, sizeof (BakBuf2
));
494 CopyMem (U8Ptr
, BakBuf
, sizeof (BakBuf
));
498 SMM Ready To Lock event notification handler.
500 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
501 perform additional lock actions that must be performed from SMM on the next SMI.
503 @param[in] Protocol Points to the protocol's unique identifier.
504 @param[in] Interface Points to the interface instance.
505 @param[in] Handle The handle on which the interface was installed.
507 @retval EFI_SUCCESS Notification handler runs successfully.
511 SmmReadyToLockEventNotify (
512 IN CONST EFI_GUID
*Protocol
,
520 // Cache a copy of UEFI memory map before we start profiling feature.
525 // Set SMM ready to lock flag and return
527 mSmmReadyToLock
= TRUE
;
532 The module Entry Point of the CPU SMM driver.
534 @param ImageHandle The firmware allocated handle for the EFI image.
535 @param SystemTable A pointer to the EFI System Table.
537 @retval EFI_SUCCESS The entry point is executed successfully.
538 @retval Other Some error occurs when executing this entry point.
544 IN EFI_HANDLE ImageHandle
,
545 IN EFI_SYSTEM_TABLE
*SystemTable
549 EFI_MP_SERVICES_PROTOCOL
*MpServices
;
550 UINTN NumberOfEnabledProcessors
;
568 // Initialize address fixup
570 PiSmmCpuSmmInitFixupAddress ();
571 PiSmmCpuSmiEntryFixupAddress ();
574 // Initialize Debug Agent to support source level debug in SMM code
576 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM
, NULL
, NULL
);
579 // Report the start of CPU SMM initialization.
583 EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_INIT
587 // Find out SMRR Base and SMRR Size
589 FindSmramInfo (&mCpuHotPlugData
.SmrrBase
, &mCpuHotPlugData
.SmrrSize
);
592 // Get MP Services Protocol
594 Status
= SystemTable
->BootServices
->LocateProtocol (&gEfiMpServiceProtocolGuid
, NULL
, (VOID
**)&MpServices
);
595 ASSERT_EFI_ERROR (Status
);
598 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
600 Status
= MpServices
->GetNumberOfProcessors (MpServices
, &mNumberOfCpus
, &NumberOfEnabledProcessors
);
601 ASSERT_EFI_ERROR (Status
);
602 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
605 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
606 // A constant BSP index makes no sense because it may be hot removed.
609 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
610 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection
));
616 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
618 mSmmCodeAccessCheckEnable
= PcdGetBool (PcdCpuSmmCodeAccessCheckEnable
);
619 DEBUG ((DEBUG_INFO
, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable
));
622 // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.
623 // Make sure AddressEncMask is contained to smallest supported address field.
625 mAddressEncMask
= PcdGet64 (PcdPteMemoryEncryptionAddressOrMask
) & PAGING_1G_ADDRESS_MASK_64
;
626 DEBUG ((DEBUG_INFO
, "mAddressEncMask = 0x%lx\n", mAddressEncMask
));
629 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
631 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
632 mMaxNumberOfCpus
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
634 mMaxNumberOfCpus
= mNumberOfCpus
;
637 gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
= mMaxNumberOfCpus
;
640 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
641 // allocated buffer. The minimum size of this buffer for a uniprocessor system
642 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
643 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
644 // then the SMI entry point and the CPU save state areas can be tiles to minimize
645 // the total amount SMRAM required for all the CPUs. The tile size can be computed
646 // by adding the // CPU save state size, any extra CPU specific context, and
647 // the size of code that must be placed at the SMI entry point to transfer
648 // control to a C function in the native SMM execution mode. This size is
649 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
650 // The total amount of memory required is the maximum number of CPUs that
651 // platform supports times the tile size. The picture below shows the tiling,
652 // where m is the number of tiles that fit in 32KB.
654 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
655 // | CPU m+1 Save State |
656 // +-----------------------------+
657 // | CPU m+1 Extra Data |
658 // +-----------------------------+
660 // +-----------------------------+
661 // | CPU 2m SMI Entry |
662 // +#############################+ <-- Base of allocated buffer + 64 KB
663 // | CPU m-1 Save State |
664 // +-----------------------------+
665 // | CPU m-1 Extra Data |
666 // +-----------------------------+
668 // +-----------------------------+
669 // | CPU 2m-1 SMI Entry |
670 // +=============================+ <-- 2^n offset from Base of allocated buffer
671 // | . . . . . . . . . . . . |
672 // +=============================+ <-- 2^n offset from Base of allocated buffer
673 // | CPU 2 Save State |
674 // +-----------------------------+
675 // | CPU 2 Extra Data |
676 // +-----------------------------+
678 // +-----------------------------+
679 // | CPU m+1 SMI Entry |
680 // +=============================+ <-- Base of allocated buffer + 32 KB
681 // | CPU 1 Save State |
682 // +-----------------------------+
683 // | CPU 1 Extra Data |
684 // +-----------------------------+
686 // +-----------------------------+
687 // | CPU m SMI Entry |
688 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
689 // | CPU 0 Save State |
690 // +-----------------------------+
691 // | CPU 0 Extra Data |
692 // +-----------------------------+
694 // +-----------------------------+
695 // | CPU m-1 SMI Entry |
696 // +=============================+ <-- 2^n offset from Base of allocated buffer
697 // | . . . . . . . . . . . . |
698 // +=============================+ <-- 2^n offset from Base of allocated buffer
700 // +-----------------------------+
701 // | CPU 1 SMI Entry |
702 // +=============================+ <-- 2^n offset from Base of allocated buffer
704 // +-----------------------------+
705 // | CPU 0 SMI Entry |
706 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
710 // Retrieve CPU Family
712 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, NULL
);
713 FamilyId
= (RegEax
>> 8) & 0xf;
714 ModelId
= (RegEax
>> 4) & 0xf;
715 if ((FamilyId
== 0x06) || (FamilyId
== 0x0f)) {
716 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
720 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
721 if (RegEax
>= CPUID_EXTENDED_CPU_SIG
) {
722 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
726 // Determine the mode of the CPU at the time an SMI occurs
727 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
728 // Volume 3C, Section 34.4.1.1
730 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
;
731 if ((RegEdx
& BIT29
) != 0) {
732 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
735 if (FamilyId
== 0x06) {
736 if ((ModelId
== 0x17) || (ModelId
== 0x0f) || (ModelId
== 0x1c)) {
737 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
741 DEBUG ((DEBUG_INFO
, "PcdControlFlowEnforcementPropertyMask = %d\n", PcdGet32 (PcdControlFlowEnforcementPropertyMask
)));
742 if (PcdGet32 (PcdControlFlowEnforcementPropertyMask
) != 0) {
743 AsmCpuid (CPUID_SIGNATURE
, &RegEax
, NULL
, NULL
, NULL
);
744 if (RegEax
>= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
) {
745 AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO
, NULL
, NULL
, &RegEcx
, &RegEdx
);
746 DEBUG ((DEBUG_INFO
, "CPUID[7/0] ECX - 0x%08x\n", RegEcx
));
747 DEBUG ((DEBUG_INFO
, " CET_SS - 0x%08x\n", RegEcx
& CPUID_CET_SS
));
748 DEBUG ((DEBUG_INFO
, " CET_IBT - 0x%08x\n", RegEdx
& CPUID_CET_IBT
));
749 if ((RegEcx
& CPUID_CET_SS
) == 0) {
750 mCetSupported
= FALSE
;
751 PatchInstructionX86 (mPatchCetSupported
, mCetSupported
, 1);
755 AsmCpuidEx (CPUID_EXTENDED_STATE
, CPUID_EXTENDED_STATE_SUB_LEAF
, NULL
, &RegEbx
, &RegEcx
, NULL
);
756 DEBUG ((DEBUG_INFO
, "CPUID[D/1] EBX - 0x%08x, ECX - 0x%08x\n", RegEbx
, RegEcx
));
757 AsmCpuidEx (CPUID_EXTENDED_STATE
, 11, &RegEax
, NULL
, &RegEcx
, NULL
);
758 DEBUG ((DEBUG_INFO
, "CPUID[D/11] EAX - 0x%08x, ECX - 0x%08x\n", RegEax
, RegEcx
));
759 AsmCpuidEx (CPUID_EXTENDED_STATE
, 12, &RegEax
, NULL
, &RegEcx
, NULL
);
760 DEBUG ((DEBUG_INFO
, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", RegEax
, RegEcx
));
763 mCetSupported
= FALSE
;
764 PatchInstructionX86 (mPatchCetSupported
, mCetSupported
, 1);
767 mCetSupported
= FALSE
;
768 PatchInstructionX86 (mPatchCetSupported
, mCetSupported
, 1);
772 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
773 // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
774 // This size is rounded up to nearest power of 2.
776 TileCodeSize
= GetSmiHandlerSize ();
777 TileCodeSize
= ALIGN_VALUE (TileCodeSize
, SIZE_4KB
);
778 TileDataSize
= (SMRAM_SAVE_STATE_MAP_OFFSET
- SMM_PSD_OFFSET
) + sizeof (SMRAM_SAVE_STATE_MAP
);
779 TileDataSize
= ALIGN_VALUE (TileDataSize
, SIZE_4KB
);
780 TileSize
= TileDataSize
+ TileCodeSize
- 1;
781 TileSize
= 2 * GetPowerOfTwo32 ((UINT32
)TileSize
);
782 DEBUG ((DEBUG_INFO
, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize
, TileCodeSize
, TileDataSize
));
785 // If the TileSize is larger than space available for the SMI Handler of
786 // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save
787 // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then
788 // the SMI Handler size must be reduced or the size of the extra CPU specific
789 // context must be reduced.
791 ASSERT (TileSize
<= (SMRAM_SAVE_STATE_MAP_OFFSET
+ sizeof (SMRAM_SAVE_STATE_MAP
) - SMM_HANDLER_OFFSET
));
794 // Allocate buffer for all of the tiles.
796 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
797 // Volume 3C, Section 34.11 SMBASE Relocation
798 // For Pentium and Intel486 processors, the SMBASE values must be
799 // aligned on a 32-KByte boundary or the processor will enter shutdown
800 // state during the execution of a RSM instruction.
802 // Intel486 processors: FamilyId is 4
803 // Pentium processors : FamilyId is 5
805 BufferPages
= EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1));
806 if ((FamilyId
== 4) || (FamilyId
== 5)) {
807 Buffer
= AllocateAlignedCodePages (BufferPages
, SIZE_32KB
);
809 Buffer
= AllocateAlignedCodePages (BufferPages
, SIZE_4KB
);
812 ASSERT (Buffer
!= NULL
);
813 DEBUG ((DEBUG_INFO
, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer
, EFI_PAGES_TO_SIZE (BufferPages
)));
816 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
818 gSmmCpuPrivate
->ProcessorInfo
= (EFI_PROCESSOR_INFORMATION
*)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION
) * mMaxNumberOfCpus
);
819 ASSERT (gSmmCpuPrivate
->ProcessorInfo
!= NULL
);
821 gSmmCpuPrivate
->Operation
= (SMM_CPU_OPERATION
*)AllocatePool (sizeof (SMM_CPU_OPERATION
) * mMaxNumberOfCpus
);
822 ASSERT (gSmmCpuPrivate
->Operation
!= NULL
);
824 gSmmCpuPrivate
->CpuSaveStateSize
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
825 ASSERT (gSmmCpuPrivate
->CpuSaveStateSize
!= NULL
);
827 gSmmCpuPrivate
->CpuSaveState
= (VOID
**)AllocatePool (sizeof (VOID
*) * mMaxNumberOfCpus
);
828 ASSERT (gSmmCpuPrivate
->CpuSaveState
!= NULL
);
830 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveStateSize
= gSmmCpuPrivate
->CpuSaveStateSize
;
831 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveState
= gSmmCpuPrivate
->CpuSaveState
;
834 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
836 mCpuHotPlugData
.ApicId
= (UINT64
*)AllocatePool (sizeof (UINT64
) * mMaxNumberOfCpus
);
837 ASSERT (mCpuHotPlugData
.ApicId
!= NULL
);
838 mCpuHotPlugData
.SmBase
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
839 ASSERT (mCpuHotPlugData
.SmBase
!= NULL
);
840 mCpuHotPlugData
.ArrayLength
= (UINT32
)mMaxNumberOfCpus
;
843 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
844 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
845 // size for each CPU in the platform
847 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
848 mCpuHotPlugData
.SmBase
[Index
] = (UINTN
)Buffer
+ Index
* TileSize
- SMM_HANDLER_OFFSET
;
849 gSmmCpuPrivate
->CpuSaveStateSize
[Index
] = sizeof (SMRAM_SAVE_STATE_MAP
);
850 gSmmCpuPrivate
->CpuSaveState
[Index
] = (VOID
*)(mCpuHotPlugData
.SmBase
[Index
] + SMRAM_SAVE_STATE_MAP_OFFSET
);
851 gSmmCpuPrivate
->Operation
[Index
] = SmmCpuNone
;
853 if (Index
< mNumberOfCpus
) {
854 Status
= MpServices
->GetProcessorInfo (MpServices
, Index
, &gSmmCpuPrivate
->ProcessorInfo
[Index
]);
855 ASSERT_EFI_ERROR (Status
);
856 mCpuHotPlugData
.ApicId
[Index
] = gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
;
860 "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
862 (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
,
863 mCpuHotPlugData
.SmBase
[Index
],
864 gSmmCpuPrivate
->CpuSaveState
[Index
],
865 gSmmCpuPrivate
->CpuSaveStateSize
[Index
]
868 gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
= INVALID_APIC_ID
;
869 mCpuHotPlugData
.ApicId
[Index
] = INVALID_APIC_ID
;
874 // Allocate SMI stacks for all processors.
876 mSmmStackSize
= EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)));
877 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
879 // SMM Stack Guard Enabled
880 // 2 more pages is allocated for each processor, one is guard page and the other is known good stack.
882 // +--------------------------------------------------+-----+--------------------------------------------------+
883 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
884 // +--------------------------------------------------+-----+--------------------------------------------------+
885 // | 4K | 4K PcdCpuSmmStackSize| | 4K | 4K PcdCpuSmmStackSize|
886 // |<---------------- mSmmStackSize ----------------->| |<---------------- mSmmStackSize ----------------->|
888 // |<------------------ Processor 0 ----------------->| |<------------------ Processor n ----------------->|
890 mSmmStackSize
+= EFI_PAGES_TO_SIZE (2);
893 mSmmShadowStackSize
= 0;
894 if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask
) != 0) && mCetSupported
) {
895 mSmmShadowStackSize
= EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize
)));
897 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
899 // SMM Stack Guard Enabled
900 // Append Shadow Stack after normal stack
901 // 2 more pages is allocated for each processor, one is guard page and the other is known good shadow stack.
904 // +--------------------------------------------------+---------------------------------------------------------------+
905 // | Known Good Stack | Guard Page | SMM Stack | Known Good Shadow Stack | Guard Page | SMM Shadow Stack |
906 // +--------------------------------------------------+---------------------------------------------------------------+
907 // | 4K | 4K |PcdCpuSmmStackSize| 4K | 4K |PcdCpuSmmShadowStackSize|
908 // |<---------------- mSmmStackSize ----------------->|<--------------------- mSmmShadowStackSize ------------------->|
910 // |<-------------------------------------------- Processor N ------------------------------------------------------->|
912 mSmmShadowStackSize
+= EFI_PAGES_TO_SIZE (2);
915 // SMM Stack Guard Disabled (Known Good Stack is still required for potential stack switch.)
916 // Append Shadow Stack after normal stack with 1 more page as known good shadow stack.
917 // 1 more pages is allocated for each processor, it is known good stack.
921 // +-------------------------------------+--------------------------------------------------+
922 // | Known Good Stack | SMM Stack | Known Good Shadow Stack | SMM Shadow Stack |
923 // +-------------------------------------+--------------------------------------------------+
924 // | 4K |PcdCpuSmmStackSize| 4K |PcdCpuSmmShadowStackSize|
925 // |<---------- mSmmStackSize ---------->|<--------------- mSmmShadowStackSize ------------>|
927 // |<-------------------------------- Processor N ----------------------------------------->|
929 mSmmShadowStackSize
+= EFI_PAGES_TO_SIZE (1);
930 mSmmStackSize
+= EFI_PAGES_TO_SIZE (1);
934 Stacks
= (UINT8
*)AllocatePages (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* (EFI_SIZE_TO_PAGES (mSmmStackSize
+ mSmmShadowStackSize
)));
935 ASSERT (Stacks
!= NULL
);
936 mSmmStackArrayBase
= (UINTN
)Stacks
;
937 mSmmStackArrayEnd
= mSmmStackArrayBase
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* (mSmmStackSize
+ mSmmShadowStackSize
) - 1;
939 DEBUG ((DEBUG_INFO
, "Stacks - 0x%x\n", Stacks
));
940 DEBUG ((DEBUG_INFO
, "mSmmStackSize - 0x%x\n", mSmmStackSize
));
941 DEBUG ((DEBUG_INFO
, "PcdCpuSmmStackGuard - 0x%x\n", FeaturePcdGet (PcdCpuSmmStackGuard
)));
942 if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask
) != 0) && mCetSupported
) {
943 DEBUG ((DEBUG_INFO
, "mSmmShadowStackSize - 0x%x\n", mSmmShadowStackSize
));
947 // Set SMI stack for SMM base relocation
949 PatchInstructionX86 (
951 (UINTN
)(Stacks
+ mSmmStackSize
- sizeof (UINTN
)),
961 // Relocate SMM Base addresses to the ones allocated from SMRAM
963 mRebased
= (BOOLEAN
*)AllocateZeroPool (sizeof (BOOLEAN
) * mMaxNumberOfCpus
);
964 ASSERT (mRebased
!= NULL
);
968 // Call hook for BSP to perform extra actions in normal mode after all
969 // SMM base addresses have been relocated on all CPUs
971 SmmCpuFeaturesSmmRelocationComplete ();
973 DEBUG ((DEBUG_INFO
, "mXdSupported - 0x%x\n", mXdSupported
));
976 // SMM Time initialization
978 InitializeSmmTimer ();
981 // Initialize MP globals
983 Cr3
= InitializeMpServiceData (Stacks
, mSmmStackSize
, mSmmShadowStackSize
);
985 if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask
) != 0) && mCetSupported
) {
986 for (Index
= 0; Index
< gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
; Index
++) {
989 (EFI_PHYSICAL_ADDRESS
)(UINTN
)Stacks
+ mSmmStackSize
+ (mSmmStackSize
+ mSmmShadowStackSize
) * Index
,
992 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
995 (EFI_PHYSICAL_ADDRESS
)(UINTN
)Stacks
+ mSmmStackSize
+ EFI_PAGES_TO_SIZE (1) + (mSmmStackSize
+ mSmmShadowStackSize
) * Index
,
996 EFI_PAGES_TO_SIZE (1)
1003 // Fill in SMM Reserved Regions
1005 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedStart
= 0;
1006 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedSize
= 0;
1009 // Install the SMM Configuration Protocol onto a new handle on the handle database.
1010 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
1011 // to an SMRAM address will be present in the handle database
1013 Status
= SystemTable
->BootServices
->InstallMultipleProtocolInterfaces (
1014 &gSmmCpuPrivate
->SmmCpuHandle
,
1015 &gEfiSmmConfigurationProtocolGuid
,
1016 &gSmmCpuPrivate
->SmmConfiguration
,
1019 ASSERT_EFI_ERROR (Status
);
1022 // Install the SMM CPU Protocol into SMM protocol database
1024 Status
= gSmst
->SmmInstallProtocolInterface (
1026 &gEfiSmmCpuProtocolGuid
,
1027 EFI_NATIVE_INTERFACE
,
1030 ASSERT_EFI_ERROR (Status
);
1033 // Install the SMM Memory Attribute Protocol into SMM protocol database
1035 Status
= gSmst
->SmmInstallProtocolInterface (
1037 &gEdkiiSmmMemoryAttributeProtocolGuid
,
1038 EFI_NATIVE_INTERFACE
,
1039 &mSmmMemoryAttribute
1041 ASSERT_EFI_ERROR (Status
);
1044 // Initialize global buffer for MM MP.
1046 InitializeDataForMmMp ();
1049 // Initialize Package First Thread Index Info.
1051 InitPackageFirstThreadIndexInfo ();
1054 // Install the SMM Mp Protocol into SMM protocol database
1056 Status
= gSmst
->SmmInstallProtocolInterface (
1058 &gEfiMmMpProtocolGuid
,
1059 EFI_NATIVE_INTERFACE
,
1062 ASSERT_EFI_ERROR (Status
);
1065 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
1067 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
1068 Status
= PcdSet64S (PcdCpuHotPlugDataAddress
, (UINT64
)(UINTN
)&mCpuHotPlugData
);
1069 ASSERT_EFI_ERROR (Status
);
1073 // Initialize SMM CPU Services Support
1075 Status
= InitializeSmmCpuServices (mSmmCpuHandle
);
1076 ASSERT_EFI_ERROR (Status
);
1079 // register SMM Ready To Lock Protocol notification
1081 Status
= gSmst
->SmmRegisterProtocolNotify (
1082 &gEfiSmmReadyToLockProtocolGuid
,
1083 SmmReadyToLockEventNotify
,
1086 ASSERT_EFI_ERROR (Status
);
1089 // Initialize SMM Profile feature
1091 InitSmmProfile (Cr3
);
1093 GetAcpiS3EnableFlag ();
1094 InitSmmS3ResumeState (Cr3
);
1096 DEBUG ((DEBUG_INFO
, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
1103 Find out SMRAM information including SMRR base and SMRR size.
1105 @param SmrrBase SMRR base
1106 @param SmrrSize SMRR size
1111 OUT UINT32
*SmrrBase
,
1112 OUT UINT32
*SmrrSize
1117 EFI_SMM_ACCESS2_PROTOCOL
*SmmAccess
;
1118 EFI_SMRAM_DESCRIPTOR
*CurrentSmramRange
;
1124 // Get SMM Access Protocol
1126 Status
= gBS
->LocateProtocol (&gEfiSmmAccess2ProtocolGuid
, NULL
, (VOID
**)&SmmAccess
);
1127 ASSERT_EFI_ERROR (Status
);
1130 // Get SMRAM information
1133 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, NULL
);
1134 ASSERT (Status
== EFI_BUFFER_TOO_SMALL
);
1136 mSmmCpuSmramRanges
= (EFI_SMRAM_DESCRIPTOR
*)AllocatePool (Size
);
1137 ASSERT (mSmmCpuSmramRanges
!= NULL
);
1139 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, mSmmCpuSmramRanges
);
1140 ASSERT_EFI_ERROR (Status
);
1142 mSmmCpuSmramRangeCount
= Size
/ sizeof (EFI_SMRAM_DESCRIPTOR
);
1145 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
1147 CurrentSmramRange
= NULL
;
1148 for (Index
= 0, MaxSize
= SIZE_256KB
- EFI_PAGE_SIZE
; Index
< mSmmCpuSmramRangeCount
; Index
++) {
1150 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
1152 if ((mSmmCpuSmramRanges
[Index
].RegionState
& (EFI_ALLOCATED
| EFI_NEEDS_TESTING
| EFI_NEEDS_ECC_INITIALIZATION
)) != 0) {
1156 if (mSmmCpuSmramRanges
[Index
].CpuStart
>= BASE_1MB
) {
1157 if ((mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
) <= SMRR_MAX_ADDRESS
) {
1158 if (mSmmCpuSmramRanges
[Index
].PhysicalSize
>= MaxSize
) {
1159 MaxSize
= mSmmCpuSmramRanges
[Index
].PhysicalSize
;
1160 CurrentSmramRange
= &mSmmCpuSmramRanges
[Index
];
1166 ASSERT (CurrentSmramRange
!= NULL
);
1168 *SmrrBase
= (UINT32
)CurrentSmramRange
->CpuStart
;
1169 *SmrrSize
= (UINT32
)CurrentSmramRange
->PhysicalSize
;
1173 for (Index
= 0; Index
< mSmmCpuSmramRangeCount
; Index
++) {
1174 if ((mSmmCpuSmramRanges
[Index
].CpuStart
< *SmrrBase
) &&
1175 (*SmrrBase
== (mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
)))
1177 *SmrrBase
= (UINT32
)mSmmCpuSmramRanges
[Index
].CpuStart
;
1178 *SmrrSize
= (UINT32
)(*SmrrSize
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
);
1180 } else if (((*SmrrBase
+ *SmrrSize
) == mSmmCpuSmramRanges
[Index
].CpuStart
) && (mSmmCpuSmramRanges
[Index
].PhysicalSize
> 0)) {
1181 *SmrrSize
= (UINT32
)(*SmrrSize
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
);
1187 DEBUG ((DEBUG_INFO
, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase
, *SmrrSize
));
1191 Configure SMM Code Access Check feature on an AP.
1192 SMM Feature Control MSR will be locked after configuration.
1194 @param[in,out] Buffer Pointer to private data buffer.
1198 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1203 UINT64 SmmFeatureControlMsr
;
1204 UINT64 NewSmmFeatureControlMsr
;
1207 // Retrieve the CPU Index from the context passed in
1209 CpuIndex
= *(UINTN
*)Buffer
;
1212 // Get the current SMM Feature Control MSR value
1214 SmmFeatureControlMsr
= SmmCpuFeaturesGetSmmRegister (CpuIndex
, SmmRegFeatureControl
);
1217 // Compute the new SMM Feature Control MSR value
1219 NewSmmFeatureControlMsr
= SmmFeatureControlMsr
;
1220 if (mSmmCodeAccessCheckEnable
) {
1221 NewSmmFeatureControlMsr
|= SMM_CODE_CHK_EN_BIT
;
1222 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1223 NewSmmFeatureControlMsr
|= SMM_FEATURE_CONTROL_LOCK_BIT
;
1228 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1230 if (NewSmmFeatureControlMsr
!= SmmFeatureControlMsr
) {
1231 SmmCpuFeaturesSetSmmRegister (CpuIndex
, SmmRegFeatureControl
, NewSmmFeatureControlMsr
);
1235 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1237 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1241 Configure SMM Code Access Check feature for all processors.
1242 SMM Feature Control MSR will be locked after configuration.
1245 ConfigSmmCodeAccessCheck (
1253 // Check to see if the Feature Control MSR is supported on this CPU
1255 Index
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1256 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index
, SmmRegFeatureControl
)) {
1257 mSmmCodeAccessCheckEnable
= FALSE
;
1262 // Check to see if the CPU supports the SMM Code Access Check feature
1263 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1265 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP
) & SMM_CODE_ACCESS_CHK_BIT
) == 0) {
1266 mSmmCodeAccessCheckEnable
= FALSE
;
1271 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1273 InitializeSpinLock (mConfigSmmCodeAccessCheckLock
);
1276 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1277 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1279 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1282 // Enable SMM Code Access Check feature on the BSP.
1284 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index
);
1287 // Enable SMM Code Access Check feature for the APs.
1289 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1290 if (Index
!= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
) {
1291 if (gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
== INVALID_APIC_ID
) {
1293 // If this processor does not exist
1299 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1300 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1302 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1305 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1307 Status
= gSmst
->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor
, Index
, &Index
);
1308 ASSERT_EFI_ERROR (Status
);
1311 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1313 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock
)) {
1318 // Release the Config SMM Code Access Check spin lock.
1320 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1326 Allocate pages for code.
1328 @param[in] Pages Number of pages to be allocated.
1330 @return Allocated memory.
1338 EFI_PHYSICAL_ADDRESS Memory
;
1344 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, Pages
, &Memory
);
1345 if (EFI_ERROR (Status
)) {
1349 return (VOID
*)(UINTN
)Memory
;
1353 Allocate aligned pages for code.
1355 @param[in] Pages Number of pages to be allocated.
1356 @param[in] Alignment The requested alignment of the allocation.
1357 Must be a power of two.
1358 If Alignment is zero, then byte alignment is used.
1360 @return Allocated memory.
1363 AllocateAlignedCodePages (
1369 EFI_PHYSICAL_ADDRESS Memory
;
1370 UINTN AlignedMemory
;
1371 UINTN AlignmentMask
;
1372 UINTN UnalignedPages
;
1376 // Alignment must be a power of two or zero.
1378 ASSERT ((Alignment
& (Alignment
- 1)) == 0);
1384 if (Alignment
> EFI_PAGE_SIZE
) {
1386 // Calculate the total number of pages since alignment is larger than page size.
1388 AlignmentMask
= Alignment
- 1;
1389 RealPages
= Pages
+ EFI_SIZE_TO_PAGES (Alignment
);
1391 // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
1393 ASSERT (RealPages
> Pages
);
1395 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, RealPages
, &Memory
);
1396 if (EFI_ERROR (Status
)) {
1400 AlignedMemory
= ((UINTN
)Memory
+ AlignmentMask
) & ~AlignmentMask
;
1401 UnalignedPages
= EFI_SIZE_TO_PAGES (AlignedMemory
- (UINTN
)Memory
);
1402 if (UnalignedPages
> 0) {
1404 // Free first unaligned page(s).
1406 Status
= gSmst
->SmmFreePages (Memory
, UnalignedPages
);
1407 ASSERT_EFI_ERROR (Status
);
1410 Memory
= AlignedMemory
+ EFI_PAGES_TO_SIZE (Pages
);
1411 UnalignedPages
= RealPages
- Pages
- UnalignedPages
;
1412 if (UnalignedPages
> 0) {
1414 // Free last unaligned page(s).
1416 Status
= gSmst
->SmmFreePages (Memory
, UnalignedPages
);
1417 ASSERT_EFI_ERROR (Status
);
1421 // Do not over-allocate pages in this case.
1423 Status
= gSmst
->SmmAllocatePages (AllocateAnyPages
, EfiRuntimeServicesCode
, Pages
, &Memory
);
1424 if (EFI_ERROR (Status
)) {
1428 AlignedMemory
= (UINTN
)Memory
;
1431 return (VOID
*)AlignedMemory
;
1435 Perform the remaining tasks.
1439 PerformRemainingTasks (
1443 if (mSmmReadyToLock
) {
1445 // Start SMM Profile feature
1447 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1452 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1457 // Mark critical region to be read-only in page table
1459 SetMemMapAttributes ();
1461 if (IsRestrictedMemoryAccess ()) {
1463 // For outside SMRAM, we only map SMM communication buffer or MMIO.
1465 SetUefiMemMapAttributes ();
1468 // Set page table itself to be read-only
1470 SetPageTableAttributes ();
1474 // Configure SMM Code Access Check feature if available.
1476 ConfigSmmCodeAccessCheck ();
1478 SmmCpuFeaturesCompleteSmmReadyToLock ();
1481 // Clean SMM ready to lock flag
1483 mSmmReadyToLock
= FALSE
;
1488 Perform the pre tasks.
1496 RestoreSmmConfigurationInS3 ();