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[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c
1 /** @file
2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
3
4 Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
6
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #include "PiSmmCpuDxeSmm.h"
18
19 //
20 // SMM CPU Private Data structure that contains SMM Configuration Protocol
21 // along its supporting fields.
22 //
23 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = {
24 SMM_CPU_PRIVATE_DATA_SIGNATURE, // Signature
25 NULL, // SmmCpuHandle
26 NULL, // Pointer to ProcessorInfo array
27 NULL, // Pointer to Operation array
28 NULL, // Pointer to CpuSaveStateSize array
29 NULL, // Pointer to CpuSaveState array
30 { {0} }, // SmmReservedSmramRegion
31 {
32 SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp
33 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
34 0, // SmmCoreEntryContext.NumberOfCpus
35 NULL, // SmmCoreEntryContext.CpuSaveStateSize
36 NULL // SmmCoreEntryContext.CpuSaveState
37 },
38 NULL, // SmmCoreEntry
39 {
40 mSmmCpuPrivateData.SmmReservedSmramRegion, // SmmConfiguration.SmramReservedRegions
41 RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry
42 },
43 };
44
45 CPU_HOT_PLUG_DATA mCpuHotPlugData = {
46 CPU_HOT_PLUG_DATA_REVISION_1, // Revision
47 0, // Array Length of SmBase and APIC ID
48 NULL, // Pointer to APIC ID array
49 NULL, // Pointer to SMBASE array
50 0, // Reserved
51 0, // SmrrBase
52 0 // SmrrSize
53 };
54
55 //
56 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
57 //
58 SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate = &mSmmCpuPrivateData;
59
60 //
61 // SMM Relocation variables
62 //
63 volatile BOOLEAN *mRebased;
64 volatile BOOLEAN mIsBsp;
65
66 ///
67 /// Handle for the SMM CPU Protocol
68 ///
69 EFI_HANDLE mSmmCpuHandle = NULL;
70
71 ///
72 /// SMM CPU Protocol instance
73 ///
74 EFI_SMM_CPU_PROTOCOL mSmmCpu = {
75 SmmReadSaveState,
76 SmmWriteSaveState
77 };
78
79 ///
80 /// SMM Memory Attribute Protocol instance
81 ///
82 EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = {
83 EdkiiSmmGetMemoryAttributes,
84 EdkiiSmmSetMemoryAttributes,
85 EdkiiSmmClearMemoryAttributes
86 };
87
88 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];
89
90 //
91 // SMM stack information
92 //
93 UINTN mSmmStackArrayBase;
94 UINTN mSmmStackArrayEnd;
95 UINTN mSmmStackSize;
96
97 UINTN mMaxNumberOfCpus = 1;
98 UINTN mNumberOfCpus = 1;
99
100 //
101 // SMM ready to lock flag
102 //
103 BOOLEAN mSmmReadyToLock = FALSE;
104
105 //
106 // Global used to cache PCD for SMM Code Access Check enable
107 //
108 BOOLEAN mSmmCodeAccessCheckEnable = FALSE;
109
110 //
111 // Global copy of the PcdPteMemoryEncryptionAddressOrMask
112 //
113 UINT64 mAddressEncMask = 0;
114
115 //
116 // Spin lock used to serialize setting of SMM Code Access Check feature
117 //
118 SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;
119
120 //
121 // Saved SMM ranges information
122 //
123 EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
124 UINTN mSmmCpuSmramRangeCount;
125
126 UINT8 mPhysicalAddressBits;
127
128 //
129 // Control register contents saved for SMM S3 resume state initialization.
130 //
131 UINT32 mSmmCr4;
132
133 /**
134 Initialize IDT to setup exception handlers for SMM.
135
136 **/
137 VOID
138 InitializeSmmIdt (
139 VOID
140 )
141 {
142 EFI_STATUS Status;
143 BOOLEAN InterruptState;
144 IA32_DESCRIPTOR DxeIdtr;
145
146 //
147 // There are 32 (not 255) entries in it since only processor
148 // generated exceptions will be handled.
149 //
150 gcSmiIdtr.Limit = (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;
151 //
152 // Allocate page aligned IDT, because it might be set as read only.
153 //
154 gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr.Limit + 1));
155 ASSERT (gcSmiIdtr.Base != 0);
156 ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1);
157
158 //
159 // Disable Interrupt and save DXE IDT table
160 //
161 InterruptState = SaveAndDisableInterrupts ();
162 AsmReadIdtr (&DxeIdtr);
163 //
164 // Load SMM temporary IDT table
165 //
166 AsmWriteIdtr (&gcSmiIdtr);
167 //
168 // Setup SMM default exception handlers, SMM IDT table
169 // will be updated and saved in gcSmiIdtr
170 //
171 Status = InitializeCpuExceptionHandlers (NULL);
172 ASSERT_EFI_ERROR (Status);
173 //
174 // Restore DXE IDT table and CPU interrupt
175 //
176 AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr);
177 SetInterruptState (InterruptState);
178 }
179
180 /**
181 Search module name by input IP address and output it.
182
183 @param CallerIpAddress Caller instruction pointer.
184
185 **/
186 VOID
187 DumpModuleInfoByIp (
188 IN UINTN CallerIpAddress
189 )
190 {
191 UINTN Pe32Data;
192 VOID *PdbPointer;
193
194 //
195 // Find Image Base
196 //
197 Pe32Data = PeCoffSearchImageBase (CallerIpAddress);
198 if (Pe32Data != 0) {
199 DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *) CallerIpAddress));
200 PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
201 if (PdbPointer != NULL) {
202 DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));
203 }
204 }
205 }
206
207 /**
208 Read information from the CPU save state.
209
210 @param This EFI_SMM_CPU_PROTOCOL instance
211 @param Width The number of bytes to read from the CPU save state.
212 @param Register Specifies the CPU register to read form the save state.
213 @param CpuIndex Specifies the zero-based index of the CPU save state.
214 @param Buffer Upon return, this holds the CPU register value read from the save state.
215
216 @retval EFI_SUCCESS The register was read from Save State
217 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
218 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
219
220 **/
221 EFI_STATUS
222 EFIAPI
223 SmmReadSaveState (
224 IN CONST EFI_SMM_CPU_PROTOCOL *This,
225 IN UINTN Width,
226 IN EFI_SMM_SAVE_STATE_REGISTER Register,
227 IN UINTN CpuIndex,
228 OUT VOID *Buffer
229 )
230 {
231 EFI_STATUS Status;
232
233 //
234 // Retrieve pointer to the specified CPU's SMM Save State buffer
235 //
236 if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
237 return EFI_INVALID_PARAMETER;
238 }
239
240 //
241 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
242 //
243 if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {
244 //
245 // The pseudo-register only supports the 64-bit size specified by Width.
246 //
247 if (Width != sizeof (UINT64)) {
248 return EFI_INVALID_PARAMETER;
249 }
250 //
251 // If the processor is in SMM at the time the SMI occurred,
252 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
253 // Otherwise, EFI_NOT_FOUND is returned.
254 //
255 if (*(mSmmMpSyncData->CpuData[CpuIndex].Present)) {
256 *(UINT64 *)Buffer = gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId;
257 return EFI_SUCCESS;
258 } else {
259 return EFI_NOT_FOUND;
260 }
261 }
262
263 if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {
264 return EFI_INVALID_PARAMETER;
265 }
266
267 Status = SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
268 if (Status == EFI_UNSUPPORTED) {
269 Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
270 }
271 return Status;
272 }
273
274 /**
275 Write data to the CPU save state.
276
277 @param This EFI_SMM_CPU_PROTOCOL instance
278 @param Width The number of bytes to read from the CPU save state.
279 @param Register Specifies the CPU register to write to the save state.
280 @param CpuIndex Specifies the zero-based index of the CPU save state
281 @param Buffer Upon entry, this holds the new CPU register value.
282
283 @retval EFI_SUCCESS The register was written from Save State
284 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
285 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
286
287 **/
288 EFI_STATUS
289 EFIAPI
290 SmmWriteSaveState (
291 IN CONST EFI_SMM_CPU_PROTOCOL *This,
292 IN UINTN Width,
293 IN EFI_SMM_SAVE_STATE_REGISTER Register,
294 IN UINTN CpuIndex,
295 IN CONST VOID *Buffer
296 )
297 {
298 EFI_STATUS Status;
299
300 //
301 // Retrieve pointer to the specified CPU's SMM Save State buffer
302 //
303 if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
304 return EFI_INVALID_PARAMETER;
305 }
306
307 //
308 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
309 //
310 if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {
311 return EFI_SUCCESS;
312 }
313
314 if (!mSmmMpSyncData->CpuData[CpuIndex].Present) {
315 return EFI_INVALID_PARAMETER;
316 }
317
318 Status = SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
319 if (Status == EFI_UNSUPPORTED) {
320 Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
321 }
322 return Status;
323 }
324
325
326 /**
327 C function for SMI handler. To change all processor's SMMBase Register.
328
329 **/
330 VOID
331 EFIAPI
332 SmmInitHandler (
333 VOID
334 )
335 {
336 UINT32 ApicId;
337 UINTN Index;
338
339 //
340 // Update SMM IDT entries' code segment and load IDT
341 //
342 AsmWriteIdtr (&gcSmiIdtr);
343 ApicId = GetApicId ();
344
345 ASSERT (mNumberOfCpus <= mMaxNumberOfCpus);
346
347 for (Index = 0; Index < mNumberOfCpus; Index++) {
348 if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
349 //
350 // Initialize SMM specific features on the currently executing CPU
351 //
352 SmmCpuFeaturesInitializeProcessor (
353 Index,
354 mIsBsp,
355 gSmmCpuPrivate->ProcessorInfo,
356 &mCpuHotPlugData
357 );
358
359 if (!mSmmS3Flag) {
360 //
361 // Check XD and BTS features on each processor on normal boot
362 //
363 CheckFeatureSupported ();
364 }
365
366 if (mIsBsp) {
367 //
368 // BSP rebase is already done above.
369 // Initialize private data during S3 resume
370 //
371 InitializeMpSyncData ();
372 }
373
374 //
375 // Hook return after RSM to set SMM re-based flag
376 //
377 SemaphoreHook (Index, &mRebased[Index]);
378
379 return;
380 }
381 }
382 ASSERT (FALSE);
383 }
384
385 /**
386 Relocate SmmBases for each processor.
387
388 Execute on first boot and all S3 resumes
389
390 **/
391 VOID
392 EFIAPI
393 SmmRelocateBases (
394 VOID
395 )
396 {
397 UINT8 BakBuf[BACK_BUF_SIZE];
398 SMRAM_SAVE_STATE_MAP BakBuf2;
399 SMRAM_SAVE_STATE_MAP *CpuStatePtr;
400 UINT8 *U8Ptr;
401 UINT32 ApicId;
402 UINTN Index;
403 UINTN BspIndex;
404
405 //
406 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
407 //
408 ASSERT (sizeof (BakBuf) >= gcSmmInitSize);
409
410 //
411 // Patch ASM code template with current CR0, CR3, and CR4 values
412 //
413 gSmmCr0 = (UINT32)AsmReadCr0 ();
414 PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);
415 mSmmCr4 = (UINT32)AsmReadCr4 ();
416 PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);
417
418 //
419 // Patch GDTR for SMM base relocation
420 //
421 gcSmiInitGdtr.Base = gcSmiGdtr.Base;
422 gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;
423
424 U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);
425 CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
426
427 //
428 // Backup original contents at address 0x38000
429 //
430 CopyMem (BakBuf, U8Ptr, sizeof (BakBuf));
431 CopyMem (&BakBuf2, CpuStatePtr, sizeof (BakBuf2));
432
433 //
434 // Load image for relocation
435 //
436 CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize);
437
438 //
439 // Retrieve the local APIC ID of current processor
440 //
441 ApicId = GetApicId ();
442
443 //
444 // Relocate SM bases for all APs
445 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
446 //
447 mIsBsp = FALSE;
448 BspIndex = (UINTN)-1;
449 for (Index = 0; Index < mNumberOfCpus; Index++) {
450 mRebased[Index] = FALSE;
451 if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
452 SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
453 //
454 // Wait for this AP to finish its 1st SMI
455 //
456 while (!mRebased[Index]);
457 } else {
458 //
459 // BSP will be Relocated later
460 //
461 BspIndex = Index;
462 }
463 }
464
465 //
466 // Relocate BSP's SMM base
467 //
468 ASSERT (BspIndex != (UINTN)-1);
469 mIsBsp = TRUE;
470 SendSmiIpi (ApicId);
471 //
472 // Wait for the BSP to finish its 1st SMI
473 //
474 while (!mRebased[BspIndex]);
475
476 //
477 // Restore contents at address 0x38000
478 //
479 CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2));
480 CopyMem (U8Ptr, BakBuf, sizeof (BakBuf));
481 }
482
483 /**
484 SMM Ready To Lock event notification handler.
485
486 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
487 perform additional lock actions that must be performed from SMM on the next SMI.
488
489 @param[in] Protocol Points to the protocol's unique identifier.
490 @param[in] Interface Points to the interface instance.
491 @param[in] Handle The handle on which the interface was installed.
492
493 @retval EFI_SUCCESS Notification handler runs successfully.
494 **/
495 EFI_STATUS
496 EFIAPI
497 SmmReadyToLockEventNotify (
498 IN CONST EFI_GUID *Protocol,
499 IN VOID *Interface,
500 IN EFI_HANDLE Handle
501 )
502 {
503 GetAcpiCpuData ();
504
505 //
506 // Cache a copy of UEFI memory map before we start profiling feature.
507 //
508 GetUefiMemoryMap ();
509
510 //
511 // Set SMM ready to lock flag and return
512 //
513 mSmmReadyToLock = TRUE;
514 return EFI_SUCCESS;
515 }
516
517 /**
518 The module Entry Point of the CPU SMM driver.
519
520 @param ImageHandle The firmware allocated handle for the EFI image.
521 @param SystemTable A pointer to the EFI System Table.
522
523 @retval EFI_SUCCESS The entry point is executed successfully.
524 @retval Other Some error occurs when executing this entry point.
525
526 **/
527 EFI_STATUS
528 EFIAPI
529 PiCpuSmmEntry (
530 IN EFI_HANDLE ImageHandle,
531 IN EFI_SYSTEM_TABLE *SystemTable
532 )
533 {
534 EFI_STATUS Status;
535 EFI_MP_SERVICES_PROTOCOL *MpServices;
536 UINTN NumberOfEnabledProcessors;
537 UINTN Index;
538 VOID *Buffer;
539 UINTN BufferPages;
540 UINTN TileCodeSize;
541 UINTN TileDataSize;
542 UINTN TileSize;
543 UINT8 *Stacks;
544 VOID *Registration;
545 UINT32 RegEax;
546 UINT32 RegEdx;
547 UINTN FamilyId;
548 UINTN ModelId;
549 UINT32 Cr3;
550
551 //
552 // Initialize address fixup
553 //
554 PiSmmCpuSmmInitFixupAddress ();
555 PiSmmCpuSmiEntryFixupAddress ();
556
557 //
558 // Initialize Debug Agent to support source level debug in SMM code
559 //
560 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL);
561
562 //
563 // Report the start of CPU SMM initialization.
564 //
565 REPORT_STATUS_CODE (
566 EFI_PROGRESS_CODE,
567 EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT
568 );
569
570 //
571 // Fix segment address of the long-mode-switch jump
572 //
573 if (sizeof (UINTN) == sizeof (UINT64)) {
574 gSmmJmpAddr.Segment = LONG_MODE_CODE_SEGMENT;
575 }
576
577 //
578 // Find out SMRR Base and SMRR Size
579 //
580 FindSmramInfo (&mCpuHotPlugData.SmrrBase, &mCpuHotPlugData.SmrrSize);
581
582 //
583 // Get MP Services Protocol
584 //
585 Status = SystemTable->BootServices->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices);
586 ASSERT_EFI_ERROR (Status);
587
588 //
589 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
590 //
591 Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus, &NumberOfEnabledProcessors);
592 ASSERT_EFI_ERROR (Status);
593 ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
594
595 //
596 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
597 // A constant BSP index makes no sense because it may be hot removed.
598 //
599 DEBUG_CODE (
600 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
601
602 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));
603 }
604 );
605
606 //
607 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
608 //
609 mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable);
610 DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));
611
612 //
613 // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.
614 // Make sure AddressEncMask is contained to smallest supported address field.
615 //
616 mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
617 DEBUG ((EFI_D_INFO, "mAddressEncMask = 0x%lx\n", mAddressEncMask));
618
619 //
620 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
621 //
622 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
623 mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
624 } else {
625 mMaxNumberOfCpus = mNumberOfCpus;
626 }
627 gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;
628
629 //
630 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
631 // allocated buffer. The minimum size of this buffer for a uniprocessor system
632 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
633 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
634 // then the SMI entry point and the CPU save state areas can be tiles to minimize
635 // the total amount SMRAM required for all the CPUs. The tile size can be computed
636 // by adding the // CPU save state size, any extra CPU specific context, and
637 // the size of code that must be placed at the SMI entry point to transfer
638 // control to a C function in the native SMM execution mode. This size is
639 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
640 // The total amount of memory required is the maximum number of CPUs that
641 // platform supports times the tile size. The picture below shows the tiling,
642 // where m is the number of tiles that fit in 32KB.
643 //
644 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
645 // | CPU m+1 Save State |
646 // +-----------------------------+
647 // | CPU m+1 Extra Data |
648 // +-----------------------------+
649 // | Padding |
650 // +-----------------------------+
651 // | CPU 2m SMI Entry |
652 // +#############################+ <-- Base of allocated buffer + 64 KB
653 // | CPU m-1 Save State |
654 // +-----------------------------+
655 // | CPU m-1 Extra Data |
656 // +-----------------------------+
657 // | Padding |
658 // +-----------------------------+
659 // | CPU 2m-1 SMI Entry |
660 // +=============================+ <-- 2^n offset from Base of allocated buffer
661 // | . . . . . . . . . . . . |
662 // +=============================+ <-- 2^n offset from Base of allocated buffer
663 // | CPU 2 Save State |
664 // +-----------------------------+
665 // | CPU 2 Extra Data |
666 // +-----------------------------+
667 // | Padding |
668 // +-----------------------------+
669 // | CPU m+1 SMI Entry |
670 // +=============================+ <-- Base of allocated buffer + 32 KB
671 // | CPU 1 Save State |
672 // +-----------------------------+
673 // | CPU 1 Extra Data |
674 // +-----------------------------+
675 // | Padding |
676 // +-----------------------------+
677 // | CPU m SMI Entry |
678 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
679 // | CPU 0 Save State |
680 // +-----------------------------+
681 // | CPU 0 Extra Data |
682 // +-----------------------------+
683 // | Padding |
684 // +-----------------------------+
685 // | CPU m-1 SMI Entry |
686 // +=============================+ <-- 2^n offset from Base of allocated buffer
687 // | . . . . . . . . . . . . |
688 // +=============================+ <-- 2^n offset from Base of allocated buffer
689 // | Padding |
690 // +-----------------------------+
691 // | CPU 1 SMI Entry |
692 // +=============================+ <-- 2^n offset from Base of allocated buffer
693 // | Padding |
694 // +-----------------------------+
695 // | CPU 0 SMI Entry |
696 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
697 //
698
699 //
700 // Retrieve CPU Family
701 //
702 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
703 FamilyId = (RegEax >> 8) & 0xf;
704 ModelId = (RegEax >> 4) & 0xf;
705 if (FamilyId == 0x06 || FamilyId == 0x0f) {
706 ModelId = ModelId | ((RegEax >> 12) & 0xf0);
707 }
708
709 RegEdx = 0;
710 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
711 if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
712 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
713 }
714 //
715 // Determine the mode of the CPU at the time an SMI occurs
716 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
717 // Volume 3C, Section 34.4.1.1
718 //
719 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
720 if ((RegEdx & BIT29) != 0) {
721 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
722 }
723 if (FamilyId == 0x06) {
724 if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) {
725 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
726 }
727 }
728
729 //
730 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
731 // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
732 // This size is rounded up to nearest power of 2.
733 //
734 TileCodeSize = GetSmiHandlerSize ();
735 TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
736 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
737 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
738 TileSize = TileDataSize + TileCodeSize - 1;
739 TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
740 DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
741
742 //
743 // If the TileSize is larger than space available for the SMI Handler of
744 // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save
745 // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then
746 // the SMI Handler size must be reduced or the size of the extra CPU specific
747 // context must be reduced.
748 //
749 ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));
750
751 //
752 // Allocate buffer for all of the tiles.
753 //
754 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
755 // Volume 3C, Section 34.11 SMBASE Relocation
756 // For Pentium and Intel486 processors, the SMBASE values must be
757 // aligned on a 32-KByte boundary or the processor will enter shutdown
758 // state during the execution of a RSM instruction.
759 //
760 // Intel486 processors: FamilyId is 4
761 // Pentium processors : FamilyId is 5
762 //
763 BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1));
764 if ((FamilyId == 4) || (FamilyId == 5)) {
765 Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB);
766 } else {
767 Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);
768 }
769 ASSERT (Buffer != NULL);
770 DEBUG ((EFI_D_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages)));
771
772 //
773 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
774 //
775 gSmmCpuPrivate->ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus);
776 ASSERT (gSmmCpuPrivate->ProcessorInfo != NULL);
777
778 gSmmCpuPrivate->Operation = (SMM_CPU_OPERATION *)AllocatePool (sizeof (SMM_CPU_OPERATION) * mMaxNumberOfCpus);
779 ASSERT (gSmmCpuPrivate->Operation != NULL);
780
781 gSmmCpuPrivate->CpuSaveStateSize = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);
782 ASSERT (gSmmCpuPrivate->CpuSaveStateSize != NULL);
783
784 gSmmCpuPrivate->CpuSaveState = (VOID **)AllocatePool (sizeof (VOID *) * mMaxNumberOfCpus);
785 ASSERT (gSmmCpuPrivate->CpuSaveState != NULL);
786
787 mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize;
788 mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState = gSmmCpuPrivate->CpuSaveState;
789
790 //
791 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
792 //
793 mCpuHotPlugData.ApicId = (UINT64 *)AllocatePool (sizeof (UINT64) * mMaxNumberOfCpus);
794 ASSERT (mCpuHotPlugData.ApicId != NULL);
795 mCpuHotPlugData.SmBase = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);
796 ASSERT (mCpuHotPlugData.SmBase != NULL);
797 mCpuHotPlugData.ArrayLength = (UINT32)mMaxNumberOfCpus;
798
799 //
800 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
801 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
802 // size for each CPU in the platform
803 //
804 for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
805 mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
806 gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP);
807 gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);
808 gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
809
810 if (Index < mNumberOfCpus) {
811 Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]);
812 ASSERT_EFI_ERROR (Status);
813 mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;
814
815 DEBUG ((EFI_D_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
816 Index,
817 (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,
818 mCpuHotPlugData.SmBase[Index],
819 gSmmCpuPrivate->CpuSaveState[Index],
820 gSmmCpuPrivate->CpuSaveStateSize[Index]
821 ));
822 } else {
823 gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID;
824 mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID;
825 }
826 }
827
828 //
829 // Allocate SMI stacks for all processors.
830 //
831 if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
832 //
833 // 2 more pages is allocated for each processor.
834 // one is guard page and the other is known good stack.
835 //
836 // +-------------------------------------------+-----+-------------------------------------------+
837 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
838 // +-------------------------------------------+-----+-------------------------------------------+
839 // | | | |
840 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
841 //
842 mSmmStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2);
843 Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2));
844 ASSERT (Stacks != NULL);
845 mSmmStackArrayBase = (UINTN)Stacks;
846 mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize - 1;
847 } else {
848 mSmmStackSize = PcdGet32 (PcdCpuSmmStackSize);
849 Stacks = (UINT8 *) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize));
850 ASSERT (Stacks != NULL);
851 }
852
853 //
854 // Set SMI stack for SMM base relocation
855 //
856 gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));
857
858 //
859 // Initialize IDT
860 //
861 InitializeSmmIdt ();
862
863 //
864 // Relocate SMM Base addresses to the ones allocated from SMRAM
865 //
866 mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus);
867 ASSERT (mRebased != NULL);
868 SmmRelocateBases ();
869
870 //
871 // Call hook for BSP to perform extra actions in normal mode after all
872 // SMM base addresses have been relocated on all CPUs
873 //
874 SmmCpuFeaturesSmmRelocationComplete ();
875
876 DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported));
877
878 //
879 // SMM Time initialization
880 //
881 InitializeSmmTimer ();
882
883 //
884 // Initialize MP globals
885 //
886 Cr3 = InitializeMpServiceData (Stacks, mSmmStackSize);
887
888 //
889 // Fill in SMM Reserved Regions
890 //
891 gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0;
892 gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize = 0;
893
894 //
895 // Install the SMM Configuration Protocol onto a new handle on the handle database.
896 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
897 // to an SMRAM address will be present in the handle database
898 //
899 Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (
900 &gSmmCpuPrivate->SmmCpuHandle,
901 &gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration,
902 NULL
903 );
904 ASSERT_EFI_ERROR (Status);
905
906 //
907 // Install the SMM CPU Protocol into SMM protocol database
908 //
909 Status = gSmst->SmmInstallProtocolInterface (
910 &mSmmCpuHandle,
911 &gEfiSmmCpuProtocolGuid,
912 EFI_NATIVE_INTERFACE,
913 &mSmmCpu
914 );
915 ASSERT_EFI_ERROR (Status);
916
917 //
918 // Install the SMM Memory Attribute Protocol into SMM protocol database
919 //
920 Status = gSmst->SmmInstallProtocolInterface (
921 &mSmmCpuHandle,
922 &gEdkiiSmmMemoryAttributeProtocolGuid,
923 EFI_NATIVE_INTERFACE,
924 &mSmmMemoryAttribute
925 );
926 ASSERT_EFI_ERROR (Status);
927
928 //
929 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
930 //
931 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
932 Status = PcdSet64S (PcdCpuHotPlugDataAddress, (UINT64)(UINTN)&mCpuHotPlugData);
933 ASSERT_EFI_ERROR (Status);
934 }
935
936 //
937 // Initialize SMM CPU Services Support
938 //
939 Status = InitializeSmmCpuServices (mSmmCpuHandle);
940 ASSERT_EFI_ERROR (Status);
941
942 //
943 // register SMM Ready To Lock Protocol notification
944 //
945 Status = gSmst->SmmRegisterProtocolNotify (
946 &gEfiSmmReadyToLockProtocolGuid,
947 SmmReadyToLockEventNotify,
948 &Registration
949 );
950 ASSERT_EFI_ERROR (Status);
951
952 //
953 // Initialize SMM Profile feature
954 //
955 InitSmmProfile (Cr3);
956
957 GetAcpiS3EnableFlag ();
958 InitSmmS3ResumeState (Cr3);
959
960 DEBUG ((EFI_D_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
961
962 return EFI_SUCCESS;
963 }
964
965 /**
966
967 Find out SMRAM information including SMRR base and SMRR size.
968
969 @param SmrrBase SMRR base
970 @param SmrrSize SMRR size
971
972 **/
973 VOID
974 FindSmramInfo (
975 OUT UINT32 *SmrrBase,
976 OUT UINT32 *SmrrSize
977 )
978 {
979 EFI_STATUS Status;
980 UINTN Size;
981 EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
982 EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;
983 UINTN Index;
984 UINT64 MaxSize;
985 BOOLEAN Found;
986
987 //
988 // Get SMM Access Protocol
989 //
990 Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);
991 ASSERT_EFI_ERROR (Status);
992
993 //
994 // Get SMRAM information
995 //
996 Size = 0;
997 Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);
998 ASSERT (Status == EFI_BUFFER_TOO_SMALL);
999
1000 mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
1001 ASSERT (mSmmCpuSmramRanges != NULL);
1002
1003 Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRanges);
1004 ASSERT_EFI_ERROR (Status);
1005
1006 mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
1007
1008 //
1009 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
1010 //
1011 CurrentSmramRange = NULL;
1012 for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCpuSmramRangeCount; Index++) {
1013 //
1014 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
1015 //
1016 if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
1017 continue;
1018 }
1019
1020 if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {
1021 if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {
1022 if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {
1023 MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;
1024 CurrentSmramRange = &mSmmCpuSmramRanges[Index];
1025 }
1026 }
1027 }
1028 }
1029
1030 ASSERT (CurrentSmramRange != NULL);
1031
1032 *SmrrBase = (UINT32)CurrentSmramRange->CpuStart;
1033 *SmrrSize = (UINT32)CurrentSmramRange->PhysicalSize;
1034
1035 do {
1036 Found = FALSE;
1037 for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
1038 if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&
1039 *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) {
1040 *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;
1041 *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
1042 Found = TRUE;
1043 } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) {
1044 *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
1045 Found = TRUE;
1046 }
1047 }
1048 } while (Found);
1049
1050 DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));
1051 }
1052
1053 /**
1054 Configure SMM Code Access Check feature on an AP.
1055 SMM Feature Control MSR will be locked after configuration.
1056
1057 @param[in,out] Buffer Pointer to private data buffer.
1058 **/
1059 VOID
1060 EFIAPI
1061 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1062 IN OUT VOID *Buffer
1063 )
1064 {
1065 UINTN CpuIndex;
1066 UINT64 SmmFeatureControlMsr;
1067 UINT64 NewSmmFeatureControlMsr;
1068
1069 //
1070 // Retrieve the CPU Index from the context passed in
1071 //
1072 CpuIndex = *(UINTN *)Buffer;
1073
1074 //
1075 // Get the current SMM Feature Control MSR value
1076 //
1077 SmmFeatureControlMsr = SmmCpuFeaturesGetSmmRegister (CpuIndex, SmmRegFeatureControl);
1078
1079 //
1080 // Compute the new SMM Feature Control MSR value
1081 //
1082 NewSmmFeatureControlMsr = SmmFeatureControlMsr;
1083 if (mSmmCodeAccessCheckEnable) {
1084 NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT;
1085 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {
1086 NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT;
1087 }
1088 }
1089
1090 //
1091 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1092 //
1093 if (NewSmmFeatureControlMsr != SmmFeatureControlMsr) {
1094 SmmCpuFeaturesSetSmmRegister (CpuIndex, SmmRegFeatureControl, NewSmmFeatureControlMsr);
1095 }
1096
1097 //
1098 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1099 //
1100 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
1101 }
1102
1103 /**
1104 Configure SMM Code Access Check feature for all processors.
1105 SMM Feature Control MSR will be locked after configuration.
1106 **/
1107 VOID
1108 ConfigSmmCodeAccessCheck (
1109 VOID
1110 )
1111 {
1112 UINTN Index;
1113 EFI_STATUS Status;
1114
1115 //
1116 // Check to see if the Feature Control MSR is supported on this CPU
1117 //
1118 Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
1119 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) {
1120 mSmmCodeAccessCheckEnable = FALSE;
1121 return;
1122 }
1123
1124 //
1125 // Check to see if the CPU supports the SMM Code Access Check feature
1126 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1127 //
1128 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) {
1129 mSmmCodeAccessCheckEnable = FALSE;
1130 return;
1131 }
1132
1133 //
1134 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1135 //
1136 InitializeSpinLock (mConfigSmmCodeAccessCheckLock);
1137
1138 //
1139 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1140 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1141 //
1142 AcquireSpinLock (mConfigSmmCodeAccessCheckLock);
1143
1144 //
1145 // Enable SMM Code Access Check feature on the BSP.
1146 //
1147 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index);
1148
1149 //
1150 // Enable SMM Code Access Check feature for the APs.
1151 //
1152 for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
1153 if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {
1154 if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
1155 //
1156 // If this processor does not exist
1157 //
1158 continue;
1159 }
1160 //
1161 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1162 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1163 //
1164 AcquireSpinLock (mConfigSmmCodeAccessCheckLock);
1165
1166 //
1167 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1168 //
1169 Status = gSmst->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor, Index, &Index);
1170 ASSERT_EFI_ERROR (Status);
1171
1172 //
1173 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1174 //
1175 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock)) {
1176 CpuPause ();
1177 }
1178
1179 //
1180 // Release the Config SMM Code Access Check spin lock.
1181 //
1182 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
1183 }
1184 }
1185 }
1186
1187 /**
1188 This API provides a way to allocate memory for page table.
1189
1190 This API can be called more once to allocate memory for page tables.
1191
1192 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
1193 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
1194 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
1195 returned.
1196
1197 @param Pages The number of 4 KB pages to allocate.
1198
1199 @return A pointer to the allocated buffer or NULL if allocation fails.
1200
1201 **/
1202 VOID *
1203 AllocatePageTableMemory (
1204 IN UINTN Pages
1205 )
1206 {
1207 VOID *Buffer;
1208
1209 Buffer = SmmCpuFeaturesAllocatePageTableMemory (Pages);
1210 if (Buffer != NULL) {
1211 return Buffer;
1212 }
1213 return AllocatePages (Pages);
1214 }
1215
1216 /**
1217 Allocate pages for code.
1218
1219 @param[in] Pages Number of pages to be allocated.
1220
1221 @return Allocated memory.
1222 **/
1223 VOID *
1224 AllocateCodePages (
1225 IN UINTN Pages
1226 )
1227 {
1228 EFI_STATUS Status;
1229 EFI_PHYSICAL_ADDRESS Memory;
1230
1231 if (Pages == 0) {
1232 return NULL;
1233 }
1234
1235 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);
1236 if (EFI_ERROR (Status)) {
1237 return NULL;
1238 }
1239 return (VOID *) (UINTN) Memory;
1240 }
1241
1242 /**
1243 Allocate aligned pages for code.
1244
1245 @param[in] Pages Number of pages to be allocated.
1246 @param[in] Alignment The requested alignment of the allocation.
1247 Must be a power of two.
1248 If Alignment is zero, then byte alignment is used.
1249
1250 @return Allocated memory.
1251 **/
1252 VOID *
1253 AllocateAlignedCodePages (
1254 IN UINTN Pages,
1255 IN UINTN Alignment
1256 )
1257 {
1258 EFI_STATUS Status;
1259 EFI_PHYSICAL_ADDRESS Memory;
1260 UINTN AlignedMemory;
1261 UINTN AlignmentMask;
1262 UINTN UnalignedPages;
1263 UINTN RealPages;
1264
1265 //
1266 // Alignment must be a power of two or zero.
1267 //
1268 ASSERT ((Alignment & (Alignment - 1)) == 0);
1269
1270 if (Pages == 0) {
1271 return NULL;
1272 }
1273 if (Alignment > EFI_PAGE_SIZE) {
1274 //
1275 // Calculate the total number of pages since alignment is larger than page size.
1276 //
1277 AlignmentMask = Alignment - 1;
1278 RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
1279 //
1280 // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
1281 //
1282 ASSERT (RealPages > Pages);
1283
1284 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory);
1285 if (EFI_ERROR (Status)) {
1286 return NULL;
1287 }
1288 AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
1289 UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
1290 if (UnalignedPages > 0) {
1291 //
1292 // Free first unaligned page(s).
1293 //
1294 Status = gSmst->SmmFreePages (Memory, UnalignedPages);
1295 ASSERT_EFI_ERROR (Status);
1296 }
1297 Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);
1298 UnalignedPages = RealPages - Pages - UnalignedPages;
1299 if (UnalignedPages > 0) {
1300 //
1301 // Free last unaligned page(s).
1302 //
1303 Status = gSmst->SmmFreePages (Memory, UnalignedPages);
1304 ASSERT_EFI_ERROR (Status);
1305 }
1306 } else {
1307 //
1308 // Do not over-allocate pages in this case.
1309 //
1310 Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);
1311 if (EFI_ERROR (Status)) {
1312 return NULL;
1313 }
1314 AlignedMemory = (UINTN) Memory;
1315 }
1316 return (VOID *) AlignedMemory;
1317 }
1318
1319 /**
1320 Perform the remaining tasks.
1321
1322 **/
1323 VOID
1324 PerformRemainingTasks (
1325 VOID
1326 )
1327 {
1328 if (mSmmReadyToLock) {
1329 //
1330 // Start SMM Profile feature
1331 //
1332 if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
1333 SmmProfileStart ();
1334 }
1335 //
1336 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1337 //
1338 InitPaging ();
1339
1340 //
1341 // Mark critical region to be read-only in page table
1342 //
1343 SetMemMapAttributes ();
1344
1345 //
1346 // For outside SMRAM, we only map SMM communication buffer or MMIO.
1347 //
1348 SetUefiMemMapAttributes ();
1349
1350 //
1351 // Set page table itself to be read-only
1352 //
1353 SetPageTableAttributes ();
1354
1355 //
1356 // Configure SMM Code Access Check feature if available.
1357 //
1358 ConfigSmmCodeAccessCheck ();
1359
1360 SmmCpuFeaturesCompleteSmmReadyToLock ();
1361
1362 //
1363 // Clean SMM ready to lock flag
1364 //
1365 mSmmReadyToLock = FALSE;
1366 }
1367 }
1368
1369 /**
1370 Perform the pre tasks.
1371
1372 **/
1373 VOID
1374 PerformPreTasks (
1375 VOID
1376 )
1377 {
1378 RestoreSmmConfigurationInS3 ();
1379 }
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