2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PiSmmCpuDxeSmm.h"
18 // SMM CPU Private Data structure that contains SMM Configuration Protocol
19 // along its supporting fields.
21 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData
= {
22 SMM_CPU_PRIVATE_DATA_SIGNATURE
, // Signature
24 NULL
, // Pointer to ProcessorInfo array
25 NULL
, // Pointer to Operation array
26 NULL
, // Pointer to CpuSaveStateSize array
27 NULL
, // Pointer to CpuSaveState array
28 { {0} }, // SmmReservedSmramRegion
30 SmmStartupThisAp
, // SmmCoreEntryContext.SmmStartupThisAp
31 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
32 0, // SmmCoreEntryContext.NumberOfCpus
33 NULL
, // SmmCoreEntryContext.CpuSaveStateSize
34 NULL
// SmmCoreEntryContext.CpuSaveState
38 mSmmCpuPrivateData
.SmmReservedSmramRegion
, // SmmConfiguration.SmramReservedRegions
39 RegisterSmmEntry
// SmmConfiguration.RegisterSmmEntry
43 CPU_HOT_PLUG_DATA mCpuHotPlugData
= {
44 CPU_HOT_PLUG_DATA_REVISION_1
, // Revision
45 0, // Array Length of SmBase and APIC ID
46 NULL
, // Pointer to APIC ID array
47 NULL
, // Pointer to SMBASE array
54 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
56 SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
= &mSmmCpuPrivateData
;
59 // SMM Relocation variables
61 volatile BOOLEAN
*mRebased
;
62 volatile BOOLEAN mIsBsp
;
65 /// Handle for the SMM CPU Protocol
67 EFI_HANDLE mSmmCpuHandle
= NULL
;
70 /// SMM CPU Protocol instance
72 EFI_SMM_CPU_PROTOCOL mSmmCpu
= {
77 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable
[EXCEPTION_VECTOR_NUMBER
];
80 /// SMM CPU Save State Protocol instance
82 EFI_SMM_CPU_SAVE_STATE_PROTOCOL mSmmCpuSaveState
= {
87 // SMM stack information
89 UINTN mSmmStackArrayBase
;
90 UINTN mSmmStackArrayEnd
;
94 // Pointer to structure used during S3 Resume
96 SMM_S3_RESUME_STATE
*mSmmS3ResumeState
= NULL
;
98 UINTN mMaxNumberOfCpus
= 1;
99 UINTN mNumberOfCpus
= 1;
102 // SMM ready to lock flag
104 BOOLEAN mSmmReadyToLock
= FALSE
;
107 // Global used to cache PCD for SMM Code Access Check enable
109 BOOLEAN mSmmCodeAccessCheckEnable
= FALSE
;
112 // Spin lock used to serialize setting of SMM Code Access Check feature
114 SPIN_LOCK mConfigSmmCodeAccessCheckLock
;
117 Initialize IDT to setup exception handlers for SMM.
126 BOOLEAN InterruptState
;
127 IA32_DESCRIPTOR DxeIdtr
;
129 // Disable Interrupt and save DXE IDT table
131 InterruptState
= SaveAndDisableInterrupts ();
132 AsmReadIdtr (&DxeIdtr
);
134 // Load SMM temporary IDT table
136 AsmWriteIdtr (&gcSmiIdtr
);
138 // Setup SMM default exception handlers, SMM IDT table
139 // will be updated and saved in gcSmiIdtr
141 Status
= InitializeCpuExceptionHandlers (NULL
);
142 ASSERT_EFI_ERROR (Status
);
144 // Restore DXE IDT table and CPU interrupt
146 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &DxeIdtr
);
147 SetInterruptState (InterruptState
);
151 Search module name by input IP address and output it.
153 @param CallerIpAddress Caller instruction pointer.
158 IN UINTN CallerIpAddress
162 EFI_IMAGE_DOS_HEADER
*DosHdr
;
163 EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr
;
165 UINT64 DumpIpAddress
;
170 Pe32Data
= CallerIpAddress
& ~(SIZE_4KB
- 1);
171 while (Pe32Data
!= 0) {
172 DosHdr
= (EFI_IMAGE_DOS_HEADER
*) Pe32Data
;
173 if (DosHdr
->e_magic
== EFI_IMAGE_DOS_SIGNATURE
) {
175 // DOS image header is present, so read the PE header after the DOS image header.
177 Hdr
.Pe32
= (EFI_IMAGE_NT_HEADERS32
*)(Pe32Data
+ (UINTN
) ((DosHdr
->e_lfanew
) & 0x0ffff));
179 // Make sure PE header address does not overflow and is less than the initial address.
181 if (((UINTN
)Hdr
.Pe32
> Pe32Data
) && ((UINTN
)Hdr
.Pe32
< CallerIpAddress
)) {
182 if (Hdr
.Pe32
->Signature
== EFI_IMAGE_NT_SIGNATURE
) {
192 // Not found the image base, check the previous aligned address
194 Pe32Data
-= SIZE_4KB
;
197 DumpIpAddress
= CallerIpAddress
;
198 DEBUG ((EFI_D_ERROR
, "It is invoked from the instruction before IP(0x%lx)", DumpIpAddress
));
201 PdbPointer
= PeCoffLoaderGetPdbPointer ((VOID
*) Pe32Data
);
202 if (PdbPointer
!= NULL
) {
203 DEBUG ((EFI_D_ERROR
, " in module (%a)", PdbPointer
));
209 Read information from the CPU save state.
211 @param This EFI_SMM_CPU_PROTOCOL instance
212 @param Width The number of bytes to read from the CPU save state.
213 @param Register Specifies the CPU register to read form the save state.
214 @param CpuIndex Specifies the zero-based index of the CPU save state.
215 @param Buffer Upon return, this holds the CPU register value read from the save state.
217 @retval EFI_SUCCESS The register was read from Save State
218 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
219 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
225 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
227 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
235 // Retrieve pointer to the specified CPU's SMM Save State buffer
237 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
238 return EFI_INVALID_PARAMETER
;
242 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
244 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
246 // The pseudo-register only supports the 64-bit size specified by Width.
248 if (Width
!= sizeof (UINT64
)) {
249 return EFI_INVALID_PARAMETER
;
252 // If the processor is in SMM at the time the SMI occurred,
253 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
254 // Otherwise, EFI_NOT_FOUND is returned.
256 if (mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
257 *(UINT64
*)Buffer
= gSmmCpuPrivate
->ProcessorInfo
[CpuIndex
].ProcessorId
;
260 return EFI_NOT_FOUND
;
264 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
265 return EFI_INVALID_PARAMETER
;
268 Status
= SmmCpuFeaturesReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
269 if (Status
== EFI_UNSUPPORTED
) {
270 Status
= ReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
276 Write data to the CPU save state.
278 @param This EFI_SMM_CPU_PROTOCOL instance
279 @param Width The number of bytes to read from the CPU save state.
280 @param Register Specifies the CPU register to write to the save state.
281 @param CpuIndex Specifies the zero-based index of the CPU save state
282 @param Buffer Upon entry, this holds the new CPU register value.
284 @retval EFI_SUCCESS The register was written from Save State
285 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
286 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
292 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
294 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
296 IN CONST VOID
*Buffer
302 // Retrieve pointer to the specified CPU's SMM Save State buffer
304 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
305 return EFI_INVALID_PARAMETER
;
309 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
311 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
315 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
316 return EFI_INVALID_PARAMETER
;
319 Status
= SmmCpuFeaturesWriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
320 if (Status
== EFI_UNSUPPORTED
) {
321 Status
= WriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
328 C function for SMI handler. To change all processor's SMMBase Register.
341 // Update SMM IDT entries' code segment and load IDT
343 AsmWriteIdtr (&gcSmiIdtr
);
344 ApicId
= GetApicId ();
346 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
348 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
349 if (ApicId
== (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
351 // Initialize SMM specific features on the currently executing CPU
353 SmmCpuFeaturesInitializeProcessor (
356 gSmmCpuPrivate
->ProcessorInfo
,
362 // BSP rebase is already done above.
363 // Initialize private data during S3 resume
365 InitializeMpSyncData ();
369 // Hook return after RSM to set SMM re-based flag
371 SemaphoreHook (Index
, &mRebased
[Index
]);
380 Relocate SmmBases for each processor.
382 Execute on first boot and all S3 resumes
391 UINT8 BakBuf
[BACK_BUF_SIZE
];
392 SMRAM_SAVE_STATE_MAP BakBuf2
;
393 SMRAM_SAVE_STATE_MAP
*CpuStatePtr
;
400 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
402 ASSERT (sizeof (BakBuf
) >= gcSmmInitSize
);
405 // Patch ASM code template with current CR0, CR3, and CR4 values
407 gSmmCr0
= (UINT32
)AsmReadCr0 ();
408 gSmmCr3
= (UINT32
)AsmReadCr3 ();
409 gSmmCr4
= (UINT32
)AsmReadCr4 ();
412 // Patch GDTR for SMM base relocation
414 gcSmiInitGdtr
.Base
= gcSmiGdtr
.Base
;
415 gcSmiInitGdtr
.Limit
= gcSmiGdtr
.Limit
;
417 U8Ptr
= (UINT8
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMM_HANDLER_OFFSET
);
418 CpuStatePtr
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
421 // Backup original contents at address 0x38000
423 CopyMem (BakBuf
, U8Ptr
, sizeof (BakBuf
));
424 CopyMem (&BakBuf2
, CpuStatePtr
, sizeof (BakBuf2
));
427 // Load image for relocation
429 CopyMem (U8Ptr
, gcSmmInitTemplate
, gcSmmInitSize
);
432 // Retrieve the local APIC ID of current processor
434 ApicId
= GetApicId ();
437 // Relocate SM bases for all APs
438 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
441 BspIndex
= (UINTN
)-1;
442 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
443 mRebased
[Index
] = FALSE
;
444 if (ApicId
!= (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
445 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
447 // Wait for this AP to finish its 1st SMI
449 while (!mRebased
[Index
]);
452 // BSP will be Relocated later
459 // Relocate BSP's SMM base
461 ASSERT (BspIndex
!= (UINTN
)-1);
465 // Wait for the BSP to finish its 1st SMI
467 while (!mRebased
[BspIndex
]);
470 // Restore contents at address 0x38000
472 CopyMem (CpuStatePtr
, &BakBuf2
, sizeof (BakBuf2
));
473 CopyMem (U8Ptr
, BakBuf
, sizeof (BakBuf
));
477 Perform SMM initialization for all processors in the S3 boot path.
479 For a native platform, MP initialization in the S3 boot path is also performed in this function.
487 SMM_S3_RESUME_STATE
*SmmS3ResumeState
;
488 IA32_DESCRIPTOR Ia32Idtr
;
489 IA32_DESCRIPTOR X64Idtr
;
490 IA32_IDT_GATE_DESCRIPTOR IdtEntryTable
[EXCEPTION_VECTOR_NUMBER
];
493 DEBUG ((EFI_D_INFO
, "SmmRestoreCpu()\n"));
496 // See if there is enough context to resume PEI Phase
498 if (mSmmS3ResumeState
== NULL
) {
499 DEBUG ((EFI_D_ERROR
, "No context to return to PEI Phase\n"));
503 SmmS3ResumeState
= mSmmS3ResumeState
;
504 ASSERT (SmmS3ResumeState
!= NULL
);
506 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_64
) {
508 // Save the IA32 IDT Descriptor
510 AsmReadIdtr ((IA32_DESCRIPTOR
*) &Ia32Idtr
);
513 // Setup X64 IDT table
515 ZeroMem (IdtEntryTable
, sizeof (IA32_IDT_GATE_DESCRIPTOR
) * 32);
516 X64Idtr
.Base
= (UINTN
) IdtEntryTable
;
517 X64Idtr
.Limit
= (UINT16
) (sizeof (IA32_IDT_GATE_DESCRIPTOR
) * 32 - 1);
518 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &X64Idtr
);
521 // Setup the default exception handler
523 Status
= InitializeCpuExceptionHandlers (NULL
);
524 ASSERT_EFI_ERROR (Status
);
527 // Initialize Debug Agent to support source level debug
529 InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64
, (VOID
*)&Ia32Idtr
, NULL
);
533 // Do below CPU things for native platform only
535 if (!FeaturePcdGet(PcdFrameworkCompatibilitySupport
)) {
537 // Skip initialization if mAcpiCpuData is not valid
539 if (mAcpiCpuData
.NumberOfCpus
> 0) {
541 // First time microcode load and restore MTRRs
543 EarlyInitializeCpu ();
548 // Restore SMBASE for BSP and all APs
553 // Do below CPU things for native platform only
555 if (!FeaturePcdGet(PcdFrameworkCompatibilitySupport
)) {
557 // Skip initialization if mAcpiCpuData is not valid
559 if (mAcpiCpuData
.NumberOfCpus
> 0) {
561 // Restore MSRs for BSP and all APs
568 // Set a flag to restore SMM configuration in S3 path.
570 mRestoreSmmConfigurationInS3
= TRUE
;
572 DEBUG (( EFI_D_INFO
, "SMM S3 Return CS = %x\n", SmmS3ResumeState
->ReturnCs
));
573 DEBUG (( EFI_D_INFO
, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState
->ReturnEntryPoint
));
574 DEBUG (( EFI_D_INFO
, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState
->ReturnContext1
));
575 DEBUG (( EFI_D_INFO
, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState
->ReturnContext2
));
576 DEBUG (( EFI_D_INFO
, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState
->ReturnStackPointer
));
579 // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
581 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_32
) {
582 DEBUG ((EFI_D_INFO
, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
585 (SWITCH_STACK_ENTRY_POINT
)(UINTN
)SmmS3ResumeState
->ReturnEntryPoint
,
586 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnContext1
,
587 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnContext2
,
588 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnStackPointer
593 // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
595 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_64
) {
596 DEBUG ((EFI_D_INFO
, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
598 // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
600 SaveAndSetDebugTimerInterrupt (FALSE
);
602 // Restore IA32 IDT table
604 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &Ia32Idtr
);
606 SmmS3ResumeState
->ReturnCs
,
607 (UINT32
)SmmS3ResumeState
->ReturnEntryPoint
,
608 (UINT32
)SmmS3ResumeState
->ReturnContext1
,
609 (UINT32
)SmmS3ResumeState
->ReturnContext2
,
610 (UINT32
)SmmS3ResumeState
->ReturnStackPointer
615 // Can not resume PEI Phase
617 DEBUG ((EFI_D_ERROR
, "No context to return to PEI Phase\n"));
622 Copy register table from ACPI NVS memory into SMRAM.
624 @param[in] DestinationRegisterTableList Points to destination register table.
625 @param[in] SourceRegisterTableList Points to source register table.
626 @param[in] NumberOfCpus Number of CPUs.
631 IN CPU_REGISTER_TABLE
*DestinationRegisterTableList
,
632 IN CPU_REGISTER_TABLE
*SourceRegisterTableList
,
633 IN UINT32 NumberOfCpus
638 CPU_REGISTER_TABLE_ENTRY
*RegisterTableEntry
;
640 CopyMem (DestinationRegisterTableList
, SourceRegisterTableList
, NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
641 for (Index
= 0; Index
< NumberOfCpus
; Index
++) {
642 DestinationRegisterTableList
[Index
].RegisterTableEntry
= AllocatePool (DestinationRegisterTableList
[Index
].AllocatedSize
);
643 ASSERT (DestinationRegisterTableList
[Index
].RegisterTableEntry
!= NULL
);
644 CopyMem (DestinationRegisterTableList
[Index
].RegisterTableEntry
, SourceRegisterTableList
[Index
].RegisterTableEntry
, DestinationRegisterTableList
[Index
].AllocatedSize
);
646 // Go though all MSRs in register table to initialize MSR spin lock
648 RegisterTableEntry
= DestinationRegisterTableList
[Index
].RegisterTableEntry
;
649 for (Index1
= 0; Index1
< DestinationRegisterTableList
[Index
].TableLength
; Index1
++, RegisterTableEntry
++) {
650 if ((RegisterTableEntry
->RegisterType
== Msr
) && (RegisterTableEntry
->ValidBitLength
< 64)) {
652 // Initialize MSR spin lock only for those MSRs need bit field writing
654 InitMsrSpinLockByIndex (RegisterTableEntry
->Index
);
661 SMM Ready To Lock event notification handler.
663 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
664 perform additional lock actions that must be performed from SMM on the next SMI.
666 @param[in] Protocol Points to the protocol's unique identifier.
667 @param[in] Interface Points to the interface instance.
668 @param[in] Handle The handle on which the interface was installed.
670 @retval EFI_SUCCESS Notification handler runs successfully.
674 SmmReadyToLockEventNotify (
675 IN CONST EFI_GUID
*Protocol
,
680 ACPI_CPU_DATA
*AcpiCpuData
;
681 IA32_DESCRIPTOR
*Gdtr
;
682 IA32_DESCRIPTOR
*Idtr
;
685 // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0
687 mAcpiCpuData
.NumberOfCpus
= 0;
690 // If FrameworkCompatibilitySspport is enabled, then do not copy CPU S3 Data into SMRAM
692 if (FeaturePcdGet (PcdFrameworkCompatibilitySupport
)) {
697 // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM
699 AcpiCpuData
= (ACPI_CPU_DATA
*)(UINTN
)PcdGet64 (PcdCpuS3DataAddress
);
700 if (AcpiCpuData
== 0) {
705 // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.
707 CopyMem (&mAcpiCpuData
, AcpiCpuData
, sizeof (mAcpiCpuData
));
709 mAcpiCpuData
.MtrrTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (MTRR_SETTINGS
));
710 ASSERT (mAcpiCpuData
.MtrrTable
!= 0);
712 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.MtrrTable
, (VOID
*)(UINTN
)AcpiCpuData
->MtrrTable
, sizeof (MTRR_SETTINGS
));
714 mAcpiCpuData
.GdtrProfile
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (IA32_DESCRIPTOR
));
715 ASSERT (mAcpiCpuData
.GdtrProfile
!= 0);
717 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.GdtrProfile
, (VOID
*)(UINTN
)AcpiCpuData
->GdtrProfile
, sizeof (IA32_DESCRIPTOR
));
719 mAcpiCpuData
.IdtrProfile
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (IA32_DESCRIPTOR
));
720 ASSERT (mAcpiCpuData
.IdtrProfile
!= 0);
722 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.IdtrProfile
, (VOID
*)(UINTN
)AcpiCpuData
->IdtrProfile
, sizeof (IA32_DESCRIPTOR
));
724 mAcpiCpuData
.PreSmmInitRegisterTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (mAcpiCpuData
.NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
725 ASSERT (mAcpiCpuData
.PreSmmInitRegisterTable
!= 0);
728 (CPU_REGISTER_TABLE
*)(UINTN
)mAcpiCpuData
.PreSmmInitRegisterTable
,
729 (CPU_REGISTER_TABLE
*)(UINTN
)AcpiCpuData
->PreSmmInitRegisterTable
,
730 mAcpiCpuData
.NumberOfCpus
733 mAcpiCpuData
.RegisterTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (mAcpiCpuData
.NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
734 ASSERT (mAcpiCpuData
.RegisterTable
!= 0);
737 (CPU_REGISTER_TABLE
*)(UINTN
)mAcpiCpuData
.RegisterTable
,
738 (CPU_REGISTER_TABLE
*)(UINTN
)AcpiCpuData
->RegisterTable
,
739 mAcpiCpuData
.NumberOfCpus
743 // Copy AP's GDT, IDT and Machine Check handler into SMRAM.
745 Gdtr
= (IA32_DESCRIPTOR
*)(UINTN
)mAcpiCpuData
.GdtrProfile
;
746 Idtr
= (IA32_DESCRIPTOR
*)(UINTN
)mAcpiCpuData
.IdtrProfile
;
748 mGdtForAp
= AllocatePool ((Gdtr
->Limit
+ 1) + (Idtr
->Limit
+ 1) + mAcpiCpuData
.ApMachineCheckHandlerSize
);
749 ASSERT (mGdtForAp
!= NULL
);
750 mIdtForAp
= (VOID
*) ((UINTN
)mGdtForAp
+ (Gdtr
->Limit
+ 1));
751 mMachineCheckHandlerForAp
= (VOID
*) ((UINTN
)mIdtForAp
+ (Idtr
->Limit
+ 1));
753 CopyMem (mGdtForAp
, (VOID
*)Gdtr
->Base
, Gdtr
->Limit
+ 1);
754 CopyMem (mIdtForAp
, (VOID
*)Idtr
->Base
, Idtr
->Limit
+ 1);
755 CopyMem (mMachineCheckHandlerForAp
, (VOID
*)(UINTN
)mAcpiCpuData
.ApMachineCheckHandlerBase
, mAcpiCpuData
.ApMachineCheckHandlerSize
);
759 // Set SMM ready to lock flag and return
761 mSmmReadyToLock
= TRUE
;
766 The module Entry Point of the CPU SMM driver.
768 @param ImageHandle The firmware allocated handle for the EFI image.
769 @param SystemTable A pointer to the EFI System Table.
771 @retval EFI_SUCCESS The entry point is executed successfully.
772 @retval Other Some error occurs when executing this entry point.
778 IN EFI_HANDLE ImageHandle
,
779 IN EFI_SYSTEM_TABLE
*SystemTable
783 EFI_MP_SERVICES_PROTOCOL
*MpServices
;
784 UINTN NumberOfEnabledProcessors
;
789 EFI_SMRAM_DESCRIPTOR
*SmramDescriptor
;
790 SMM_S3_RESUME_STATE
*SmmS3ResumeState
;
800 // Initialize Debug Agent to support source level debug in SMM code
802 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM
, NULL
, NULL
);
805 // Report the start of CPU SMM initialization.
809 EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_INIT
813 // Fix segment address of the long-mode-switch jump
815 if (sizeof (UINTN
) == sizeof (UINT64
)) {
816 gSmmJmpAddr
.Segment
= LONG_MODE_CODE_SEGMENT
;
820 // Find out SMRR Base and SMRR Size
822 FindSmramInfo (&mCpuHotPlugData
.SmrrBase
, &mCpuHotPlugData
.SmrrSize
);
825 // Get MP Services Protocol
827 Status
= SystemTable
->BootServices
->LocateProtocol (&gEfiMpServiceProtocolGuid
, NULL
, (VOID
**)&MpServices
);
828 ASSERT_EFI_ERROR (Status
);
831 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
833 Status
= MpServices
->GetNumberOfProcessors (MpServices
, &mNumberOfCpus
, &NumberOfEnabledProcessors
);
834 ASSERT_EFI_ERROR (Status
);
835 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
838 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
839 // A constant BSP index makes no sense because it may be hot removed.
842 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
844 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection
));
849 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
851 mSmmCodeAccessCheckEnable
= PcdGetBool (PcdCpuSmmCodeAccessCheckEnable
);
852 DEBUG ((EFI_D_INFO
, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable
));
855 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
857 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
858 mMaxNumberOfCpus
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
860 mMaxNumberOfCpus
= mNumberOfCpus
;
862 gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
= mMaxNumberOfCpus
;
865 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
866 // allocated buffer. The minimum size of this buffer for a uniprocessor system
867 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
868 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
869 // then the SMI entry point and the CPU save state areas can be tiles to minimize
870 // the total amount SMRAM required for all the CPUs. The tile size can be computed
871 // by adding the // CPU save state size, any extra CPU specific context, and
872 // the size of code that must be placed at the SMI entry point to transfer
873 // control to a C function in the native SMM execution mode. This size is
874 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
875 // The total amount of memory required is the maximum number of CPUs that
876 // platform supports times the tile size. The picture below shows the tiling,
877 // where m is the number of tiles that fit in 32KB.
879 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
880 // | CPU m+1 Save State |
881 // +-----------------------------+
882 // | CPU m+1 Extra Data |
883 // +-----------------------------+
885 // +-----------------------------+
886 // | CPU 2m SMI Entry |
887 // +#############################+ <-- Base of allocated buffer + 64 KB
888 // | CPU m-1 Save State |
889 // +-----------------------------+
890 // | CPU m-1 Extra Data |
891 // +-----------------------------+
893 // +-----------------------------+
894 // | CPU 2m-1 SMI Entry |
895 // +=============================+ <-- 2^n offset from Base of allocated buffer
896 // | . . . . . . . . . . . . |
897 // +=============================+ <-- 2^n offset from Base of allocated buffer
898 // | CPU 2 Save State |
899 // +-----------------------------+
900 // | CPU 2 Extra Data |
901 // +-----------------------------+
903 // +-----------------------------+
904 // | CPU m+1 SMI Entry |
905 // +=============================+ <-- Base of allocated buffer + 32 KB
906 // | CPU 1 Save State |
907 // +-----------------------------+
908 // | CPU 1 Extra Data |
909 // +-----------------------------+
911 // +-----------------------------+
912 // | CPU m SMI Entry |
913 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
914 // | CPU 0 Save State |
915 // +-----------------------------+
916 // | CPU 0 Extra Data |
917 // +-----------------------------+
919 // +-----------------------------+
920 // | CPU m-1 SMI Entry |
921 // +=============================+ <-- 2^n offset from Base of allocated buffer
922 // | . . . . . . . . . . . . |
923 // +=============================+ <-- 2^n offset from Base of allocated buffer
925 // +-----------------------------+
926 // | CPU 1 SMI Entry |
927 // +=============================+ <-- 2^n offset from Base of allocated buffer
929 // +-----------------------------+
930 // | CPU 0 SMI Entry |
931 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
935 // Retrieve CPU Family
937 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, &RegEdx
);
938 FamilyId
= (RegEax
>> 8) & 0xf;
939 ModelId
= (RegEax
>> 4) & 0xf;
940 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
941 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
945 // Determine the mode of the CPU at the time an SMI occurs
946 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
947 // Volume 3C, Section 34.4.1.1
949 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
;
950 if ((RegEdx
& BIT29
) != 0) {
951 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
953 if (FamilyId
== 0x06) {
954 if (ModelId
== 0x17 || ModelId
== 0x0f || ModelId
== 0x1c) {
955 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
960 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
961 // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size
962 // is rounded up to nearest power of 2.
964 TileSize
= sizeof (SMRAM_SAVE_STATE_MAP
) + sizeof (PROCESSOR_SMM_DESCRIPTOR
) + GetSmiHandlerSize () - 1;
965 TileSize
= 2 * GetPowerOfTwo32 ((UINT32
)TileSize
);
966 DEBUG ((EFI_D_INFO
, "SMRAM TileSize = %08x\n", TileSize
));
969 // If the TileSize is larger than space available for the SMI Handler of CPU[i],
970 // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],
971 // the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be
974 ASSERT (TileSize
<= (SMRAM_SAVE_STATE_MAP_OFFSET
+ sizeof (SMRAM_SAVE_STATE_MAP
) - SMM_HANDLER_OFFSET
));
977 // Allocate buffer for all of the tiles.
979 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
980 // Volume 3C, Section 34.11 SMBASE Relocation
981 // For Pentium and Intel486 processors, the SMBASE values must be
982 // aligned on a 32-KByte boundary or the processor will enter shutdown
983 // state during the execution of a RSM instruction.
985 // Intel486 processors: FamilyId is 4
986 // Pentium processors : FamilyId is 5
988 if ((FamilyId
== 4) || (FamilyId
== 5)) {
989 Buffer
= AllocateAlignedPages (EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1)), SIZE_32KB
);
991 Buffer
= AllocatePages (EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1)));
993 ASSERT (Buffer
!= NULL
);
996 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
998 gSmmCpuPrivate
->ProcessorInfo
= (EFI_PROCESSOR_INFORMATION
*)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION
) * mMaxNumberOfCpus
);
999 ASSERT (gSmmCpuPrivate
->ProcessorInfo
!= NULL
);
1001 gSmmCpuPrivate
->Operation
= (SMM_CPU_OPERATION
*)AllocatePool (sizeof (SMM_CPU_OPERATION
) * mMaxNumberOfCpus
);
1002 ASSERT (gSmmCpuPrivate
->Operation
!= NULL
);
1004 gSmmCpuPrivate
->CpuSaveStateSize
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
1005 ASSERT (gSmmCpuPrivate
->CpuSaveStateSize
!= NULL
);
1007 gSmmCpuPrivate
->CpuSaveState
= (VOID
**)AllocatePool (sizeof (VOID
*) * mMaxNumberOfCpus
);
1008 ASSERT (gSmmCpuPrivate
->CpuSaveState
!= NULL
);
1010 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveStateSize
= gSmmCpuPrivate
->CpuSaveStateSize
;
1011 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveState
= gSmmCpuPrivate
->CpuSaveState
;
1012 mSmmCpuSaveState
.CpuSaveState
= (EFI_SMM_CPU_STATE
**)gSmmCpuPrivate
->CpuSaveState
;
1015 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
1017 mCpuHotPlugData
.ApicId
= (UINT64
*)AllocatePool (sizeof (UINT64
) * mMaxNumberOfCpus
);
1018 ASSERT (mCpuHotPlugData
.ApicId
!= NULL
);
1019 mCpuHotPlugData
.SmBase
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
1020 ASSERT (mCpuHotPlugData
.SmBase
!= NULL
);
1021 mCpuHotPlugData
.ArrayLength
= (UINT32
)mMaxNumberOfCpus
;
1024 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
1025 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
1026 // size for each CPU in the platform
1028 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
1029 mCpuHotPlugData
.SmBase
[Index
] = (UINTN
)Buffer
+ Index
* TileSize
- SMM_HANDLER_OFFSET
;
1030 gSmmCpuPrivate
->CpuSaveStateSize
[Index
] = sizeof(SMRAM_SAVE_STATE_MAP
);
1031 gSmmCpuPrivate
->CpuSaveState
[Index
] = (VOID
*)(mCpuHotPlugData
.SmBase
[Index
] + SMRAM_SAVE_STATE_MAP_OFFSET
);
1032 gSmmCpuPrivate
->Operation
[Index
] = SmmCpuNone
;
1034 if (Index
< mNumberOfCpus
) {
1035 Status
= MpServices
->GetProcessorInfo (MpServices
, Index
, &gSmmCpuPrivate
->ProcessorInfo
[Index
]);
1036 ASSERT_EFI_ERROR (Status
);
1037 mCpuHotPlugData
.ApicId
[Index
] = gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
;
1039 DEBUG ((EFI_D_INFO
, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
1041 (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
,
1042 mCpuHotPlugData
.SmBase
[Index
],
1043 gSmmCpuPrivate
->CpuSaveState
[Index
],
1044 gSmmCpuPrivate
->CpuSaveStateSize
[Index
]
1047 gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
= INVALID_APIC_ID
;
1048 mCpuHotPlugData
.ApicId
[Index
] = INVALID_APIC_ID
;
1053 // Allocate SMI stacks for all processors.
1055 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
1057 // 2 more pages is allocated for each processor.
1058 // one is guard page and the other is known good stack.
1060 // +-------------------------------------------+-----+-------------------------------------------+
1061 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
1062 // +-------------------------------------------+-----+-------------------------------------------+
1064 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
1066 mSmmStackSize
= EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2);
1067 Stacks
= (UINT8
*) AllocatePages (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2));
1068 ASSERT (Stacks
!= NULL
);
1069 mSmmStackArrayBase
= (UINTN
)Stacks
;
1070 mSmmStackArrayEnd
= mSmmStackArrayBase
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
- 1;
1072 mSmmStackSize
= PcdGet32 (PcdCpuSmmStackSize
);
1073 Stacks
= (UINT8
*) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
));
1074 ASSERT (Stacks
!= NULL
);
1078 // Set SMI stack for SMM base relocation
1080 gSmmInitStack
= (UINTN
) (Stacks
+ mSmmStackSize
- sizeof (UINTN
));
1085 InitializeSmmIdt ();
1088 // Relocate SMM Base addresses to the ones allocated from SMRAM
1090 mRebased
= (BOOLEAN
*)AllocateZeroPool (sizeof (BOOLEAN
) * mMaxNumberOfCpus
);
1091 ASSERT (mRebased
!= NULL
);
1092 SmmRelocateBases ();
1095 // Call hook for BSP to perform extra actions in normal mode after all
1096 // SMM base addresses have been relocated on all CPUs
1098 SmmCpuFeaturesSmmRelocationComplete ();
1101 // SMM Time initialization
1103 InitializeSmmTimer ();
1106 // Initialize MP globals
1108 Cr3
= InitializeMpServiceData (Stacks
, mSmmStackSize
);
1111 // Fill in SMM Reserved Regions
1113 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedStart
= 0;
1114 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedSize
= 0;
1117 // Install the SMM Configuration Protocol onto a new handle on the handle database.
1118 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
1119 // to an SMRAM address will be present in the handle database
1121 Status
= SystemTable
->BootServices
->InstallMultipleProtocolInterfaces (
1122 &gSmmCpuPrivate
->SmmCpuHandle
,
1123 &gEfiSmmConfigurationProtocolGuid
, &gSmmCpuPrivate
->SmmConfiguration
,
1126 ASSERT_EFI_ERROR (Status
);
1129 // Install the SMM CPU Protocol into SMM protocol database
1131 Status
= gSmst
->SmmInstallProtocolInterface (
1133 &gEfiSmmCpuProtocolGuid
,
1134 EFI_NATIVE_INTERFACE
,
1137 ASSERT_EFI_ERROR (Status
);
1140 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
1142 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
1143 Status
= PcdSet64S (PcdCpuHotPlugDataAddress
, (UINT64
)(UINTN
)&mCpuHotPlugData
);
1144 ASSERT_EFI_ERROR (Status
);
1148 // Initialize SMM CPU Services Support
1150 Status
= InitializeSmmCpuServices (mSmmCpuHandle
);
1151 ASSERT_EFI_ERROR (Status
);
1153 if (FeaturePcdGet (PcdFrameworkCompatibilitySupport
)) {
1155 // Install Framework SMM Save State Protocol into UEFI protocol database for backward compatibility
1157 Status
= SystemTable
->BootServices
->InstallMultipleProtocolInterfaces (
1158 &gSmmCpuPrivate
->SmmCpuHandle
,
1159 &gEfiSmmCpuSaveStateProtocolGuid
,
1163 ASSERT_EFI_ERROR (Status
);
1165 // The SmmStartupThisAp service in Framework SMST should always be non-null.
1166 // Update SmmStartupThisAp pointer in PI SMST here so that PI/Framework SMM thunk
1167 // can have it ready when constructing Framework SMST.
1169 gSmst
->SmmStartupThisAp
= SmmStartupThisAp
;
1173 // register SMM Ready To Lock Protocol notification
1175 Status
= gSmst
->SmmRegisterProtocolNotify (
1176 &gEfiSmmReadyToLockProtocolGuid
,
1177 SmmReadyToLockEventNotify
,
1180 ASSERT_EFI_ERROR (Status
);
1182 GuidHob
= GetFirstGuidHob (&gEfiAcpiVariableGuid
);
1183 if (GuidHob
!= NULL
) {
1184 SmramDescriptor
= (EFI_SMRAM_DESCRIPTOR
*) GET_GUID_HOB_DATA (GuidHob
);
1186 DEBUG ((EFI_D_INFO
, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor
));
1187 DEBUG ((EFI_D_INFO
, "SMM S3 Structure = %x\n", SmramDescriptor
->CpuStart
));
1189 SmmS3ResumeState
= (SMM_S3_RESUME_STATE
*)(UINTN
)SmramDescriptor
->CpuStart
;
1190 ZeroMem (SmmS3ResumeState
, sizeof (SMM_S3_RESUME_STATE
));
1192 mSmmS3ResumeState
= SmmS3ResumeState
;
1193 SmmS3ResumeState
->Smst
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)gSmst
;
1195 SmmS3ResumeState
->SmmS3ResumeEntryPoint
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)SmmRestoreCpu
;
1197 SmmS3ResumeState
->SmmS3StackSize
= SIZE_32KB
;
1198 SmmS3ResumeState
->SmmS3StackBase
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN
)SmmS3ResumeState
->SmmS3StackSize
));
1199 if (SmmS3ResumeState
->SmmS3StackBase
== 0) {
1200 SmmS3ResumeState
->SmmS3StackSize
= 0;
1203 SmmS3ResumeState
->SmmS3Cr0
= gSmmCr0
;
1204 SmmS3ResumeState
->SmmS3Cr3
= Cr3
;
1205 SmmS3ResumeState
->SmmS3Cr4
= gSmmCr4
;
1207 if (sizeof (UINTN
) == sizeof (UINT64
)) {
1208 SmmS3ResumeState
->Signature
= SMM_S3_RESUME_SMM_64
;
1210 if (sizeof (UINTN
) == sizeof (UINT32
)) {
1211 SmmS3ResumeState
->Signature
= SMM_S3_RESUME_SMM_32
;
1216 // Check XD and BTS features
1218 CheckProcessorFeature ();
1221 // Initialize SMM Profile feature
1223 InitSmmProfile (Cr3
);
1226 // Patch SmmS3ResumeState->SmmS3Cr3
1230 DEBUG ((EFI_D_INFO
, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
1237 Find out SMRAM information including SMRR base and SMRR size.
1239 @param SmrrBase SMRR base
1240 @param SmrrSize SMRR size
1245 OUT UINT32
*SmrrBase
,
1246 OUT UINT32
*SmrrSize
1251 EFI_SMM_ACCESS2_PROTOCOL
*SmmAccess
;
1252 EFI_SMRAM_DESCRIPTOR
*CurrentSmramRange
;
1253 EFI_SMRAM_DESCRIPTOR
*SmramRanges
;
1254 UINTN SmramRangeCount
;
1260 // Get SMM Access Protocol
1262 Status
= gBS
->LocateProtocol (&gEfiSmmAccess2ProtocolGuid
, NULL
, (VOID
**)&SmmAccess
);
1263 ASSERT_EFI_ERROR (Status
);
1266 // Get SMRAM information
1269 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, NULL
);
1270 ASSERT (Status
== EFI_BUFFER_TOO_SMALL
);
1272 SmramRanges
= (EFI_SMRAM_DESCRIPTOR
*)AllocatePool (Size
);
1273 ASSERT (SmramRanges
!= NULL
);
1275 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, SmramRanges
);
1276 ASSERT_EFI_ERROR (Status
);
1278 SmramRangeCount
= Size
/ sizeof (EFI_SMRAM_DESCRIPTOR
);
1281 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
1283 CurrentSmramRange
= NULL
;
1284 for (Index
= 0, MaxSize
= SIZE_256KB
- EFI_PAGE_SIZE
; Index
< SmramRangeCount
; Index
++) {
1286 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
1288 if ((SmramRanges
[Index
].RegionState
& (EFI_ALLOCATED
| EFI_NEEDS_TESTING
| EFI_NEEDS_ECC_INITIALIZATION
)) != 0) {
1292 if (SmramRanges
[Index
].CpuStart
>= BASE_1MB
) {
1293 if ((SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
) <= BASE_4GB
) {
1294 if (SmramRanges
[Index
].PhysicalSize
>= MaxSize
) {
1295 MaxSize
= SmramRanges
[Index
].PhysicalSize
;
1296 CurrentSmramRange
= &SmramRanges
[Index
];
1302 ASSERT (CurrentSmramRange
!= NULL
);
1304 *SmrrBase
= (UINT32
)CurrentSmramRange
->CpuStart
;
1305 *SmrrSize
= (UINT32
)CurrentSmramRange
->PhysicalSize
;
1309 for (Index
= 0; Index
< SmramRangeCount
; Index
++) {
1310 if (SmramRanges
[Index
].CpuStart
< *SmrrBase
&& *SmrrBase
== (SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
)) {
1311 *SmrrBase
= (UINT32
)SmramRanges
[Index
].CpuStart
;
1312 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1314 } else if ((*SmrrBase
+ *SmrrSize
) == SmramRanges
[Index
].CpuStart
&& SmramRanges
[Index
].PhysicalSize
> 0) {
1315 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1321 DEBUG ((EFI_D_INFO
, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase
, *SmrrSize
));
1325 Configure SMM Code Access Check feature on an AP.
1326 SMM Feature Control MSR will be locked after configuration.
1328 @param[in,out] Buffer Pointer to private data buffer.
1332 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1337 UINT64 SmmFeatureControlMsr
;
1338 UINT64 NewSmmFeatureControlMsr
;
1341 // Retrieve the CPU Index from the context passed in
1343 CpuIndex
= *(UINTN
*)Buffer
;
1346 // Get the current SMM Feature Control MSR value
1348 SmmFeatureControlMsr
= SmmCpuFeaturesGetSmmRegister (CpuIndex
, SmmRegFeatureControl
);
1351 // Compute the new SMM Feature Control MSR value
1353 NewSmmFeatureControlMsr
= SmmFeatureControlMsr
;
1354 if (mSmmCodeAccessCheckEnable
) {
1355 NewSmmFeatureControlMsr
|= SMM_CODE_CHK_EN_BIT
;
1357 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1358 NewSmmFeatureControlMsr
|= SMM_FEATURE_CONTROL_LOCK_BIT
;
1362 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1364 if (NewSmmFeatureControlMsr
!= SmmFeatureControlMsr
) {
1365 SmmCpuFeaturesSetSmmRegister (CpuIndex
, SmmRegFeatureControl
, NewSmmFeatureControlMsr
);
1369 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1371 ReleaseSpinLock (&mConfigSmmCodeAccessCheckLock
);
1375 Configure SMM Code Access Check feature for all processors.
1376 SMM Feature Control MSR will be locked after configuration.
1379 ConfigSmmCodeAccessCheck (
1387 // Check to see if the Feature Control MSR is supported on this CPU
1389 Index
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1390 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index
, SmmRegFeatureControl
)) {
1391 mSmmCodeAccessCheckEnable
= FALSE
;
1396 // Check to see if the CPU supports the SMM Code Access Check feature
1397 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1399 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP
) & SMM_CODE_ACCESS_CHK_BIT
) == 0) {
1400 mSmmCodeAccessCheckEnable
= FALSE
;
1404 // If the SMM Code Access Check feature is disabled and the Feature Control MSR
1405 // is not being locked, then no additional work is required
1407 if (!mSmmCodeAccessCheckEnable
&& !FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1412 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1414 InitializeSpinLock (&mConfigSmmCodeAccessCheckLock
);
1417 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1418 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1420 AcquireSpinLock (&mConfigSmmCodeAccessCheckLock
);
1423 // Enable SMM Code Access Check feature on the BSP.
1425 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index
);
1428 // Enable SMM Code Access Check feature for the APs.
1430 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1431 if (Index
!= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
) {
1434 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1435 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1437 AcquireSpinLock (&mConfigSmmCodeAccessCheckLock
);
1440 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1442 Status
= gSmst
->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor
, Index
, &Index
);
1443 ASSERT_EFI_ERROR (Status
);
1446 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1448 while (!AcquireSpinLockOrFail (&mConfigSmmCodeAccessCheckLock
)) {
1453 // Release the Config SMM Code Access Check spin lock.
1455 ReleaseSpinLock (&mConfigSmmCodeAccessCheckLock
);
1461 Perform the remaining tasks.
1465 PerformRemainingTasks (
1469 if (mSmmReadyToLock
) {
1471 // Start SMM Profile feature
1473 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1477 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1481 // Configure SMM Code Access Check feature if available.
1483 ConfigSmmCodeAccessCheck ();
1486 // Clean SMM ready to lock flag
1488 mSmmReadyToLock
= FALSE
;