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[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c
1 /** @file
2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
3
4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PiSmmCpuDxeSmm.h"
16
17 //
18 // SMM CPU Private Data structure that contains SMM Configuration Protocol
19 // along its supporting fields.
20 //
21 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = {
22 SMM_CPU_PRIVATE_DATA_SIGNATURE, // Signature
23 NULL, // SmmCpuHandle
24 NULL, // Pointer to ProcessorInfo array
25 NULL, // Pointer to Operation array
26 NULL, // Pointer to CpuSaveStateSize array
27 NULL, // Pointer to CpuSaveState array
28 { {0} }, // SmmReservedSmramRegion
29 {
30 SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp
31 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
32 0, // SmmCoreEntryContext.NumberOfCpus
33 NULL, // SmmCoreEntryContext.CpuSaveStateSize
34 NULL // SmmCoreEntryContext.CpuSaveState
35 },
36 NULL, // SmmCoreEntry
37 {
38 mSmmCpuPrivateData.SmmReservedSmramRegion, // SmmConfiguration.SmramReservedRegions
39 RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry
40 },
41 };
42
43 CPU_HOT_PLUG_DATA mCpuHotPlugData = {
44 CPU_HOT_PLUG_DATA_REVISION_1, // Revision
45 0, // Array Length of SmBase and APIC ID
46 NULL, // Pointer to APIC ID array
47 NULL, // Pointer to SMBASE array
48 0, // Reserved
49 0, // SmrrBase
50 0 // SmrrSize
51 };
52
53 //
54 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
55 //
56 SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate = &mSmmCpuPrivateData;
57
58 //
59 // SMM Relocation variables
60 //
61 volatile BOOLEAN *mRebased;
62 volatile BOOLEAN mIsBsp;
63
64 ///
65 /// Handle for the SMM CPU Protocol
66 ///
67 EFI_HANDLE mSmmCpuHandle = NULL;
68
69 ///
70 /// SMM CPU Protocol instance
71 ///
72 EFI_SMM_CPU_PROTOCOL mSmmCpu = {
73 SmmReadSaveState,
74 SmmWriteSaveState
75 };
76
77 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];
78
79 //
80 // SMM stack information
81 //
82 UINTN mSmmStackArrayBase;
83 UINTN mSmmStackArrayEnd;
84 UINTN mSmmStackSize;
85
86 //
87 // Pointer to structure used during S3 Resume
88 //
89 SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL;
90
91 UINTN mMaxNumberOfCpus = 1;
92 UINTN mNumberOfCpus = 1;
93
94 //
95 // SMM ready to lock flag
96 //
97 BOOLEAN mSmmReadyToLock = FALSE;
98
99 //
100 // S3 boot flag
101 //
102 BOOLEAN mSmmS3Flag = FALSE;
103
104 //
105 // Global used to cache PCD for SMM Code Access Check enable
106 //
107 BOOLEAN mSmmCodeAccessCheckEnable = FALSE;
108
109 //
110 // Spin lock used to serialize setting of SMM Code Access Check feature
111 //
112 SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;
113
114 /**
115 Initialize IDT to setup exception handlers for SMM.
116
117 **/
118 VOID
119 InitializeSmmIdt (
120 VOID
121 )
122 {
123 EFI_STATUS Status;
124 BOOLEAN InterruptState;
125 IA32_DESCRIPTOR DxeIdtr;
126 //
127 // Disable Interrupt and save DXE IDT table
128 //
129 InterruptState = SaveAndDisableInterrupts ();
130 AsmReadIdtr (&DxeIdtr);
131 //
132 // Load SMM temporary IDT table
133 //
134 AsmWriteIdtr (&gcSmiIdtr);
135 //
136 // Setup SMM default exception handlers, SMM IDT table
137 // will be updated and saved in gcSmiIdtr
138 //
139 Status = InitializeCpuExceptionHandlers (NULL);
140 ASSERT_EFI_ERROR (Status);
141 //
142 // Restore DXE IDT table and CPU interrupt
143 //
144 AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr);
145 SetInterruptState (InterruptState);
146 }
147
148 /**
149 Search module name by input IP address and output it.
150
151 @param CallerIpAddress Caller instruction pointer.
152
153 **/
154 VOID
155 DumpModuleInfoByIp (
156 IN UINTN CallerIpAddress
157 )
158 {
159 UINTN Pe32Data;
160 EFI_IMAGE_DOS_HEADER *DosHdr;
161 EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
162 VOID *PdbPointer;
163 UINT64 DumpIpAddress;
164
165 //
166 // Find Image Base
167 //
168 Pe32Data = CallerIpAddress & ~(SIZE_4KB - 1);
169 while (Pe32Data != 0) {
170 DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
171 if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
172 //
173 // DOS image header is present, so read the PE header after the DOS image header.
174 //
175 Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));
176 //
177 // Make sure PE header address does not overflow and is less than the initial address.
178 //
179 if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < CallerIpAddress)) {
180 if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
181 //
182 // It's PE image.
183 //
184 break;
185 }
186 }
187 }
188
189 //
190 // Not found the image base, check the previous aligned address
191 //
192 Pe32Data -= SIZE_4KB;
193 }
194
195 DumpIpAddress = CallerIpAddress;
196 DEBUG ((EFI_D_ERROR, "It is invoked from the instruction before IP(0x%lx)", DumpIpAddress));
197
198 if (Pe32Data != 0) {
199 PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
200 if (PdbPointer != NULL) {
201 DEBUG ((EFI_D_ERROR, " in module (%a)", PdbPointer));
202 }
203 }
204 }
205
206 /**
207 Read information from the CPU save state.
208
209 @param This EFI_SMM_CPU_PROTOCOL instance
210 @param Width The number of bytes to read from the CPU save state.
211 @param Register Specifies the CPU register to read form the save state.
212 @param CpuIndex Specifies the zero-based index of the CPU save state.
213 @param Buffer Upon return, this holds the CPU register value read from the save state.
214
215 @retval EFI_SUCCESS The register was read from Save State
216 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
217 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
218
219 **/
220 EFI_STATUS
221 EFIAPI
222 SmmReadSaveState (
223 IN CONST EFI_SMM_CPU_PROTOCOL *This,
224 IN UINTN Width,
225 IN EFI_SMM_SAVE_STATE_REGISTER Register,
226 IN UINTN CpuIndex,
227 OUT VOID *Buffer
228 )
229 {
230 EFI_STATUS Status;
231
232 //
233 // Retrieve pointer to the specified CPU's SMM Save State buffer
234 //
235 if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
236 return EFI_INVALID_PARAMETER;
237 }
238
239 //
240 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
241 //
242 if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {
243 //
244 // The pseudo-register only supports the 64-bit size specified by Width.
245 //
246 if (Width != sizeof (UINT64)) {
247 return EFI_INVALID_PARAMETER;
248 }
249 //
250 // If the processor is in SMM at the time the SMI occurred,
251 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
252 // Otherwise, EFI_NOT_FOUND is returned.
253 //
254 if (*(mSmmMpSyncData->CpuData[CpuIndex].Present)) {
255 *(UINT64 *)Buffer = gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId;
256 return EFI_SUCCESS;
257 } else {
258 return EFI_NOT_FOUND;
259 }
260 }
261
262 if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {
263 return EFI_INVALID_PARAMETER;
264 }
265
266 Status = SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
267 if (Status == EFI_UNSUPPORTED) {
268 Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
269 }
270 return Status;
271 }
272
273 /**
274 Write data to the CPU save state.
275
276 @param This EFI_SMM_CPU_PROTOCOL instance
277 @param Width The number of bytes to read from the CPU save state.
278 @param Register Specifies the CPU register to write to the save state.
279 @param CpuIndex Specifies the zero-based index of the CPU save state
280 @param Buffer Upon entry, this holds the new CPU register value.
281
282 @retval EFI_SUCCESS The register was written from Save State
283 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
284 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
285
286 **/
287 EFI_STATUS
288 EFIAPI
289 SmmWriteSaveState (
290 IN CONST EFI_SMM_CPU_PROTOCOL *This,
291 IN UINTN Width,
292 IN EFI_SMM_SAVE_STATE_REGISTER Register,
293 IN UINTN CpuIndex,
294 IN CONST VOID *Buffer
295 )
296 {
297 EFI_STATUS Status;
298
299 //
300 // Retrieve pointer to the specified CPU's SMM Save State buffer
301 //
302 if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
303 return EFI_INVALID_PARAMETER;
304 }
305
306 //
307 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
308 //
309 if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {
310 return EFI_SUCCESS;
311 }
312
313 if (!mSmmMpSyncData->CpuData[CpuIndex].Present) {
314 return EFI_INVALID_PARAMETER;
315 }
316
317 Status = SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
318 if (Status == EFI_UNSUPPORTED) {
319 Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
320 }
321 return Status;
322 }
323
324
325 /**
326 C function for SMI handler. To change all processor's SMMBase Register.
327
328 **/
329 VOID
330 EFIAPI
331 SmmInitHandler (
332 VOID
333 )
334 {
335 UINT32 ApicId;
336 UINTN Index;
337
338 //
339 // Update SMM IDT entries' code segment and load IDT
340 //
341 AsmWriteIdtr (&gcSmiIdtr);
342 ApicId = GetApicId ();
343
344 ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
345
346 for (Index = 0; Index < mNumberOfCpus; Index++) {
347 if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
348 //
349 // Initialize SMM specific features on the currently executing CPU
350 //
351 SmmCpuFeaturesInitializeProcessor (
352 Index,
353 mIsBsp,
354 gSmmCpuPrivate->ProcessorInfo,
355 &mCpuHotPlugData
356 );
357
358 if (mIsBsp) {
359 //
360 // BSP rebase is already done above.
361 // Initialize private data during S3 resume
362 //
363 InitializeMpSyncData ();
364 }
365
366 //
367 // Hook return after RSM to set SMM re-based flag
368 //
369 SemaphoreHook (Index, &mRebased[Index]);
370
371 return;
372 }
373 }
374 ASSERT (FALSE);
375 }
376
377 /**
378 Relocate SmmBases for each processor.
379
380 Execute on first boot and all S3 resumes
381
382 **/
383 VOID
384 EFIAPI
385 SmmRelocateBases (
386 VOID
387 )
388 {
389 UINT8 BakBuf[BACK_BUF_SIZE];
390 SMRAM_SAVE_STATE_MAP BakBuf2;
391 SMRAM_SAVE_STATE_MAP *CpuStatePtr;
392 UINT8 *U8Ptr;
393 UINT32 ApicId;
394 UINTN Index;
395 UINTN BspIndex;
396
397 //
398 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
399 //
400 ASSERT (sizeof (BakBuf) >= gcSmmInitSize);
401
402 //
403 // Patch ASM code template with current CR0, CR3, and CR4 values
404 //
405 gSmmCr0 = (UINT32)AsmReadCr0 ();
406 gSmmCr3 = (UINT32)AsmReadCr3 ();
407 gSmmCr4 = (UINT32)AsmReadCr4 ();
408
409 //
410 // Patch GDTR for SMM base relocation
411 //
412 gcSmiInitGdtr.Base = gcSmiGdtr.Base;
413 gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;
414
415 U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);
416 CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
417
418 //
419 // Backup original contents at address 0x38000
420 //
421 CopyMem (BakBuf, U8Ptr, sizeof (BakBuf));
422 CopyMem (&BakBuf2, CpuStatePtr, sizeof (BakBuf2));
423
424 //
425 // Load image for relocation
426 //
427 CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize);
428
429 //
430 // Retrieve the local APIC ID of current processor
431 //
432 ApicId = GetApicId ();
433
434 //
435 // Relocate SM bases for all APs
436 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
437 //
438 mIsBsp = FALSE;
439 BspIndex = (UINTN)-1;
440 for (Index = 0; Index < mNumberOfCpus; Index++) {
441 mRebased[Index] = FALSE;
442 if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
443 SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
444 //
445 // Wait for this AP to finish its 1st SMI
446 //
447 while (!mRebased[Index]);
448 } else {
449 //
450 // BSP will be Relocated later
451 //
452 BspIndex = Index;
453 }
454 }
455
456 //
457 // Relocate BSP's SMM base
458 //
459 ASSERT (BspIndex != (UINTN)-1);
460 mIsBsp = TRUE;
461 SendSmiIpi (ApicId);
462 //
463 // Wait for the BSP to finish its 1st SMI
464 //
465 while (!mRebased[BspIndex]);
466
467 //
468 // Restore contents at address 0x38000
469 //
470 CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2));
471 CopyMem (U8Ptr, BakBuf, sizeof (BakBuf));
472 }
473
474 /**
475 Perform SMM initialization for all processors in the S3 boot path.
476
477 For a native platform, MP initialization in the S3 boot path is also performed in this function.
478 **/
479 VOID
480 EFIAPI
481 SmmRestoreCpu (
482 VOID
483 )
484 {
485 SMM_S3_RESUME_STATE *SmmS3ResumeState;
486 IA32_DESCRIPTOR Ia32Idtr;
487 IA32_DESCRIPTOR X64Idtr;
488 IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
489 EFI_STATUS Status;
490
491 DEBUG ((EFI_D_INFO, "SmmRestoreCpu()\n"));
492
493 mSmmS3Flag = TRUE;
494
495 InitializeSpinLock (mMemoryMappedLock);
496
497 //
498 // See if there is enough context to resume PEI Phase
499 //
500 if (mSmmS3ResumeState == NULL) {
501 DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
502 CpuDeadLoop ();
503 }
504
505 SmmS3ResumeState = mSmmS3ResumeState;
506 ASSERT (SmmS3ResumeState != NULL);
507
508 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
509 //
510 // Save the IA32 IDT Descriptor
511 //
512 AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
513
514 //
515 // Setup X64 IDT table
516 //
517 ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);
518 X64Idtr.Base = (UINTN) IdtEntryTable;
519 X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);
520 AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);
521
522 //
523 // Setup the default exception handler
524 //
525 Status = InitializeCpuExceptionHandlers (NULL);
526 ASSERT_EFI_ERROR (Status);
527
528 //
529 // Initialize Debug Agent to support source level debug
530 //
531 InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);
532 }
533
534 //
535 // Skip initialization if mAcpiCpuData is not valid
536 //
537 if (mAcpiCpuData.NumberOfCpus > 0) {
538 //
539 // First time microcode load and restore MTRRs
540 //
541 EarlyInitializeCpu ();
542 }
543
544 //
545 // Restore SMBASE for BSP and all APs
546 //
547 SmmRelocateBases ();
548
549 //
550 // Skip initialization if mAcpiCpuData is not valid
551 //
552 if (mAcpiCpuData.NumberOfCpus > 0) {
553 //
554 // Restore MSRs for BSP and all APs
555 //
556 InitializeCpu ();
557 }
558
559 //
560 // Set a flag to restore SMM configuration in S3 path.
561 //
562 mRestoreSmmConfigurationInS3 = TRUE;
563
564 DEBUG (( EFI_D_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
565 DEBUG (( EFI_D_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
566 DEBUG (( EFI_D_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
567 DEBUG (( EFI_D_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
568 DEBUG (( EFI_D_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
569
570 //
571 // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
572 //
573 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {
574 DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
575
576 SwitchStack (
577 (SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->ReturnEntryPoint,
578 (VOID *)(UINTN)SmmS3ResumeState->ReturnContext1,
579 (VOID *)(UINTN)SmmS3ResumeState->ReturnContext2,
580 (VOID *)(UINTN)SmmS3ResumeState->ReturnStackPointer
581 );
582 }
583
584 //
585 // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
586 //
587 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
588 DEBUG ((EFI_D_INFO, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
589 //
590 // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
591 //
592 SaveAndSetDebugTimerInterrupt (FALSE);
593 //
594 // Restore IA32 IDT table
595 //
596 AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
597 AsmDisablePaging64 (
598 SmmS3ResumeState->ReturnCs,
599 (UINT32)SmmS3ResumeState->ReturnEntryPoint,
600 (UINT32)SmmS3ResumeState->ReturnContext1,
601 (UINT32)SmmS3ResumeState->ReturnContext2,
602 (UINT32)SmmS3ResumeState->ReturnStackPointer
603 );
604 }
605
606 //
607 // Can not resume PEI Phase
608 //
609 DEBUG ((EFI_D_ERROR, "No context to return to PEI Phase\n"));
610 CpuDeadLoop ();
611 }
612
613 /**
614 Copy register table from ACPI NVS memory into SMRAM.
615
616 @param[in] DestinationRegisterTableList Points to destination register table.
617 @param[in] SourceRegisterTableList Points to source register table.
618 @param[in] NumberOfCpus Number of CPUs.
619
620 **/
621 VOID
622 CopyRegisterTable (
623 IN CPU_REGISTER_TABLE *DestinationRegisterTableList,
624 IN CPU_REGISTER_TABLE *SourceRegisterTableList,
625 IN UINT32 NumberOfCpus
626 )
627 {
628 UINTN Index;
629 UINTN Index1;
630 CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
631
632 CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
633 for (Index = 0; Index < NumberOfCpus; Index++) {
634 DestinationRegisterTableList[Index].RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);
635 ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry != NULL);
636 CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry, SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);
637 //
638 // Go though all MSRs in register table to initialize MSR spin lock
639 //
640 RegisterTableEntry = DestinationRegisterTableList[Index].RegisterTableEntry;
641 for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
642 if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
643 //
644 // Initialize MSR spin lock only for those MSRs need bit field writing
645 //
646 InitMsrSpinLockByIndex (RegisterTableEntry->Index);
647 }
648 }
649 }
650 }
651
652 /**
653 SMM Ready To Lock event notification handler.
654
655 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
656 perform additional lock actions that must be performed from SMM on the next SMI.
657
658 @param[in] Protocol Points to the protocol's unique identifier.
659 @param[in] Interface Points to the interface instance.
660 @param[in] Handle The handle on which the interface was installed.
661
662 @retval EFI_SUCCESS Notification handler runs successfully.
663 **/
664 EFI_STATUS
665 EFIAPI
666 SmmReadyToLockEventNotify (
667 IN CONST EFI_GUID *Protocol,
668 IN VOID *Interface,
669 IN EFI_HANDLE Handle
670 )
671 {
672 ACPI_CPU_DATA *AcpiCpuData;
673 IA32_DESCRIPTOR *Gdtr;
674 IA32_DESCRIPTOR *Idtr;
675
676 //
677 // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0
678 //
679 mAcpiCpuData.NumberOfCpus = 0;
680
681 //
682 // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM
683 //
684 AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);
685 if (AcpiCpuData == 0) {
686 goto Done;
687 }
688
689 //
690 // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.
691 //
692 CopyMem (&mAcpiCpuData, AcpiCpuData, sizeof (mAcpiCpuData));
693
694 mAcpiCpuData.MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (MTRR_SETTINGS));
695 ASSERT (mAcpiCpuData.MtrrTable != 0);
696
697 CopyMem ((VOID *)(UINTN)mAcpiCpuData.MtrrTable, (VOID *)(UINTN)AcpiCpuData->MtrrTable, sizeof (MTRR_SETTINGS));
698
699 mAcpiCpuData.GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
700 ASSERT (mAcpiCpuData.GdtrProfile != 0);
701
702 CopyMem ((VOID *)(UINTN)mAcpiCpuData.GdtrProfile, (VOID *)(UINTN)AcpiCpuData->GdtrProfile, sizeof (IA32_DESCRIPTOR));
703
704 mAcpiCpuData.IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (sizeof (IA32_DESCRIPTOR));
705 ASSERT (mAcpiCpuData.IdtrProfile != 0);
706
707 CopyMem ((VOID *)(UINTN)mAcpiCpuData.IdtrProfile, (VOID *)(UINTN)AcpiCpuData->IdtrProfile, sizeof (IA32_DESCRIPTOR));
708
709 mAcpiCpuData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
710 ASSERT (mAcpiCpuData.PreSmmInitRegisterTable != 0);
711
712 CopyRegisterTable (
713 (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.PreSmmInitRegisterTable,
714 (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->PreSmmInitRegisterTable,
715 mAcpiCpuData.NumberOfCpus
716 );
717
718 mAcpiCpuData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
719 ASSERT (mAcpiCpuData.RegisterTable != 0);
720
721 CopyRegisterTable (
722 (CPU_REGISTER_TABLE *)(UINTN)mAcpiCpuData.RegisterTable,
723 (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->RegisterTable,
724 mAcpiCpuData.NumberOfCpus
725 );
726
727 //
728 // Copy AP's GDT, IDT and Machine Check handler into SMRAM.
729 //
730 Gdtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile;
731 Idtr = (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile;
732
733 mGdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);
734 ASSERT (mGdtForAp != NULL);
735 mIdtForAp = (VOID *) ((UINTN)mGdtForAp + (Gdtr->Limit + 1));
736 mMachineCheckHandlerForAp = (VOID *) ((UINTN)mIdtForAp + (Idtr->Limit + 1));
737
738 CopyMem (mGdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);
739 CopyMem (mIdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);
740 CopyMem (mMachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);
741
742 Done:
743 //
744 // Set SMM ready to lock flag and return
745 //
746 mSmmReadyToLock = TRUE;
747 return EFI_SUCCESS;
748 }
749
750 /**
751 The module Entry Point of the CPU SMM driver.
752
753 @param ImageHandle The firmware allocated handle for the EFI image.
754 @param SystemTable A pointer to the EFI System Table.
755
756 @retval EFI_SUCCESS The entry point is executed successfully.
757 @retval Other Some error occurs when executing this entry point.
758
759 **/
760 EFI_STATUS
761 EFIAPI
762 PiCpuSmmEntry (
763 IN EFI_HANDLE ImageHandle,
764 IN EFI_SYSTEM_TABLE *SystemTable
765 )
766 {
767 EFI_STATUS Status;
768 EFI_MP_SERVICES_PROTOCOL *MpServices;
769 UINTN NumberOfEnabledProcessors;
770 UINTN Index;
771 VOID *Buffer;
772 UINTN BufferPages;
773 UINTN TileCodeSize;
774 UINTN TileDataSize;
775 UINTN TileSize;
776 VOID *GuidHob;
777 EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
778 SMM_S3_RESUME_STATE *SmmS3ResumeState;
779 UINT8 *Stacks;
780 VOID *Registration;
781 UINT32 RegEax;
782 UINT32 RegEdx;
783 UINTN FamilyId;
784 UINTN ModelId;
785 UINT32 Cr3;
786
787 //
788 // Initialize Debug Agent to support source level debug in SMM code
789 //
790 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL);
791
792 //
793 // Report the start of CPU SMM initialization.
794 //
795 REPORT_STATUS_CODE (
796 EFI_PROGRESS_CODE,
797 EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT
798 );
799
800 //
801 // Fix segment address of the long-mode-switch jump
802 //
803 if (sizeof (UINTN) == sizeof (UINT64)) {
804 gSmmJmpAddr.Segment = LONG_MODE_CODE_SEGMENT;
805 }
806
807 //
808 // Find out SMRR Base and SMRR Size
809 //
810 FindSmramInfo (&mCpuHotPlugData.SmrrBase, &mCpuHotPlugData.SmrrSize);
811
812 //
813 // Get MP Services Protocol
814 //
815 Status = SystemTable->BootServices->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices);
816 ASSERT_EFI_ERROR (Status);
817
818 //
819 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
820 //
821 Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus, &NumberOfEnabledProcessors);
822 ASSERT_EFI_ERROR (Status);
823 ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
824
825 //
826 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
827 // A constant BSP index makes no sense because it may be hot removed.
828 //
829 DEBUG_CODE (
830 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
831
832 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));
833 }
834 );
835
836 //
837 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
838 //
839 mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable);
840 DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));
841
842 //
843 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
844 //
845 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
846 mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
847 } else {
848 mMaxNumberOfCpus = mNumberOfCpus;
849 }
850 gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;
851
852 //
853 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
854 // allocated buffer. The minimum size of this buffer for a uniprocessor system
855 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
856 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
857 // then the SMI entry point and the CPU save state areas can be tiles to minimize
858 // the total amount SMRAM required for all the CPUs. The tile size can be computed
859 // by adding the // CPU save state size, any extra CPU specific context, and
860 // the size of code that must be placed at the SMI entry point to transfer
861 // control to a C function in the native SMM execution mode. This size is
862 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
863 // The total amount of memory required is the maximum number of CPUs that
864 // platform supports times the tile size. The picture below shows the tiling,
865 // where m is the number of tiles that fit in 32KB.
866 //
867 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
868 // | CPU m+1 Save State |
869 // +-----------------------------+
870 // | CPU m+1 Extra Data |
871 // +-----------------------------+
872 // | Padding |
873 // +-----------------------------+
874 // | CPU 2m SMI Entry |
875 // +#############################+ <-- Base of allocated buffer + 64 KB
876 // | CPU m-1 Save State |
877 // +-----------------------------+
878 // | CPU m-1 Extra Data |
879 // +-----------------------------+
880 // | Padding |
881 // +-----------------------------+
882 // | CPU 2m-1 SMI Entry |
883 // +=============================+ <-- 2^n offset from Base of allocated buffer
884 // | . . . . . . . . . . . . |
885 // +=============================+ <-- 2^n offset from Base of allocated buffer
886 // | CPU 2 Save State |
887 // +-----------------------------+
888 // | CPU 2 Extra Data |
889 // +-----------------------------+
890 // | Padding |
891 // +-----------------------------+
892 // | CPU m+1 SMI Entry |
893 // +=============================+ <-- Base of allocated buffer + 32 KB
894 // | CPU 1 Save State |
895 // +-----------------------------+
896 // | CPU 1 Extra Data |
897 // +-----------------------------+
898 // | Padding |
899 // +-----------------------------+
900 // | CPU m SMI Entry |
901 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
902 // | CPU 0 Save State |
903 // +-----------------------------+
904 // | CPU 0 Extra Data |
905 // +-----------------------------+
906 // | Padding |
907 // +-----------------------------+
908 // | CPU m-1 SMI Entry |
909 // +=============================+ <-- 2^n offset from Base of allocated buffer
910 // | . . . . . . . . . . . . |
911 // +=============================+ <-- 2^n offset from Base of allocated buffer
912 // | Padding |
913 // +-----------------------------+
914 // | CPU 1 SMI Entry |
915 // +=============================+ <-- 2^n offset from Base of allocated buffer
916 // | Padding |
917 // +-----------------------------+
918 // | CPU 0 SMI Entry |
919 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
920 //
921
922 //
923 // Retrieve CPU Family
924 //
925 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
926 FamilyId = (RegEax >> 8) & 0xf;
927 ModelId = (RegEax >> 4) & 0xf;
928 if (FamilyId == 0x06 || FamilyId == 0x0f) {
929 ModelId = ModelId | ((RegEax >> 12) & 0xf0);
930 }
931
932 RegEdx = 0;
933 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
934 if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
935 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
936 }
937 //
938 // Determine the mode of the CPU at the time an SMI occurs
939 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
940 // Volume 3C, Section 34.4.1.1
941 //
942 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
943 if ((RegEdx & BIT29) != 0) {
944 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
945 }
946 if (FamilyId == 0x06) {
947 if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) {
948 mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
949 }
950 }
951
952 //
953 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
954 // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size
955 // is rounded up to nearest power of 2.
956 //
957 TileCodeSize = GetSmiHandlerSize ();
958 TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
959 TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);
960 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
961 TileSize = TileDataSize + TileCodeSize - 1;
962 TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
963 DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
964
965 //
966 // If the TileSize is larger than space available for the SMI Handler of CPU[i],
967 // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],
968 // the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be
969 // reduced.
970 //
971 ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));
972
973 //
974 // Allocate buffer for all of the tiles.
975 //
976 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
977 // Volume 3C, Section 34.11 SMBASE Relocation
978 // For Pentium and Intel486 processors, the SMBASE values must be
979 // aligned on a 32-KByte boundary or the processor will enter shutdown
980 // state during the execution of a RSM instruction.
981 //
982 // Intel486 processors: FamilyId is 4
983 // Pentium processors : FamilyId is 5
984 //
985 BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1));
986 if ((FamilyId == 4) || (FamilyId == 5)) {
987 Buffer = AllocateAlignedPages (BufferPages, SIZE_32KB);
988 } else {
989 Buffer = AllocateAlignedPages (BufferPages, SIZE_4KB);
990 }
991 ASSERT (Buffer != NULL);
992 DEBUG ((EFI_D_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages)));
993
994 //
995 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
996 //
997 gSmmCpuPrivate->ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus);
998 ASSERT (gSmmCpuPrivate->ProcessorInfo != NULL);
999
1000 gSmmCpuPrivate->Operation = (SMM_CPU_OPERATION *)AllocatePool (sizeof (SMM_CPU_OPERATION) * mMaxNumberOfCpus);
1001 ASSERT (gSmmCpuPrivate->Operation != NULL);
1002
1003 gSmmCpuPrivate->CpuSaveStateSize = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);
1004 ASSERT (gSmmCpuPrivate->CpuSaveStateSize != NULL);
1005
1006 gSmmCpuPrivate->CpuSaveState = (VOID **)AllocatePool (sizeof (VOID *) * mMaxNumberOfCpus);
1007 ASSERT (gSmmCpuPrivate->CpuSaveState != NULL);
1008
1009 mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize;
1010 mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState = gSmmCpuPrivate->CpuSaveState;
1011
1012 //
1013 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
1014 //
1015 mCpuHotPlugData.ApicId = (UINT64 *)AllocatePool (sizeof (UINT64) * mMaxNumberOfCpus);
1016 ASSERT (mCpuHotPlugData.ApicId != NULL);
1017 mCpuHotPlugData.SmBase = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);
1018 ASSERT (mCpuHotPlugData.SmBase != NULL);
1019 mCpuHotPlugData.ArrayLength = (UINT32)mMaxNumberOfCpus;
1020
1021 //
1022 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
1023 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
1024 // size for each CPU in the platform
1025 //
1026 for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
1027 mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
1028 gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP);
1029 gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);
1030 gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
1031
1032 if (Index < mNumberOfCpus) {
1033 Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]);
1034 ASSERT_EFI_ERROR (Status);
1035 mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;
1036
1037 DEBUG ((EFI_D_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
1038 Index,
1039 (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,
1040 mCpuHotPlugData.SmBase[Index],
1041 gSmmCpuPrivate->CpuSaveState[Index],
1042 gSmmCpuPrivate->CpuSaveStateSize[Index]
1043 ));
1044 } else {
1045 gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID;
1046 mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID;
1047 }
1048 }
1049
1050 //
1051 // Allocate SMI stacks for all processors.
1052 //
1053 if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
1054 //
1055 // 2 more pages is allocated for each processor.
1056 // one is guard page and the other is known good stack.
1057 //
1058 // +-------------------------------------------+-----+-------------------------------------------+
1059 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
1060 // +-------------------------------------------+-----+-------------------------------------------+
1061 // | | | |
1062 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
1063 //
1064 mSmmStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2);
1065 Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2));
1066 ASSERT (Stacks != NULL);
1067 mSmmStackArrayBase = (UINTN)Stacks;
1068 mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize - 1;
1069 } else {
1070 mSmmStackSize = PcdGet32 (PcdCpuSmmStackSize);
1071 Stacks = (UINT8 *) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize));
1072 ASSERT (Stacks != NULL);
1073 }
1074
1075 //
1076 // Set SMI stack for SMM base relocation
1077 //
1078 gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));
1079
1080 //
1081 // Initialize IDT
1082 //
1083 InitializeSmmIdt ();
1084
1085 //
1086 // Relocate SMM Base addresses to the ones allocated from SMRAM
1087 //
1088 mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus);
1089 ASSERT (mRebased != NULL);
1090 SmmRelocateBases ();
1091
1092 //
1093 // Call hook for BSP to perform extra actions in normal mode after all
1094 // SMM base addresses have been relocated on all CPUs
1095 //
1096 SmmCpuFeaturesSmmRelocationComplete ();
1097
1098 //
1099 // SMM Time initialization
1100 //
1101 InitializeSmmTimer ();
1102
1103 //
1104 // Initialize MP globals
1105 //
1106 Cr3 = InitializeMpServiceData (Stacks, mSmmStackSize);
1107
1108 //
1109 // Fill in SMM Reserved Regions
1110 //
1111 gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0;
1112 gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize = 0;
1113
1114 //
1115 // Install the SMM Configuration Protocol onto a new handle on the handle database.
1116 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
1117 // to an SMRAM address will be present in the handle database
1118 //
1119 Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (
1120 &gSmmCpuPrivate->SmmCpuHandle,
1121 &gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration,
1122 NULL
1123 );
1124 ASSERT_EFI_ERROR (Status);
1125
1126 //
1127 // Install the SMM CPU Protocol into SMM protocol database
1128 //
1129 Status = gSmst->SmmInstallProtocolInterface (
1130 &mSmmCpuHandle,
1131 &gEfiSmmCpuProtocolGuid,
1132 EFI_NATIVE_INTERFACE,
1133 &mSmmCpu
1134 );
1135 ASSERT_EFI_ERROR (Status);
1136
1137 //
1138 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
1139 //
1140 if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
1141 Status = PcdSet64S (PcdCpuHotPlugDataAddress, (UINT64)(UINTN)&mCpuHotPlugData);
1142 ASSERT_EFI_ERROR (Status);
1143 }
1144
1145 //
1146 // Initialize SMM CPU Services Support
1147 //
1148 Status = InitializeSmmCpuServices (mSmmCpuHandle);
1149 ASSERT_EFI_ERROR (Status);
1150
1151 //
1152 // register SMM Ready To Lock Protocol notification
1153 //
1154 Status = gSmst->SmmRegisterProtocolNotify (
1155 &gEfiSmmReadyToLockProtocolGuid,
1156 SmmReadyToLockEventNotify,
1157 &Registration
1158 );
1159 ASSERT_EFI_ERROR (Status);
1160
1161 GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);
1162 if (GuidHob != NULL) {
1163 SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);
1164
1165 DEBUG ((EFI_D_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));
1166 DEBUG ((EFI_D_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));
1167
1168 SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;
1169 ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));
1170
1171 mSmmS3ResumeState = SmmS3ResumeState;
1172 SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst;
1173
1174 SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu;
1175
1176 SmmS3ResumeState->SmmS3StackSize = SIZE_32KB;
1177 SmmS3ResumeState->SmmS3StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)SmmS3ResumeState->SmmS3StackSize));
1178 if (SmmS3ResumeState->SmmS3StackBase == 0) {
1179 SmmS3ResumeState->SmmS3StackSize = 0;
1180 }
1181
1182 SmmS3ResumeState->SmmS3Cr0 = gSmmCr0;
1183 SmmS3ResumeState->SmmS3Cr3 = Cr3;
1184 SmmS3ResumeState->SmmS3Cr4 = gSmmCr4;
1185
1186 if (sizeof (UINTN) == sizeof (UINT64)) {
1187 SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
1188 }
1189 if (sizeof (UINTN) == sizeof (UINT32)) {
1190 SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;
1191 }
1192 }
1193
1194 //
1195 // Check XD and BTS features
1196 //
1197 CheckProcessorFeature ();
1198
1199 //
1200 // Initialize SMM Profile feature
1201 //
1202 InitSmmProfile (Cr3);
1203
1204 //
1205 // Patch SmmS3ResumeState->SmmS3Cr3
1206 //
1207 InitSmmS3Cr3 ();
1208
1209 DEBUG ((EFI_D_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
1210
1211 return EFI_SUCCESS;
1212 }
1213
1214 /**
1215
1216 Find out SMRAM information including SMRR base and SMRR size.
1217
1218 @param SmrrBase SMRR base
1219 @param SmrrSize SMRR size
1220
1221 **/
1222 VOID
1223 FindSmramInfo (
1224 OUT UINT32 *SmrrBase,
1225 OUT UINT32 *SmrrSize
1226 )
1227 {
1228 EFI_STATUS Status;
1229 UINTN Size;
1230 EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
1231 EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;
1232 EFI_SMRAM_DESCRIPTOR *SmramRanges;
1233 UINTN SmramRangeCount;
1234 UINTN Index;
1235 UINT64 MaxSize;
1236 BOOLEAN Found;
1237
1238 //
1239 // Get SMM Access Protocol
1240 //
1241 Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);
1242 ASSERT_EFI_ERROR (Status);
1243
1244 //
1245 // Get SMRAM information
1246 //
1247 Size = 0;
1248 Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);
1249 ASSERT (Status == EFI_BUFFER_TOO_SMALL);
1250
1251 SmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
1252 ASSERT (SmramRanges != NULL);
1253
1254 Status = SmmAccess->GetCapabilities (SmmAccess, &Size, SmramRanges);
1255 ASSERT_EFI_ERROR (Status);
1256
1257 SmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
1258
1259 //
1260 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
1261 //
1262 CurrentSmramRange = NULL;
1263 for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < SmramRangeCount; Index++) {
1264 //
1265 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
1266 //
1267 if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
1268 continue;
1269 }
1270
1271 if (SmramRanges[Index].CpuStart >= BASE_1MB) {
1272 if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) <= BASE_4GB) {
1273 if (SmramRanges[Index].PhysicalSize >= MaxSize) {
1274 MaxSize = SmramRanges[Index].PhysicalSize;
1275 CurrentSmramRange = &SmramRanges[Index];
1276 }
1277 }
1278 }
1279 }
1280
1281 ASSERT (CurrentSmramRange != NULL);
1282
1283 *SmrrBase = (UINT32)CurrentSmramRange->CpuStart;
1284 *SmrrSize = (UINT32)CurrentSmramRange->PhysicalSize;
1285
1286 do {
1287 Found = FALSE;
1288 for (Index = 0; Index < SmramRangeCount; Index++) {
1289 if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase == (SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) {
1290 *SmrrBase = (UINT32)SmramRanges[Index].CpuStart;
1291 *SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);
1292 Found = TRUE;
1293 } else if ((*SmrrBase + *SmrrSize) == SmramRanges[Index].CpuStart && SmramRanges[Index].PhysicalSize > 0) {
1294 *SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);
1295 Found = TRUE;
1296 }
1297 }
1298 } while (Found);
1299
1300 DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));
1301 }
1302
1303 /**
1304 Configure SMM Code Access Check feature on an AP.
1305 SMM Feature Control MSR will be locked after configuration.
1306
1307 @param[in,out] Buffer Pointer to private data buffer.
1308 **/
1309 VOID
1310 EFIAPI
1311 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1312 IN OUT VOID *Buffer
1313 )
1314 {
1315 UINTN CpuIndex;
1316 UINT64 SmmFeatureControlMsr;
1317 UINT64 NewSmmFeatureControlMsr;
1318
1319 //
1320 // Retrieve the CPU Index from the context passed in
1321 //
1322 CpuIndex = *(UINTN *)Buffer;
1323
1324 //
1325 // Get the current SMM Feature Control MSR value
1326 //
1327 SmmFeatureControlMsr = SmmCpuFeaturesGetSmmRegister (CpuIndex, SmmRegFeatureControl);
1328
1329 //
1330 // Compute the new SMM Feature Control MSR value
1331 //
1332 NewSmmFeatureControlMsr = SmmFeatureControlMsr;
1333 if (mSmmCodeAccessCheckEnable) {
1334 NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT;
1335 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {
1336 NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT;
1337 }
1338 }
1339
1340 //
1341 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1342 //
1343 if (NewSmmFeatureControlMsr != SmmFeatureControlMsr) {
1344 SmmCpuFeaturesSetSmmRegister (CpuIndex, SmmRegFeatureControl, NewSmmFeatureControlMsr);
1345 }
1346
1347 //
1348 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1349 //
1350 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
1351 }
1352
1353 /**
1354 Configure SMM Code Access Check feature for all processors.
1355 SMM Feature Control MSR will be locked after configuration.
1356 **/
1357 VOID
1358 ConfigSmmCodeAccessCheck (
1359 VOID
1360 )
1361 {
1362 UINTN Index;
1363 EFI_STATUS Status;
1364
1365 //
1366 // Check to see if the Feature Control MSR is supported on this CPU
1367 //
1368 Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
1369 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) {
1370 mSmmCodeAccessCheckEnable = FALSE;
1371 return;
1372 }
1373
1374 //
1375 // Check to see if the CPU supports the SMM Code Access Check feature
1376 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1377 //
1378 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) {
1379 mSmmCodeAccessCheckEnable = FALSE;
1380 return;
1381 }
1382
1383 //
1384 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1385 //
1386 InitializeSpinLock (mConfigSmmCodeAccessCheckLock);
1387
1388 //
1389 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1390 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1391 //
1392 AcquireSpinLock (mConfigSmmCodeAccessCheckLock);
1393
1394 //
1395 // Enable SMM Code Access Check feature on the BSP.
1396 //
1397 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index);
1398
1399 //
1400 // Enable SMM Code Access Check feature for the APs.
1401 //
1402 for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
1403 if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {
1404
1405 //
1406 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1407 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1408 //
1409 AcquireSpinLock (mConfigSmmCodeAccessCheckLock);
1410
1411 //
1412 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1413 //
1414 Status = gSmst->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor, Index, &Index);
1415 ASSERT_EFI_ERROR (Status);
1416
1417 //
1418 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1419 //
1420 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock)) {
1421 CpuPause ();
1422 }
1423
1424 //
1425 // Release the Config SMM Code Access Check spin lock.
1426 //
1427 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
1428 }
1429 }
1430 }
1431
1432 /**
1433 This API provides a way to allocate memory for page table.
1434
1435 This API can be called more once to allocate memory for page tables.
1436
1437 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
1438 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
1439 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
1440 returned.
1441
1442 @param Pages The number of 4 KB pages to allocate.
1443
1444 @return A pointer to the allocated buffer or NULL if allocation fails.
1445
1446 **/
1447 VOID *
1448 AllocatePageTableMemory (
1449 IN UINTN Pages
1450 )
1451 {
1452 VOID *Buffer;
1453
1454 Buffer = SmmCpuFeaturesAllocatePageTableMemory (Pages);
1455 if (Buffer != NULL) {
1456 return Buffer;
1457 }
1458 return AllocatePages (Pages);
1459 }
1460
1461 /**
1462 Perform the remaining tasks.
1463
1464 **/
1465 VOID
1466 PerformRemainingTasks (
1467 VOID
1468 )
1469 {
1470 if (mSmmReadyToLock) {
1471 //
1472 // Start SMM Profile feature
1473 //
1474 if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
1475 SmmProfileStart ();
1476 }
1477 //
1478 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1479 //
1480 InitPaging ();
1481 //
1482 // Configure SMM Code Access Check feature if available.
1483 //
1484 ConfigSmmCodeAccessCheck ();
1485
1486 SmmCpuFeaturesCompleteSmmReadyToLock ();
1487
1488 //
1489 // Clean SMM ready to lock flag
1490 //
1491 mSmmReadyToLock = FALSE;
1492 }
1493 }
1494
1495 /**
1496 Perform the pre tasks.
1497
1498 **/
1499 VOID
1500 PerformPreTasks (
1501 VOID
1502 )
1503 {
1504 //
1505 // Restore SMM Configuration in S3 boot path.
1506 //
1507 if (mRestoreSmmConfigurationInS3) {
1508 //
1509 // Need make sure gSmst is correct because below function may use them.
1510 //
1511 gSmst->SmmStartupThisAp = gSmmCpuPrivate->SmmCoreEntryContext.SmmStartupThisAp;
1512 gSmst->CurrentlyExecutingCpu = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;
1513 gSmst->NumberOfCpus = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
1514 gSmst->CpuSaveStateSize = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveStateSize;
1515 gSmst->CpuSaveState = gSmmCpuPrivate->SmmCoreEntryContext.CpuSaveState;
1516
1517 //
1518 // Configure SMM Code Access Check feature if available.
1519 //
1520 ConfigSmmCodeAccessCheck ();
1521
1522 SmmCpuFeaturesCompleteSmmReadyToLock ();
1523
1524 mRestoreSmmConfigurationInS3 = FALSE;
1525 }
1526 }
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