UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h

   1 /** @file
   2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
   3
   4 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_PISMMCPUDXESMM_H_
  16 #define _CPU_PISMMCPUDXESMM_H_
  17
  18 #include <PiSmm.h>
  19
  20 #include <Protocol/MpService.h>
  21 #include <Protocol/SmmConfiguration.h>
  22 #include <Protocol/SmmCpu.h>
  23 #include <Protocol/SmmAccess2.h>
  24 #include <Protocol/SmmCpuSaveState.h>
  25 #include <Protocol/SmmReadyToLock.h>
  26 #include <Protocol/SmmCpuService.h>
  27
  28 #include <Guid/AcpiS3Context.h>
  29
  30 #include <Library/BaseLib.h>
  31 #include <Library/IoLib.h>
  32 #include <Library/TimerLib.h>
  33 #include <Library/SynchronizationLib.h>
  34 #include <Library/DebugLib.h>
  35 #include <Library/BaseMemoryLib.h>
  36 #include <Library/PcdLib.h>
  37 #include <Library/CacheMaintenanceLib.h>
  38 #include <Library/MtrrLib.h>
  39 #include <Library/SmmCpuPlatformHookLib.h>
  40 #include <Library/SmmServicesTableLib.h>
  41 #include <Library/MemoryAllocationLib.h>
  42 #include <Library/UefiBootServicesTableLib.h>
  43 #include <Library/UefiRuntimeServicesTableLib.h>
  44 #include <Library/DebugAgentLib.h>
  45 #include <Library/HobLib.h>
  46 #include <Library/LocalApicLib.h>
  47 #include <Library/UefiCpuLib.h>
  48 #include <Library/CpuExceptionHandlerLib.h>
  49 #include <Library/ReportStatusCodeLib.h>
  50 #include <Library/SmmCpuFeaturesLib.h>
  51 #include <Library/PeCoffGetEntryPointLib.h>
  52
  53 #include <AcpiCpuData.h>
  54 #include <CpuHotPlugData.h>
  55
  56 #include <Register/Cpuid.h>
  57
  58 #include "CpuService.h"
  59 #include "SmmProfile.h"
  60
  61 //
  62 // MSRs required for configuration of SMM Code Access Check
  63 //
  64 #define EFI_MSR_SMM_MCA_CAP                    0x17D
  65 #define  SMM_CODE_ACCESS_CHK_BIT               BIT58
  66
  67 #define  SMM_FEATURE_CONTROL_LOCK_BIT          BIT0
  68 #define  SMM_CODE_CHK_EN_BIT                   BIT2
  69
  70 ///
  71 /// Page Table Entry
  72 ///
  73 #define IA32_PG_P                   BIT0
  74 #define IA32_PG_RW                  BIT1
  75 #define IA32_PG_WT                  BIT3
  76 #define IA32_PG_CD                  BIT4
  77 #define IA32_PG_A                   BIT5
  78 #define IA32_PG_PS                  BIT7
  79 #define IA32_PG_PAT_2M              BIT12
  80 #define IA32_PG_PAT_4K              IA32_PG_PS
  81 #define IA32_PG_PMNT                BIT62
  82 #define IA32_PG_NX                  BIT63
  83
  84 //
  85 // Size of Task-State Segment defined in IA32 Manual
  86 //
  87 #define TSS_SIZE              104
  88 #define TSS_X64_IST1_OFFSET   36
  89 #define TSS_IA32_CR3_OFFSET   28
  90 #define TSS_IA32_ESP_OFFSET   56
  91
  92 //
  93 // Code select value
  94 //
  95 #define PROTECT_MODE_CODE_SEGMENT          0x08
  96 #define LONG_MODE_CODE_SEGMENT             0x38
  97
  98 //
  99 // The size 0x20 must be bigger than
 100 // the size of template code of SmmInit. Currently,
 101 // the size of SmmInit requires the 0x16 Bytes buffer
 102 // at least.
 103 //
 104 #define BACK_BUF_SIZE  0x20
 105
 106 #define EXCEPTION_VECTOR_NUMBER     0x20
 107
 108 #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
 109
 110 typedef UINT32                              SMM_CPU_ARRIVAL_EXCEPTIONS;
 111 #define ARRIVAL_EXCEPTION_BLOCKED           0x1
 112 #define ARRIVAL_EXCEPTION_DELAYED           0x2
 113 #define ARRIVAL_EXCEPTION_SMI_DISABLED      0x4
 114
 115 //
 116 // Private structure for the SMM CPU module that is stored in DXE Runtime memory
 117 // Contains the SMM Configuration Protocols that is produced.
 118 // Contains a mix of DXE and SMM contents.  All the fields must be used properly.
 119 //
 120 #define SMM_CPU_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('s', 'c', 'p', 'u')
 121
 122 typedef struct {
 123   UINTN                           Signature;
 124
 125   EFI_HANDLE                      SmmCpuHandle;
 126
 127   EFI_PROCESSOR_INFORMATION       *ProcessorInfo;
 128   SMM_CPU_OPERATION               *Operation;
 129   UINTN                           *CpuSaveStateSize;
 130   VOID                            **CpuSaveState;
 131
 132   EFI_SMM_RESERVED_SMRAM_REGION   SmmReservedSmramRegion[1];
 133   EFI_SMM_ENTRY_CONTEXT           SmmCoreEntryContext;
 134   EFI_SMM_ENTRY_POINT             SmmCoreEntry;
 135
 136   EFI_SMM_CONFIGURATION_PROTOCOL  SmmConfiguration;
 137 } SMM_CPU_PRIVATE_DATA;
 138
 139 extern SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate;
 140 extern CPU_HOT_PLUG_DATA      mCpuHotPlugData;
 141 extern UINTN                  mMaxNumberOfCpus;
 142 extern UINTN                  mNumberOfCpus;
 143 extern BOOLEAN                mRestoreSmmConfigurationInS3;
 144 extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;
 145
 146 ///
 147 /// The mode of the CPU at the time an SMI occurs
 148 ///
 149 extern UINT8  mSmmSaveStateRegisterLma;
 150
 151
 152 //
 153 // SMM CPU Protocol function prototypes.
 154 //
 155
 156 /**
 157   Read information from the CPU save state.
 158
 159   @param  This      EFI_SMM_CPU_PROTOCOL instance
 160   @param  Width     The number of bytes to read from the CPU save state.
 161   @param  Register  Specifies the CPU register to read form the save state.
 162   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 163   @param  Buffer    Upon return, this holds the CPU register value read from the save state.
 164
 165   @retval EFI_SUCCESS   The register was read from Save State
 166   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 167   @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.
 168
 169 **/
 170 EFI_STATUS
 171 EFIAPI
 172 SmmReadSaveState (
 173   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 174   IN UINTN                              Width,
 175   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 176   IN UINTN                              CpuIndex,
 177   OUT VOID                              *Buffer
 178   );
 179
 180 /**
 181   Write data to the CPU save state.
 182
 183   @param  This      EFI_SMM_CPU_PROTOCOL instance
 184   @param  Width     The number of bytes to read from the CPU save state.
 185   @param  Register  Specifies the CPU register to write to the save state.
 186   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 187   @param  Buffer    Upon entry, this holds the new CPU register value.
 188
 189   @retval EFI_SUCCESS   The register was written from Save State
 190   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 191   @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct
 192
 193 **/
 194 EFI_STATUS
 195 EFIAPI
 196 SmmWriteSaveState (
 197   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 198   IN UINTN                              Width,
 199   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 200   IN UINTN                              CpuIndex,
 201   IN CONST VOID                         *Buffer
 202   );
 203
 204 /**
 205 Read a CPU Save State register on the target processor.
 206
 207 This function abstracts the differences that whether the CPU Save State register is in the
 208 IA32 CPU Save State Map or X64 CPU Save State Map.
 209
 210 This function supports reading a CPU Save State register in SMBase relocation handler.
 211
 212 @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
 213 @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 214 @param[in]  Width          The number of bytes to read from the CPU save state.
 215 @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
 216
 217 @retval EFI_SUCCESS           The register was read from Save State.
 218 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 219 @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
 220
 221 **/
 222 EFI_STATUS
 223 EFIAPI
 224 ReadSaveStateRegister (
 225   IN UINTN                        CpuIndex,
 226   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 227   IN UINTN                        Width,
 228   OUT VOID                        *Buffer
 229   );
 230
 231 /**
 232 Write value to a CPU Save State register on the target processor.
 233
 234 This function abstracts the differences that whether the CPU Save State register is in the
 235 IA32 CPU Save State Map or X64 CPU Save State Map.
 236
 237 This function supports writing a CPU Save State register in SMBase relocation handler.
 238
 239 @param[in] CpuIndex       Specifies the zero-based index of the CPU save state.
 240 @param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 241 @param[in] Width          The number of bytes to read from the CPU save state.
 242 @param[in] Buffer         Upon entry, this holds the new CPU register value.
 243
 244 @retval EFI_SUCCESS           The register was written to Save State.
 245 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 246 @retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.
 247
 248 **/
 249 EFI_STATUS
 250 EFIAPI
 251 WriteSaveStateRegister (
 252   IN UINTN                        CpuIndex,
 253   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 254   IN UINTN                        Width,
 255   IN CONST VOID                   *Buffer
 256   );
 257
 258 //
 259 //
 260 //
 261 typedef struct {
 262   UINT32                            Offset;
 263   UINT16                            Segment;
 264   UINT16                            Reserved;
 265 } IA32_FAR_ADDRESS;
 266
 267 extern IA32_FAR_ADDRESS             gSmmJmpAddr;
 268
 269 extern CONST UINT8                  gcSmmInitTemplate[];
 270 extern CONST UINT16                 gcSmmInitSize;
 271 extern UINT32                       gSmmCr0;
 272 extern UINT32                       gSmmCr3;
 273 extern UINT32                       gSmmCr4;
 274 extern UINTN                        gSmmInitStack;
 275
 276 /**
 277   Semaphore operation for all processor relocate SMMBase.
 278 **/
 279 VOID
 280 EFIAPI
 281 SmmRelocationSemaphoreComplete (
 282   VOID
 283   );
 284
 285 ///
 286 /// The type of SMM CPU Information
 287 ///
 288 typedef struct {
 289   SPIN_LOCK                         Busy;
 290   volatile EFI_AP_PROCEDURE         Procedure;
 291   volatile VOID                     *Parameter;
 292   volatile UINT32                   Run;
 293   volatile BOOLEAN                  Present;
 294 } SMM_CPU_DATA_BLOCK;
 295
 296 typedef enum {
 297   SmmCpuSyncModeTradition,
 298   SmmCpuSyncModeRelaxedAp,
 299   SmmCpuSyncModeMax
 300 } SMM_CPU_SYNC_MODE;
 301
 302 typedef struct {
 303   //
 304   // Pointer to an array. The array should be located immediately after this structure
 305   // so that UC cache-ability can be set together.
 306   //
 307   SMM_CPU_DATA_BLOCK            *CpuData;
 308   volatile UINT32               Counter;
 309   volatile UINT32               BspIndex;
 310   volatile BOOLEAN              InsideSmm;
 311   volatile BOOLEAN              AllCpusInSync;
 312   volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;
 313   volatile BOOLEAN              SwitchBsp;
 314   volatile BOOLEAN              *CandidateBsp;
 315 } SMM_DISPATCHER_MP_SYNC_DATA;
 316
 317 typedef struct {
 318   SPIN_LOCK    SpinLock;
 319   UINT32       MsrIndex;
 320 } MP_MSR_LOCK;
 321
 322 #define SMM_PSD_OFFSET              0xfb00
 323
 324 typedef struct {
 325   UINT64                            Signature;              // Offset 0x00
 326   UINT16                            Reserved1;              // Offset 0x08
 327   UINT16                            Reserved2;              // Offset 0x0A
 328   UINT16                            Reserved3;              // Offset 0x0C
 329   UINT16                            SmmCs;                  // Offset 0x0E
 330   UINT16                            SmmDs;                  // Offset 0x10
 331   UINT16                            SmmSs;                  // Offset 0x12
 332   UINT16                            SmmOtherSegment;        // Offset 0x14
 333   UINT16                            Reserved4;              // Offset 0x16
 334   UINT64                            Reserved5;              // Offset 0x18
 335   UINT64                            Reserved6;              // Offset 0x20
 336   UINT64                            Reserved7;              // Offset 0x28
 337   UINT64                            SmmGdtPtr;              // Offset 0x30
 338   UINT32                            SmmGdtSize;             // Offset 0x38
 339   UINT32                            Reserved8;              // Offset 0x3C
 340   UINT64                            Reserved9;              // Offset 0x40
 341   UINT64                            Reserved10;             // Offset 0x48
 342   UINT16                            Reserved11;             // Offset 0x50
 343   UINT16                            Reserved12;             // Offset 0x52
 344   UINT32                            Reserved13;             // Offset 0x54
 345   UINT64                            MtrrBaseMaskPtr;        // Offset 0x58
 346 } PROCESSOR_SMM_DESCRIPTOR;
 347
 348 extern IA32_DESCRIPTOR                     gcSmiGdtr;
 349 extern IA32_DESCRIPTOR                     gcSmiIdtr;
 350 extern VOID                                *gcSmiIdtrPtr;
 351 extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;
 352 extern UINT64                              gPhyMask;
 353 extern ACPI_CPU_DATA                       mAcpiCpuData;
 354 extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;
 355 extern VOID                                *mGdtForAp;
 356 extern VOID                                *mIdtForAp;
 357 extern VOID                                *mMachineCheckHandlerForAp;
 358 extern UINTN                               mSmmStackArrayBase;
 359 extern UINTN                               mSmmStackArrayEnd;
 360 extern UINTN                               mSmmStackSize;
 361 extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;
 362 extern IA32_DESCRIPTOR                     gcSmiInitGdtr;
 363
 364 /**
 365   Create 4G PageTable in SMRAM.
 366
 367   @param          ExtraPages       Additional page numbers besides for 4G memory
 368   @return         PageTable Address
 369
 370 **/
 371 UINT32
 372 Gen4GPageTable (
 373   IN      UINTN                     ExtraPages
 374   );
 375
 376
 377 /**
 378   Initialize global data for MP synchronization.
 379
 380   @param Stacks       Base address of SMI stack buffer for all processors.
 381   @param StackSize    Stack size for each processor in SMM.
 382
 383 **/
 384 UINT32
 385 InitializeMpServiceData (
 386   IN VOID        *Stacks,
 387   IN UINTN       StackSize
 388   );
 389
 390 /**
 391   Initialize Timer for SMM AP Sync.
 392
 393 **/
 394 VOID
 395 InitializeSmmTimer (
 396   VOID
 397   );
 398
 399 /**
 400   Start Timer for SMM AP Sync.
 401
 402 **/
 403 UINT64
 404 EFIAPI
 405 StartSyncTimer (
 406   VOID
 407   );
 408
 409 /**
 410   Check if the SMM AP Sync timer is timeout.
 411
 412   @param Timer  The start timer from the begin.
 413
 414 **/
 415 BOOLEAN
 416 EFIAPI
 417 IsSyncTimerTimeout (
 418   IN      UINT64                    Timer
 419   );
 420
 421 /**
 422   Initialize IDT for SMM Stack Guard.
 423
 424 **/
 425 VOID
 426 EFIAPI
 427 InitializeIDTSmmStackGuard (
 428   VOID
 429   );
 430
 431 /**
 432
 433   Register the SMM Foundation entry point.
 434
 435   @param          This              Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
 436   @param          SmmEntryPoint     SMM Foundation EntryPoint
 437
 438   @retval         EFI_SUCCESS       Successfully to register SMM foundation entry point
 439
 440 **/
 441 EFI_STATUS
 442 EFIAPI
 443 RegisterSmmEntry (
 444   IN CONST EFI_SMM_CONFIGURATION_PROTOCOL  *This,
 445   IN EFI_SMM_ENTRY_POINT                   SmmEntryPoint
 446   );
 447
 448 /**
 449   Create PageTable for SMM use.
 450
 451   @return     PageTable Address
 452
 453 **/
 454 UINT32
 455 SmmInitPageTable (
 456   VOID
 457   );
 458
 459 /**
 460   Schedule a procedure to run on the specified CPU.
 461
 462   @param   Procedure        The address of the procedure to run
 463   @param   CpuIndex         Target CPU number
 464   @param   ProcArguments    The parameter to pass to the procedure
 465
 466   @retval   EFI_INVALID_PARAMETER    CpuNumber not valid
 467   @retval   EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 468   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 469   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 470   @retval   EFI_SUCCESS - The procedure has been successfully scheduled
 471
 472 **/
 473 EFI_STATUS
 474 EFIAPI
 475 SmmStartupThisAp (
 476   IN      EFI_AP_PROCEDURE          Procedure,
 477   IN      UINTN                     CpuIndex,
 478   IN OUT  VOID                      *ProcArguments OPTIONAL
 479   );
 480
 481 /**
 482   Schedule a procedure to run on the specified CPU in a blocking fashion.
 483
 484   @param  Procedure                The address of the procedure to run
 485   @param  CpuIndex                 Target CPU Index
 486   @param  ProcArguments            The parameter to pass to the procedure
 487
 488   @retval EFI_INVALID_PARAMETER    CpuNumber not valid
 489   @retval EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 490   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 491   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 492   @retval EFI_SUCCESS              The procedure has been successfully scheduled
 493
 494 **/
 495 EFI_STATUS
 496 EFIAPI
 497 SmmBlockingStartupThisAp (
 498   IN      EFI_AP_PROCEDURE          Procedure,
 499   IN      UINTN                     CpuIndex,
 500   IN OUT  VOID                      *ProcArguments OPTIONAL
 501   );
 502
 503 /**
 504   Initialize MP synchronization data.
 505
 506 **/
 507 VOID
 508 EFIAPI
 509 InitializeMpSyncData (
 510   VOID
 511   );
 512
 513 /**
 514
 515   Find out SMRAM information including SMRR base and SMRR size.
 516
 517   @param          SmrrBase          SMRR base
 518   @param          SmrrSize          SMRR size
 519
 520 **/
 521 VOID
 522 FindSmramInfo (
 523   OUT UINT32   *SmrrBase,
 524   OUT UINT32   *SmrrSize
 525   );
 526
 527 /**
 528   The function is invoked before SMBASE relocation in S3 path to restores CPU status.
 529
 530   The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
 531   and restores MTRRs for both BSP and APs.
 532
 533 **/
 534 VOID
 535 EarlyInitializeCpu (
 536   VOID
 537   );
 538
 539 /**
 540   The function is invoked after SMBASE relocation in S3 path to restores CPU status.
 541
 542   The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
 543   data saved by normal boot path for both BSP and APs.
 544
 545 **/
 546 VOID
 547 InitializeCpu (
 548   VOID
 549   );
 550
 551 /**
 552   Page Fault handler for SMM use.
 553
 554   @param  InterruptType    Defines the type of interrupt or exception that
 555                            occurred on the processor.This parameter is processor architecture specific.
 556   @param  SystemContext    A pointer to the processor context when
 557                            the interrupt occurred on the processor.
 558 **/
 559 VOID
 560 EFIAPI
 561 SmiPFHandler (
 562     IN EFI_EXCEPTION_TYPE   InterruptType,
 563     IN EFI_SYSTEM_CONTEXT   SystemContext
 564   );
 565
 566 /**
 567   Perform the remaining tasks.
 568
 569 **/
 570 VOID
 571 PerformRemainingTasks (
 572   VOID
 573   );
 574
 575 /**
 576   Initialize MSR spin lock by MSR index.
 577
 578   @param  MsrIndex       MSR index value.
 579
 580 **/
 581 VOID
 582 InitMsrSpinLockByIndex (
 583   IN UINT32      MsrIndex
 584   );
 585
 586 /**
 587   Hook return address of SMM Save State so that semaphore code
 588   can be executed immediately after AP exits SMM to indicate to
 589   the BSP that an AP has exited SMM after SMBASE relocation.
 590
 591   @param[in] CpuIndex     The processor index.
 592   @param[in] RebasedFlag  A pointer to a flag that is set to TRUE
 593                           immediately after AP exits SMM.
 594
 595 **/
 596 VOID
 597 SemaphoreHook (
 598   IN UINTN             CpuIndex,
 599   IN volatile BOOLEAN  *RebasedFlag
 600   );
 601
 602 /**
 603 Configure SMM Code Access Check feature for all processors.
 604 SMM Feature Control MSR will be locked after configuration.
 605 **/
 606 VOID
 607 ConfigSmmCodeAccessCheck (
 608   VOID
 609   );
 610
 611 /**
 612   Hook the code executed immediately after an RSM instruction on the currently
 613   executing CPU.  The mode of code executed immediately after RSM must be
 614   detected, and the appropriate hook must be selected.  Always clear the auto
 615   HALT restart flag if it is set.
 616
 617   @param[in] CpuIndex                 The processor index for the currently
 618                                       executing CPU.
 619   @param[in] CpuState                 Pointer to SMRAM Save State Map for the
 620                                       currently executing CPU.
 621   @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
 622                                       32-bit mode from 64-bit SMM.
 623   @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
 624                                       same mode as SMM.
 625
 626   @retval The value of the original instruction pointer before it was hooked.
 627
 628 **/
 629 UINT64
 630 EFIAPI
 631 HookReturnFromSmm (
 632   IN UINTN              CpuIndex,
 633   SMRAM_SAVE_STATE_MAP  *CpuState,
 634   UINT64                NewInstructionPointer32,
 635   UINT64                NewInstructionPointer
 636   );
 637
 638 /**
 639   Get the size of the SMI Handler in bytes.
 640
 641   @retval The size, in bytes, of the SMI Handler.
 642
 643 **/
 644 UINTN
 645 EFIAPI
 646 GetSmiHandlerSize (
 647   VOID
 648   );
 649
 650 /**
 651   Install the SMI handler for the CPU specified by CpuIndex.  This function
 652   is called by the CPU that was elected as monarch during System Management
 653   Mode initialization.
 654
 655   @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
 656                         The value must be between 0 and the NumberOfCpus field
 657                         in the System Management System Table (SMST).
 658   @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
 659   @param[in] SmiStack   The stack to use when an SMI is processed by the
 660                         the CPU specified by CpuIndex.
 661   @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
 662                         processed by the CPU specified by CpuIndex.
 663   @param[in] GdtBase    The base address of the GDT to use when an SMI is
 664                         processed by the CPU specified by CpuIndex.
 665   @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
 666                         processed by the CPU specified by CpuIndex.
 667   @param[in] IdtBase    The base address of the IDT to use when an SMI is
 668                         processed by the CPU specified by CpuIndex.
 669   @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
 670                         processed by the CPU specified by CpuIndex.
 671   @param[in] Cr3        The base address of the page tables to use when an SMI
 672                         is processed by the CPU specified by CpuIndex.
 673 **/
 674 VOID
 675 EFIAPI
 676 InstallSmiHandler (
 677   IN UINTN   CpuIndex,
 678   IN UINT32  SmBase,
 679   IN VOID    *SmiStack,
 680   IN UINTN   StackSize,
 681   IN UINTN   GdtBase,
 682   IN UINTN   GdtSize,
 683   IN UINTN   IdtBase,
 684   IN UINTN   IdtSize,
 685   IN UINT32  Cr3
 686   );
 687
 688 /**
 689   Search module name by input IP address and output it.
 690
 691   @param CallerIpAddress   Caller instruction pointer.
 692
 693 **/
 694 VOID
 695 DumpModuleInfoByIp (
 696   IN  UINTN              CallerIpAddress
 697   );
 698 #endif