2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef _CPU_PISMMCPUDXESMM_H_
16 #define _CPU_PISMMCPUDXESMM_H_
20 #include <Protocol/MpService.h>
21 #include <Protocol/SmmConfiguration.h>
22 #include <Protocol/SmmCpu.h>
23 #include <Protocol/SmmAccess2.h>
24 #include <Protocol/SmmReadyToLock.h>
25 #include <Protocol/SmmCpuService.h>
27 #include <Guid/AcpiS3Context.h>
28 #include <Guid/PiSmmMemoryAttributesTable.h>
30 #include <Library/BaseLib.h>
31 #include <Library/IoLib.h>
32 #include <Library/TimerLib.h>
33 #include <Library/SynchronizationLib.h>
34 #include <Library/DebugLib.h>
35 #include <Library/BaseMemoryLib.h>
36 #include <Library/PcdLib.h>
37 #include <Library/CacheMaintenanceLib.h>
38 #include <Library/MtrrLib.h>
39 #include <Library/SmmCpuPlatformHookLib.h>
40 #include <Library/SmmServicesTableLib.h>
41 #include <Library/MemoryAllocationLib.h>
42 #include <Library/UefiBootServicesTableLib.h>
43 #include <Library/UefiRuntimeServicesTableLib.h>
44 #include <Library/DebugAgentLib.h>
45 #include <Library/HobLib.h>
46 #include <Library/LocalApicLib.h>
47 #include <Library/UefiCpuLib.h>
48 #include <Library/CpuExceptionHandlerLib.h>
49 #include <Library/ReportStatusCodeLib.h>
50 #include <Library/SmmCpuFeaturesLib.h>
51 #include <Library/PeCoffGetEntryPointLib.h>
53 #include <AcpiCpuData.h>
54 #include <CpuHotPlugData.h>
56 #include <Register/Cpuid.h>
57 #include <Register/Msr.h>
59 #include "CpuService.h"
60 #include "SmmProfile.h"
63 // MSRs required for configuration of SMM Code Access Check
65 #define EFI_MSR_SMM_MCA_CAP 0x17D
66 #define SMM_CODE_ACCESS_CHK_BIT BIT58
68 #define SMM_FEATURE_CONTROL_LOCK_BIT BIT0
69 #define SMM_CODE_CHK_EN_BIT BIT2
74 #define IA32_PG_P BIT0
75 #define IA32_PG_RW BIT1
76 #define IA32_PG_U BIT2
77 #define IA32_PG_WT BIT3
78 #define IA32_PG_CD BIT4
79 #define IA32_PG_A BIT5
80 #define IA32_PG_D BIT6
81 #define IA32_PG_PS BIT7
82 #define IA32_PG_PAT_2M BIT12
83 #define IA32_PG_PAT_4K IA32_PG_PS
84 #define IA32_PG_PMNT BIT62
85 #define IA32_PG_NX BIT63
87 #define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)
89 // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE
90 // X64 PAE PDPTE does not have such restriction
92 #define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)
94 #define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)
96 #define PAGING_4K_MASK 0xFFF
97 #define PAGING_2M_MASK 0x1FFFFF
98 #define PAGING_1G_MASK 0x3FFFFFFF
100 #define PAGING_PAE_INDEX_MASK 0x1FF
102 #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
103 #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
104 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
114 PAGE_ATTRIBUTE Attribute
;
117 } PAGE_ATTRIBUTE_TABLE
;
120 // Size of Task-State Segment defined in IA32 Manual
123 #define TSS_X64_IST1_OFFSET 36
124 #define TSS_IA32_CR3_OFFSET 28
125 #define TSS_IA32_ESP_OFFSET 56
132 #define PROTECT_MODE_CODE_SEGMENT 0x08
133 #define LONG_MODE_CODE_SEGMENT 0x38
136 // The size 0x20 must be bigger than
137 // the size of template code of SmmInit. Currently,
138 // the size of SmmInit requires the 0x16 Bytes buffer
141 #define BACK_BUF_SIZE 0x20
143 #define EXCEPTION_VECTOR_NUMBER 0x20
145 #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
147 typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS
;
148 #define ARRIVAL_EXCEPTION_BLOCKED 0x1
149 #define ARRIVAL_EXCEPTION_DELAYED 0x2
150 #define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4
153 // Private structure for the SMM CPU module that is stored in DXE Runtime memory
154 // Contains the SMM Configuration Protocols that is produced.
155 // Contains a mix of DXE and SMM contents. All the fields must be used properly.
157 #define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')
162 EFI_HANDLE SmmCpuHandle
;
164 EFI_PROCESSOR_INFORMATION
*ProcessorInfo
;
165 SMM_CPU_OPERATION
*Operation
;
166 UINTN
*CpuSaveStateSize
;
169 EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion
[1];
170 EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext
;
171 EFI_SMM_ENTRY_POINT SmmCoreEntry
;
173 EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration
;
174 } SMM_CPU_PRIVATE_DATA
;
176 extern SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
;
177 extern CPU_HOT_PLUG_DATA mCpuHotPlugData
;
178 extern UINTN mMaxNumberOfCpus
;
179 extern UINTN mNumberOfCpus
;
180 extern EFI_SMM_CPU_PROTOCOL mSmmCpu
;
183 /// The mode of the CPU at the time an SMI occurs
185 extern UINT8 mSmmSaveStateRegisterLma
;
189 // SMM CPU Protocol function prototypes.
193 Read information from the CPU save state.
195 @param This EFI_SMM_CPU_PROTOCOL instance
196 @param Width The number of bytes to read from the CPU save state.
197 @param Register Specifies the CPU register to read form the save state.
198 @param CpuIndex Specifies the zero-based index of the CPU save state
199 @param Buffer Upon return, this holds the CPU register value read from the save state.
201 @retval EFI_SUCCESS The register was read from Save State
202 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
203 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
209 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
211 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
217 Write data to the CPU save state.
219 @param This EFI_SMM_CPU_PROTOCOL instance
220 @param Width The number of bytes to read from the CPU save state.
221 @param Register Specifies the CPU register to write to the save state.
222 @param CpuIndex Specifies the zero-based index of the CPU save state
223 @param Buffer Upon entry, this holds the new CPU register value.
225 @retval EFI_SUCCESS The register was written from Save State
226 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
227 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
233 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
235 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
237 IN CONST VOID
*Buffer
241 Read a CPU Save State register on the target processor.
243 This function abstracts the differences that whether the CPU Save State register is in the
244 IA32 CPU Save State Map or X64 CPU Save State Map.
246 This function supports reading a CPU Save State register in SMBase relocation handler.
248 @param[in] CpuIndex Specifies the zero-based index of the CPU save state.
249 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
250 @param[in] Width The number of bytes to read from the CPU save state.
251 @param[out] Buffer Upon return, this holds the CPU register value read from the save state.
253 @retval EFI_SUCCESS The register was read from Save State.
254 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
255 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
260 ReadSaveStateRegister (
262 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
268 Write value to a CPU Save State register on the target processor.
270 This function abstracts the differences that whether the CPU Save State register is in the
271 IA32 CPU Save State Map or X64 CPU Save State Map.
273 This function supports writing a CPU Save State register in SMBase relocation handler.
275 @param[in] CpuIndex Specifies the zero-based index of the CPU save state.
276 @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
277 @param[in] Width The number of bytes to read from the CPU save state.
278 @param[in] Buffer Upon entry, this holds the new CPU register value.
280 @retval EFI_SUCCESS The register was written to Save State.
281 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
282 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.
287 WriteSaveStateRegister (
289 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
291 IN CONST VOID
*Buffer
303 extern IA32_FAR_ADDRESS gSmmJmpAddr
;
305 extern CONST UINT8 gcSmmInitTemplate
[];
306 extern CONST UINT16 gcSmmInitSize
;
307 extern UINT32 gSmmCr0
;
308 extern UINT32 gSmmCr3
;
309 extern UINT32 gSmmCr4
;
310 extern UINTN gSmmInitStack
;
313 Semaphore operation for all processor relocate SMMBase.
317 SmmRelocationSemaphoreComplete (
322 /// The type of SMM CPU Information
326 volatile EFI_AP_PROCEDURE Procedure
;
327 volatile VOID
*Parameter
;
328 volatile UINT32
*Run
;
329 volatile BOOLEAN
*Present
;
330 } SMM_CPU_DATA_BLOCK
;
333 SmmCpuSyncModeTradition
,
334 SmmCpuSyncModeRelaxedAp
,
340 // Pointer to an array. The array should be located immediately after this structure
341 // so that UC cache-ability can be set together.
343 SMM_CPU_DATA_BLOCK
*CpuData
;
344 volatile UINT32
*Counter
;
345 volatile UINT32 BspIndex
;
346 volatile BOOLEAN
*InsideSmm
;
347 volatile BOOLEAN
*AllCpusInSync
;
348 volatile SMM_CPU_SYNC_MODE EffectiveSyncMode
;
349 volatile BOOLEAN SwitchBsp
;
350 volatile BOOLEAN
*CandidateBsp
;
351 } SMM_DISPATCHER_MP_SYNC_DATA
;
353 #define MSR_SPIN_LOCK_INIT_NUM 15
360 #define SMM_PSD_OFFSET 0xfb00
363 UINT64 Signature
; // Offset 0x00
364 UINT16 Reserved1
; // Offset 0x08
365 UINT16 Reserved2
; // Offset 0x0A
366 UINT16 Reserved3
; // Offset 0x0C
367 UINT16 SmmCs
; // Offset 0x0E
368 UINT16 SmmDs
; // Offset 0x10
369 UINT16 SmmSs
; // Offset 0x12
370 UINT16 SmmOtherSegment
; // Offset 0x14
371 UINT16 Reserved4
; // Offset 0x16
372 UINT64 Reserved5
; // Offset 0x18
373 UINT64 Reserved6
; // Offset 0x20
374 UINT64 Reserved7
; // Offset 0x28
375 UINT64 SmmGdtPtr
; // Offset 0x30
376 UINT32 SmmGdtSize
; // Offset 0x38
377 UINT32 Reserved8
; // Offset 0x3C
378 UINT64 Reserved9
; // Offset 0x40
379 UINT64 Reserved10
; // Offset 0x48
380 UINT16 Reserved11
; // Offset 0x50
381 UINT16 Reserved12
; // Offset 0x52
382 UINT32 Reserved13
; // Offset 0x54
383 UINT64 MtrrBaseMaskPtr
; // Offset 0x58
384 } PROCESSOR_SMM_DESCRIPTOR
;
388 /// All global semaphores' pointer
391 volatile UINT32
*Counter
;
392 volatile BOOLEAN
*InsideSmm
;
393 volatile BOOLEAN
*AllCpusInSync
;
395 SPIN_LOCK
*CodeAccessCheckLock
;
396 SPIN_LOCK
*MemoryMappedLock
;
397 } SMM_CPU_SEMAPHORE_GLOBAL
;
400 /// All semaphores for each processor
404 volatile UINT32
*Run
;
405 volatile BOOLEAN
*Present
;
406 } SMM_CPU_SEMAPHORE_CPU
;
409 /// All MSRs semaphores' pointer and counter
413 UINTN AvailableCounter
;
414 } SMM_CPU_SEMAPHORE_MSR
;
417 /// All semaphores' information
420 SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal
;
421 SMM_CPU_SEMAPHORE_CPU SemaphoreCpu
;
422 SMM_CPU_SEMAPHORE_MSR SemaphoreMsr
;
423 } SMM_CPU_SEMAPHORES
;
425 extern IA32_DESCRIPTOR gcSmiGdtr
;
426 extern EFI_PHYSICAL_ADDRESS mGdtBuffer
;
427 extern UINTN mGdtBufferSize
;
428 extern IA32_DESCRIPTOR gcSmiIdtr
;
429 extern VOID
*gcSmiIdtrPtr
;
430 extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd
;
431 extern UINT64 gPhyMask
;
432 extern SMM_DISPATCHER_MP_SYNC_DATA
*mSmmMpSyncData
;
433 extern UINTN mSmmStackArrayBase
;
434 extern UINTN mSmmStackArrayEnd
;
435 extern UINTN mSmmStackSize
;
436 extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService
;
437 extern IA32_DESCRIPTOR gcSmiInitGdtr
;
438 extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores
;
439 extern UINTN mSemaphoreSize
;
440 extern SPIN_LOCK
*mPFLock
;
441 extern SPIN_LOCK
*mConfigSmmCodeAccessCheckLock
;
442 extern SPIN_LOCK
*mMemoryMappedLock
;
445 Create 4G PageTable in SMRAM.
447 @param[in] Is32BitPageTable Whether the page table is 32-bit PAE
448 @return PageTable Address
453 IN BOOLEAN Is32BitPageTable
458 Initialize global data for MP synchronization.
460 @param Stacks Base address of SMI stack buffer for all processors.
461 @param StackSize Stack size for each processor in SMM.
465 InitializeMpServiceData (
471 Initialize Timer for SMM AP Sync.
480 Start Timer for SMM AP Sync.
490 Check if the SMM AP Sync timer is timeout.
492 @param Timer The start timer from the begin.
502 Initialize IDT for SMM Stack Guard.
507 InitializeIDTSmmStackGuard (
512 Initialize Gdt for all processors.
514 @param[in] Cr3 CR3 value.
515 @param[out] GdtStepSize The step size for GDT table.
517 @return GdtBase for processor 0.
518 GdtBase for processor X is: GdtBase + (GdtStepSize * X)
523 OUT UINTN
*GdtStepSize
528 Register the SMM Foundation entry point.
530 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
531 @param SmmEntryPoint SMM Foundation EntryPoint
533 @retval EFI_SUCCESS Successfully to register SMM foundation entry point
539 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL
*This
,
540 IN EFI_SMM_ENTRY_POINT SmmEntryPoint
544 Create PageTable for SMM use.
546 @return PageTable Address
555 Schedule a procedure to run on the specified CPU.
557 @param Procedure The address of the procedure to run
558 @param CpuIndex Target CPU number
559 @param ProcArguments The parameter to pass to the procedure
561 @retval EFI_INVALID_PARAMETER CpuNumber not valid
562 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
563 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
564 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
565 @retval EFI_SUCCESS - The procedure has been successfully scheduled
571 IN EFI_AP_PROCEDURE Procedure
,
573 IN OUT VOID
*ProcArguments OPTIONAL
577 Schedule a procedure to run on the specified CPU in a blocking fashion.
579 @param Procedure The address of the procedure to run
580 @param CpuIndex Target CPU Index
581 @param ProcArguments The parameter to pass to the procedure
583 @retval EFI_INVALID_PARAMETER CpuNumber not valid
584 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
585 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
586 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
587 @retval EFI_SUCCESS The procedure has been successfully scheduled
592 SmmBlockingStartupThisAp (
593 IN EFI_AP_PROCEDURE Procedure
,
595 IN OUT VOID
*ProcArguments OPTIONAL
599 Initialize MP synchronization data.
604 InitializeMpSyncData (
610 Find out SMRAM information including SMRR base and SMRR size.
612 @param SmrrBase SMRR base
613 @param SmrrSize SMRR size
618 OUT UINT32
*SmrrBase
,
623 Relocate SmmBases for each processor.
625 Execute on first boot and all S3 resumes
635 Page Fault handler for SMM use.
637 @param InterruptType Defines the type of interrupt or exception that
638 occurred on the processor.This parameter is processor architecture specific.
639 @param SystemContext A pointer to the processor context when
640 the interrupt occurred on the processor.
645 IN EFI_EXCEPTION_TYPE InterruptType
,
646 IN EFI_SYSTEM_CONTEXT SystemContext
650 Perform the remaining tasks.
654 PerformRemainingTasks (
659 Perform the pre tasks.
668 Initialize MSR spin lock by MSR index.
670 @param MsrIndex MSR index value.
674 InitMsrSpinLockByIndex (
679 Hook return address of SMM Save State so that semaphore code
680 can be executed immediately after AP exits SMM to indicate to
681 the BSP that an AP has exited SMM after SMBASE relocation.
683 @param[in] CpuIndex The processor index.
684 @param[in] RebasedFlag A pointer to a flag that is set to TRUE
685 immediately after AP exits SMM.
691 IN
volatile BOOLEAN
*RebasedFlag
695 Configure SMM Code Access Check feature for all processors.
696 SMM Feature Control MSR will be locked after configuration.
699 ConfigSmmCodeAccessCheck (
704 Hook the code executed immediately after an RSM instruction on the currently
705 executing CPU. The mode of code executed immediately after RSM must be
706 detected, and the appropriate hook must be selected. Always clear the auto
707 HALT restart flag if it is set.
709 @param[in] CpuIndex The processor index for the currently
711 @param[in] CpuState Pointer to SMRAM Save State Map for the
712 currently executing CPU.
713 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
714 32-bit mode from 64-bit SMM.
715 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
718 @retval The value of the original instruction pointer before it was hooked.
725 SMRAM_SAVE_STATE_MAP
*CpuState
,
726 UINT64 NewInstructionPointer32
,
727 UINT64 NewInstructionPointer
731 Get the size of the SMI Handler in bytes.
733 @retval The size, in bytes, of the SMI Handler.
743 Install the SMI handler for the CPU specified by CpuIndex. This function
744 is called by the CPU that was elected as monarch during System Management
747 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
748 The value must be between 0 and the NumberOfCpus field
749 in the System Management System Table (SMST).
750 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
751 @param[in] SmiStack The stack to use when an SMI is processed by the
752 the CPU specified by CpuIndex.
753 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
754 processed by the CPU specified by CpuIndex.
755 @param[in] GdtBase The base address of the GDT to use when an SMI is
756 processed by the CPU specified by CpuIndex.
757 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
758 processed by the CPU specified by CpuIndex.
759 @param[in] IdtBase The base address of the IDT to use when an SMI is
760 processed by the CPU specified by CpuIndex.
761 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
762 processed by the CPU specified by CpuIndex.
763 @param[in] Cr3 The base address of the page tables to use when an SMI
764 is processed by the CPU specified by CpuIndex.
781 Search module name by input IP address and output it.
783 @param CallerIpAddress Caller instruction pointer.
788 IN UINTN CallerIpAddress
792 This function sets memory attribute according to MemoryAttributesTable.
795 SetMemMapAttributes (
800 This function sets memory attribute for page table.
803 SetPageTableAttributes (
808 Return page table base.
810 @return page table base.
818 This function sets the attributes for the memory region specified by BaseAddress and
819 Length from their current attributes to the attributes specified by Attributes.
821 @param[in] BaseAddress The physical address that is the start address of a memory region.
822 @param[in] Length The size in bytes of the memory region.
823 @param[in] Attributes The bit mask of attributes to set for the memory region.
824 @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.
826 @retval EFI_SUCCESS The attributes were set for the memory region.
827 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
828 BaseAddress and Length cannot be modified.
829 @retval EFI_INVALID_PARAMETER Length is zero.
830 Attributes specified an illegal combination of attributes that
831 cannot be set together.
832 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
833 the memory resource range.
834 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
835 resource range specified by BaseAddress and Length.
836 The bit mask of attributes is not support for the memory resource
837 range specified by BaseAddress and Length.
842 SmmSetMemoryAttributesEx (
843 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
845 IN UINT64 Attributes
,
846 OUT BOOLEAN
*IsSplitted OPTIONAL
850 This function clears the attributes for the memory region specified by BaseAddress and
851 Length from their current attributes to the attributes specified by Attributes.
853 @param[in] BaseAddress The physical address that is the start address of a memory region.
854 @param[in] Length The size in bytes of the memory region.
855 @param[in] Attributes The bit mask of attributes to clear for the memory region.
856 @param[out] IsSplitted TRUE means page table splitted. FALSE means page table not splitted.
858 @retval EFI_SUCCESS The attributes were cleared for the memory region.
859 @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
860 BaseAddress and Length cannot be modified.
861 @retval EFI_INVALID_PARAMETER Length is zero.
862 Attributes specified an illegal combination of attributes that
863 cannot be set together.
864 @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
865 the memory resource range.
866 @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
867 resource range specified by BaseAddress and Length.
868 The bit mask of attributes is not support for the memory resource
869 range specified by BaseAddress and Length.
874 SmmClearMemoryAttributesEx (
875 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
877 IN UINT64 Attributes
,
878 OUT BOOLEAN
*IsSplitted OPTIONAL
882 This API provides a way to allocate memory for page table.
884 This API can be called more once to allocate memory for page tables.
886 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
887 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
888 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
891 @param Pages The number of 4 KB pages to allocate.
893 @return A pointer to the allocated buffer or NULL if allocation fails.
897 AllocatePageTableMemory (
902 Allocate pages for code.
904 @param[in] Pages Number of pages to be allocated.
906 @return Allocated memory.
914 Allocate aligned pages for code.
916 @param[in] Pages Number of pages to be allocated.
917 @param[in] Alignment The requested alignment of the allocation.
918 Must be a power of two.
919 If Alignment is zero, then byte alignment is used.
921 @return Allocated memory.
924 AllocateAlignedCodePages (
931 // S3 related global variable and function prototype.
934 extern BOOLEAN mSmmS3Flag
;
937 Initialize SMM S3 resume state structure used during S3 Resume.
939 @param[in] Cr3 The base address of the page tables to use in SMM.
943 InitSmmS3ResumeState (
957 Restore SMM Configuration in S3 boot path.
961 RestoreSmmConfigurationInS3 (
966 Get ACPI S3 enable flag.
970 GetAcpiS3EnableFlag (
975 Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.
977 @param[in] ApHltLoopCode The address of the safe hlt-loop function.
978 @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.
979 @param[in] NumberToFinishAddress Address of Semaphore of APs finish count.
983 TransferApToSafeState (
984 IN UINTN ApHltLoopCode
,
986 IN UINTN NumberToFinishAddress