UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h

   1 /** @file
   2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
   3
   4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_PISMMCPUDXESMM_H_
  16 #define _CPU_PISMMCPUDXESMM_H_
  17
  18 #include <PiSmm.h>
  19
  20 #include <Protocol/MpService.h>
  21 #include <Protocol/SmmConfiguration.h>
  22 #include <Protocol/SmmCpu.h>
  23 #include <Protocol/SmmAccess2.h>
  24 #include <Protocol/SmmReadyToLock.h>
  25 #include <Protocol/SmmCpuService.h>
  26
  27 #include <Guid/AcpiS3Context.h>
  28
  29 #include <Library/BaseLib.h>
  30 #include <Library/IoLib.h>
  31 #include <Library/TimerLib.h>
  32 #include <Library/SynchronizationLib.h>
  33 #include <Library/DebugLib.h>
  34 #include <Library/BaseMemoryLib.h>
  35 #include <Library/PcdLib.h>
  36 #include <Library/CacheMaintenanceLib.h>
  37 #include <Library/MtrrLib.h>
  38 #include <Library/SmmCpuPlatformHookLib.h>
  39 #include <Library/SmmServicesTableLib.h>
  40 #include <Library/MemoryAllocationLib.h>
  41 #include <Library/UefiBootServicesTableLib.h>
  42 #include <Library/UefiRuntimeServicesTableLib.h>
  43 #include <Library/DebugAgentLib.h>
  44 #include <Library/HobLib.h>
  45 #include <Library/LocalApicLib.h>
  46 #include <Library/UefiCpuLib.h>
  47 #include <Library/CpuExceptionHandlerLib.h>
  48 #include <Library/ReportStatusCodeLib.h>
  49 #include <Library/SmmCpuFeaturesLib.h>
  50 #include <Library/PeCoffGetEntryPointLib.h>
  51
  52 #include <AcpiCpuData.h>
  53 #include <CpuHotPlugData.h>
  54
  55 #include <Register/Cpuid.h>
  56 #include <Register/Msr.h>
  57
  58 #include "CpuService.h"
  59 #include "SmmProfile.h"
  60
  61 //
  62 // MSRs required for configuration of SMM Code Access Check
  63 //
  64 #define EFI_MSR_SMM_MCA_CAP                    0x17D
  65 #define  SMM_CODE_ACCESS_CHK_BIT               BIT58
  66
  67 #define  SMM_FEATURE_CONTROL_LOCK_BIT          BIT0
  68 #define  SMM_CODE_CHK_EN_BIT                   BIT2
  69
  70 ///
  71 /// Page Table Entry
  72 ///
  73 #define IA32_PG_P                   BIT0
  74 #define IA32_PG_RW                  BIT1
  75 #define IA32_PG_U                   BIT2
  76 #define IA32_PG_WT                  BIT3
  77 #define IA32_PG_CD                  BIT4
  78 #define IA32_PG_A                   BIT5
  79 #define IA32_PG_D                   BIT6
  80 #define IA32_PG_PS                  BIT7
  81 #define IA32_PG_PAT_2M              BIT12
  82 #define IA32_PG_PAT_4K              IA32_PG_PS
  83 #define IA32_PG_PMNT                BIT62
  84 #define IA32_PG_NX                  BIT63
  85
  86 #define PAGE_ATTRIBUTE_BITS         (IA32_PG_RW | IA32_PG_P)
  87 //
  88 // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE
  89 // X64 PAE PDPTE does not have such restriction
  90 //
  91 #define IA32_PAE_PDPTE_ATTRIBUTE_BITS    (IA32_PG_P)
  92
  93 //
  94 // Size of Task-State Segment defined in IA32 Manual
  95 //
  96 #define TSS_SIZE              104
  97 #define TSS_X64_IST1_OFFSET   36
  98 #define TSS_IA32_CR3_OFFSET   28
  99 #define TSS_IA32_ESP_OFFSET   56
 100
 101 //
 102 // Code select value
 103 //
 104 #define PROTECT_MODE_CODE_SEGMENT          0x08
 105 #define LONG_MODE_CODE_SEGMENT             0x38
 106
 107 //
 108 // The size 0x20 must be bigger than
 109 // the size of template code of SmmInit. Currently,
 110 // the size of SmmInit requires the 0x16 Bytes buffer
 111 // at least.
 112 //
 113 #define BACK_BUF_SIZE  0x20
 114
 115 #define EXCEPTION_VECTOR_NUMBER     0x20
 116
 117 #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
 118
 119 typedef UINT32                              SMM_CPU_ARRIVAL_EXCEPTIONS;
 120 #define ARRIVAL_EXCEPTION_BLOCKED           0x1
 121 #define ARRIVAL_EXCEPTION_DELAYED           0x2
 122 #define ARRIVAL_EXCEPTION_SMI_DISABLED      0x4
 123
 124 //
 125 // Private structure for the SMM CPU module that is stored in DXE Runtime memory
 126 // Contains the SMM Configuration Protocols that is produced.
 127 // Contains a mix of DXE and SMM contents.  All the fields must be used properly.
 128 //
 129 #define SMM_CPU_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('s', 'c', 'p', 'u')
 130
 131 typedef struct {
 132   UINTN                           Signature;
 133
 134   EFI_HANDLE                      SmmCpuHandle;
 135
 136   EFI_PROCESSOR_INFORMATION       *ProcessorInfo;
 137   SMM_CPU_OPERATION               *Operation;
 138   UINTN                           *CpuSaveStateSize;
 139   VOID                            **CpuSaveState;
 140
 141   EFI_SMM_RESERVED_SMRAM_REGION   SmmReservedSmramRegion[1];
 142   EFI_SMM_ENTRY_CONTEXT           SmmCoreEntryContext;
 143   EFI_SMM_ENTRY_POINT             SmmCoreEntry;
 144
 145   EFI_SMM_CONFIGURATION_PROTOCOL  SmmConfiguration;
 146 } SMM_CPU_PRIVATE_DATA;
 147
 148 extern SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate;
 149 extern CPU_HOT_PLUG_DATA      mCpuHotPlugData;
 150 extern UINTN                  mMaxNumberOfCpus;
 151 extern UINTN                  mNumberOfCpus;
 152 extern BOOLEAN                mRestoreSmmConfigurationInS3;
 153 extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;
 154
 155 ///
 156 /// The mode of the CPU at the time an SMI occurs
 157 ///
 158 extern UINT8  mSmmSaveStateRegisterLma;
 159
 160
 161 //
 162 // SMM CPU Protocol function prototypes.
 163 //
 164
 165 /**
 166   Read information from the CPU save state.
 167
 168   @param  This      EFI_SMM_CPU_PROTOCOL instance
 169   @param  Width     The number of bytes to read from the CPU save state.
 170   @param  Register  Specifies the CPU register to read form the save state.
 171   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 172   @param  Buffer    Upon return, this holds the CPU register value read from the save state.
 173
 174   @retval EFI_SUCCESS   The register was read from Save State
 175   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 176   @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.
 177
 178 **/
 179 EFI_STATUS
 180 EFIAPI
 181 SmmReadSaveState (
 182   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 183   IN UINTN                              Width,
 184   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 185   IN UINTN                              CpuIndex,
 186   OUT VOID                              *Buffer
 187   );
 188
 189 /**
 190   Write data to the CPU save state.
 191
 192   @param  This      EFI_SMM_CPU_PROTOCOL instance
 193   @param  Width     The number of bytes to read from the CPU save state.
 194   @param  Register  Specifies the CPU register to write to the save state.
 195   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 196   @param  Buffer    Upon entry, this holds the new CPU register value.
 197
 198   @retval EFI_SUCCESS   The register was written from Save State
 199   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 200   @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct
 201
 202 **/
 203 EFI_STATUS
 204 EFIAPI
 205 SmmWriteSaveState (
 206   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 207   IN UINTN                              Width,
 208   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 209   IN UINTN                              CpuIndex,
 210   IN CONST VOID                         *Buffer
 211   );
 212
 213 /**
 214 Read a CPU Save State register on the target processor.
 215
 216 This function abstracts the differences that whether the CPU Save State register is in the
 217 IA32 CPU Save State Map or X64 CPU Save State Map.
 218
 219 This function supports reading a CPU Save State register in SMBase relocation handler.
 220
 221 @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
 222 @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 223 @param[in]  Width          The number of bytes to read from the CPU save state.
 224 @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
 225
 226 @retval EFI_SUCCESS           The register was read from Save State.
 227 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 228 @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
 229
 230 **/
 231 EFI_STATUS
 232 EFIAPI
 233 ReadSaveStateRegister (
 234   IN UINTN                        CpuIndex,
 235   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 236   IN UINTN                        Width,
 237   OUT VOID                        *Buffer
 238   );
 239
 240 /**
 241 Write value to a CPU Save State register on the target processor.
 242
 243 This function abstracts the differences that whether the CPU Save State register is in the
 244 IA32 CPU Save State Map or X64 CPU Save State Map.
 245
 246 This function supports writing a CPU Save State register in SMBase relocation handler.
 247
 248 @param[in] CpuIndex       Specifies the zero-based index of the CPU save state.
 249 @param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 250 @param[in] Width          The number of bytes to read from the CPU save state.
 251 @param[in] Buffer         Upon entry, this holds the new CPU register value.
 252
 253 @retval EFI_SUCCESS           The register was written to Save State.
 254 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 255 @retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.
 256
 257 **/
 258 EFI_STATUS
 259 EFIAPI
 260 WriteSaveStateRegister (
 261   IN UINTN                        CpuIndex,
 262   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 263   IN UINTN                        Width,
 264   IN CONST VOID                   *Buffer
 265   );
 266
 267 //
 268 //
 269 //
 270 typedef struct {
 271   UINT32                            Offset;
 272   UINT16                            Segment;
 273   UINT16                            Reserved;
 274 } IA32_FAR_ADDRESS;
 275
 276 extern IA32_FAR_ADDRESS             gSmmJmpAddr;
 277
 278 extern CONST UINT8                  gcSmmInitTemplate[];
 279 extern CONST UINT16                 gcSmmInitSize;
 280 extern UINT32                       gSmmCr0;
 281 extern UINT32                       gSmmCr3;
 282 extern UINT32                       gSmmCr4;
 283 extern UINTN                        gSmmInitStack;
 284
 285 /**
 286   Semaphore operation for all processor relocate SMMBase.
 287 **/
 288 VOID
 289 EFIAPI
 290 SmmRelocationSemaphoreComplete (
 291   VOID
 292   );
 293
 294 ///
 295 /// The type of SMM CPU Information
 296 ///
 297 typedef struct {
 298   SPIN_LOCK                         *Busy;
 299   volatile EFI_AP_PROCEDURE         Procedure;
 300   volatile VOID                     *Parameter;
 301   volatile UINT32                   *Run;
 302   volatile BOOLEAN                  *Present;
 303 } SMM_CPU_DATA_BLOCK;
 304
 305 typedef enum {
 306   SmmCpuSyncModeTradition,
 307   SmmCpuSyncModeRelaxedAp,
 308   SmmCpuSyncModeMax
 309 } SMM_CPU_SYNC_MODE;
 310
 311 typedef struct {
 312   //
 313   // Pointer to an array. The array should be located immediately after this structure
 314   // so that UC cache-ability can be set together.
 315   //
 316   SMM_CPU_DATA_BLOCK            *CpuData;
 317   volatile UINT32               *Counter;
 318   volatile UINT32               BspIndex;
 319   volatile BOOLEAN              *InsideSmm;
 320   volatile BOOLEAN              *AllCpusInSync;
 321   volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;
 322   volatile BOOLEAN              SwitchBsp;
 323   volatile BOOLEAN              *CandidateBsp;
 324 } SMM_DISPATCHER_MP_SYNC_DATA;
 325
 326 #define MSR_SPIN_LOCK_INIT_NUM 15
 327
 328 typedef struct {
 329   SPIN_LOCK    SpinLock;
 330   UINT32       MsrIndex;
 331 } MP_MSR_LOCK;
 332
 333 #define SMM_PSD_OFFSET              0xfb00
 334
 335 typedef struct {
 336   UINT64                            Signature;              // Offset 0x00
 337   UINT16                            Reserved1;              // Offset 0x08
 338   UINT16                            Reserved2;              // Offset 0x0A
 339   UINT16                            Reserved3;              // Offset 0x0C
 340   UINT16                            SmmCs;                  // Offset 0x0E
 341   UINT16                            SmmDs;                  // Offset 0x10
 342   UINT16                            SmmSs;                  // Offset 0x12
 343   UINT16                            SmmOtherSegment;        // Offset 0x14
 344   UINT16                            Reserved4;              // Offset 0x16
 345   UINT64                            Reserved5;              // Offset 0x18
 346   UINT64                            Reserved6;              // Offset 0x20
 347   UINT64                            Reserved7;              // Offset 0x28
 348   UINT64                            SmmGdtPtr;              // Offset 0x30
 349   UINT32                            SmmGdtSize;             // Offset 0x38
 350   UINT32                            Reserved8;              // Offset 0x3C
 351   UINT64                            Reserved9;              // Offset 0x40
 352   UINT64                            Reserved10;             // Offset 0x48
 353   UINT16                            Reserved11;             // Offset 0x50
 354   UINT16                            Reserved12;             // Offset 0x52
 355   UINT32                            Reserved13;             // Offset 0x54
 356   UINT64                            MtrrBaseMaskPtr;        // Offset 0x58
 357 } PROCESSOR_SMM_DESCRIPTOR;
 358
 359
 360 ///
 361 /// All global semaphores' pointer
 362 ///
 363 typedef struct {
 364   volatile UINT32      *Counter;
 365   volatile BOOLEAN     *InsideSmm;
 366   volatile BOOLEAN     *AllCpusInSync;
 367   SPIN_LOCK            *PFLock;
 368   SPIN_LOCK            *CodeAccessCheckLock;
 369 } SMM_CPU_SEMAPHORE_GLOBAL;
 370
 371 ///
 372 /// All semaphores for each processor
 373 ///
 374 typedef struct {
 375   SPIN_LOCK                         *Busy;
 376   volatile UINT32                   *Run;
 377   volatile BOOLEAN                  *Present;
 378 } SMM_CPU_SEMAPHORE_CPU;
 379
 380 ///
 381 /// All MSRs semaphores' pointer and counter
 382 ///
 383 typedef struct {
 384   SPIN_LOCK            *Msr;
 385   UINTN                AvailableCounter;
 386 } SMM_CPU_SEMAPHORE_MSR;
 387
 388 ///
 389 /// All semaphores' information
 390 ///
 391 typedef struct {
 392   SMM_CPU_SEMAPHORE_GLOBAL          SemaphoreGlobal;
 393   SMM_CPU_SEMAPHORE_CPU             SemaphoreCpu;
 394   SMM_CPU_SEMAPHORE_MSR             SemaphoreMsr;
 395 } SMM_CPU_SEMAPHORES;
 396
 397 extern IA32_DESCRIPTOR                     gcSmiGdtr;
 398 extern IA32_DESCRIPTOR                     gcSmiIdtr;
 399 extern VOID                                *gcSmiIdtrPtr;
 400 extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;
 401 extern UINT64                              gPhyMask;
 402 extern ACPI_CPU_DATA                       mAcpiCpuData;
 403 extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;
 404 extern VOID                                *mGdtForAp;
 405 extern VOID                                *mIdtForAp;
 406 extern VOID                                *mMachineCheckHandlerForAp;
 407 extern UINTN                               mSmmStackArrayBase;
 408 extern UINTN                               mSmmStackArrayEnd;
 409 extern UINTN                               mSmmStackSize;
 410 extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;
 411 extern IA32_DESCRIPTOR                     gcSmiInitGdtr;
 412 extern SPIN_LOCK                           *mPFLock;
 413 extern SPIN_LOCK                           *mConfigSmmCodeAccessCheckLock;
 414
 415 /**
 416   Create 4G PageTable in SMRAM.
 417
 418   @param          ExtraPages       Additional page numbers besides for 4G memory
 419   @param          Is32BitPageTable Whether the page table is 32-bit PAE
 420   @return         PageTable Address
 421
 422 **/
 423 UINT32
 424 Gen4GPageTable (
 425   IN      UINTN                     ExtraPages,
 426   IN      BOOLEAN                   Is32BitPageTable
 427   );
 428
 429
 430 /**
 431   Initialize global data for MP synchronization.
 432
 433   @param Stacks       Base address of SMI stack buffer for all processors.
 434   @param StackSize    Stack size for each processor in SMM.
 435
 436 **/
 437 UINT32
 438 InitializeMpServiceData (
 439   IN VOID        *Stacks,
 440   IN UINTN       StackSize
 441   );
 442
 443 /**
 444   Initialize Timer for SMM AP Sync.
 445
 446 **/
 447 VOID
 448 InitializeSmmTimer (
 449   VOID
 450   );
 451
 452 /**
 453   Start Timer for SMM AP Sync.
 454
 455 **/
 456 UINT64
 457 EFIAPI
 458 StartSyncTimer (
 459   VOID
 460   );
 461
 462 /**
 463   Check if the SMM AP Sync timer is timeout.
 464
 465   @param Timer  The start timer from the begin.
 466
 467 **/
 468 BOOLEAN
 469 EFIAPI
 470 IsSyncTimerTimeout (
 471   IN      UINT64                    Timer
 472   );
 473
 474 /**
 475   Initialize IDT for SMM Stack Guard.
 476
 477 **/
 478 VOID
 479 EFIAPI
 480 InitializeIDTSmmStackGuard (
 481   VOID
 482   );
 483
 484 /**
 485   Initialize Gdt for all processors.
 486
 487   @param[in]   Cr3          CR3 value.
 488   @param[out]  GdtStepSize  The step size for GDT table.
 489
 490   @return GdtBase for processor 0.
 491           GdtBase for processor X is: GdtBase + (GdtStepSize * X)
 492 **/
 493 VOID *
 494 InitGdt (
 495   IN  UINTN  Cr3,
 496   OUT UINTN  *GdtStepSize
 497   );
 498
 499 /**
 500
 501   Register the SMM Foundation entry point.
 502
 503   @param          This              Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
 504   @param          SmmEntryPoint     SMM Foundation EntryPoint
 505
 506   @retval         EFI_SUCCESS       Successfully to register SMM foundation entry point
 507
 508 **/
 509 EFI_STATUS
 510 EFIAPI
 511 RegisterSmmEntry (
 512   IN CONST EFI_SMM_CONFIGURATION_PROTOCOL  *This,
 513   IN EFI_SMM_ENTRY_POINT                   SmmEntryPoint
 514   );
 515
 516 /**
 517   Create PageTable for SMM use.
 518
 519   @return     PageTable Address
 520
 521 **/
 522 UINT32
 523 SmmInitPageTable (
 524   VOID
 525   );
 526
 527 /**
 528   Schedule a procedure to run on the specified CPU.
 529
 530   @param   Procedure        The address of the procedure to run
 531   @param   CpuIndex         Target CPU number
 532   @param   ProcArguments    The parameter to pass to the procedure
 533
 534   @retval   EFI_INVALID_PARAMETER    CpuNumber not valid
 535   @retval   EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 536   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 537   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 538   @retval   EFI_SUCCESS - The procedure has been successfully scheduled
 539
 540 **/
 541 EFI_STATUS
 542 EFIAPI
 543 SmmStartupThisAp (
 544   IN      EFI_AP_PROCEDURE          Procedure,
 545   IN      UINTN                     CpuIndex,
 546   IN OUT  VOID                      *ProcArguments OPTIONAL
 547   );
 548
 549 /**
 550   Schedule a procedure to run on the specified CPU in a blocking fashion.
 551
 552   @param  Procedure                The address of the procedure to run
 553   @param  CpuIndex                 Target CPU Index
 554   @param  ProcArguments            The parameter to pass to the procedure
 555
 556   @retval EFI_INVALID_PARAMETER    CpuNumber not valid
 557   @retval EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 558   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 559   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 560   @retval EFI_SUCCESS              The procedure has been successfully scheduled
 561
 562 **/
 563 EFI_STATUS
 564 EFIAPI
 565 SmmBlockingStartupThisAp (
 566   IN      EFI_AP_PROCEDURE          Procedure,
 567   IN      UINTN                     CpuIndex,
 568   IN OUT  VOID                      *ProcArguments OPTIONAL
 569   );
 570
 571 /**
 572   Initialize MP synchronization data.
 573
 574 **/
 575 VOID
 576 EFIAPI
 577 InitializeMpSyncData (
 578   VOID
 579   );
 580
 581 /**
 582
 583   Find out SMRAM information including SMRR base and SMRR size.
 584
 585   @param          SmrrBase          SMRR base
 586   @param          SmrrSize          SMRR size
 587
 588 **/
 589 VOID
 590 FindSmramInfo (
 591   OUT UINT32   *SmrrBase,
 592   OUT UINT32   *SmrrSize
 593   );
 594
 595 /**
 596   The function is invoked before SMBASE relocation in S3 path to restores CPU status.
 597
 598   The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
 599   and restores MTRRs for both BSP and APs.
 600
 601 **/
 602 VOID
 603 EarlyInitializeCpu (
 604   VOID
 605   );
 606
 607 /**
 608   The function is invoked after SMBASE relocation in S3 path to restores CPU status.
 609
 610   The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
 611   data saved by normal boot path for both BSP and APs.
 612
 613 **/
 614 VOID
 615 InitializeCpu (
 616   VOID
 617   );
 618
 619 /**
 620   Page Fault handler for SMM use.
 621
 622   @param  InterruptType    Defines the type of interrupt or exception that
 623                            occurred on the processor.This parameter is processor architecture specific.
 624   @param  SystemContext    A pointer to the processor context when
 625                            the interrupt occurred on the processor.
 626 **/
 627 VOID
 628 EFIAPI
 629 SmiPFHandler (
 630     IN EFI_EXCEPTION_TYPE   InterruptType,
 631     IN EFI_SYSTEM_CONTEXT   SystemContext
 632   );
 633
 634 /**
 635   Perform the remaining tasks.
 636
 637 **/
 638 VOID
 639 PerformRemainingTasks (
 640   VOID
 641   );
 642
 643 /**
 644   Perform the pre tasks.
 645
 646 **/
 647 VOID
 648 PerformPreTasks (
 649   VOID
 650   );
 651
 652 /**
 653   Initialize MSR spin lock by MSR index.
 654
 655   @param  MsrIndex       MSR index value.
 656
 657 **/
 658 VOID
 659 InitMsrSpinLockByIndex (
 660   IN UINT32      MsrIndex
 661   );
 662
 663 /**
 664   Hook return address of SMM Save State so that semaphore code
 665   can be executed immediately after AP exits SMM to indicate to
 666   the BSP that an AP has exited SMM after SMBASE relocation.
 667
 668   @param[in] CpuIndex     The processor index.
 669   @param[in] RebasedFlag  A pointer to a flag that is set to TRUE
 670                           immediately after AP exits SMM.
 671
 672 **/
 673 VOID
 674 SemaphoreHook (
 675   IN UINTN             CpuIndex,
 676   IN volatile BOOLEAN  *RebasedFlag
 677   );
 678
 679 /**
 680 Configure SMM Code Access Check feature for all processors.
 681 SMM Feature Control MSR will be locked after configuration.
 682 **/
 683 VOID
 684 ConfigSmmCodeAccessCheck (
 685   VOID
 686   );
 687
 688 /**
 689   Hook the code executed immediately after an RSM instruction on the currently
 690   executing CPU.  The mode of code executed immediately after RSM must be
 691   detected, and the appropriate hook must be selected.  Always clear the auto
 692   HALT restart flag if it is set.
 693
 694   @param[in] CpuIndex                 The processor index for the currently
 695                                       executing CPU.
 696   @param[in] CpuState                 Pointer to SMRAM Save State Map for the
 697                                       currently executing CPU.
 698   @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
 699                                       32-bit mode from 64-bit SMM.
 700   @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
 701                                       same mode as SMM.
 702
 703   @retval The value of the original instruction pointer before it was hooked.
 704
 705 **/
 706 UINT64
 707 EFIAPI
 708 HookReturnFromSmm (
 709   IN UINTN              CpuIndex,
 710   SMRAM_SAVE_STATE_MAP  *CpuState,
 711   UINT64                NewInstructionPointer32,
 712   UINT64                NewInstructionPointer
 713   );
 714
 715 /**
 716   Get the size of the SMI Handler in bytes.
 717
 718   @retval The size, in bytes, of the SMI Handler.
 719
 720 **/
 721 UINTN
 722 EFIAPI
 723 GetSmiHandlerSize (
 724   VOID
 725   );
 726
 727 /**
 728   Install the SMI handler for the CPU specified by CpuIndex.  This function
 729   is called by the CPU that was elected as monarch during System Management
 730   Mode initialization.
 731
 732   @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
 733                         The value must be between 0 and the NumberOfCpus field
 734                         in the System Management System Table (SMST).
 735   @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
 736   @param[in] SmiStack   The stack to use when an SMI is processed by the
 737                         the CPU specified by CpuIndex.
 738   @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
 739                         processed by the CPU specified by CpuIndex.
 740   @param[in] GdtBase    The base address of the GDT to use when an SMI is
 741                         processed by the CPU specified by CpuIndex.
 742   @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
 743                         processed by the CPU specified by CpuIndex.
 744   @param[in] IdtBase    The base address of the IDT to use when an SMI is
 745                         processed by the CPU specified by CpuIndex.
 746   @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
 747                         processed by the CPU specified by CpuIndex.
 748   @param[in] Cr3        The base address of the page tables to use when an SMI
 749                         is processed by the CPU specified by CpuIndex.
 750 **/
 751 VOID
 752 EFIAPI
 753 InstallSmiHandler (
 754   IN UINTN   CpuIndex,
 755   IN UINT32  SmBase,
 756   IN VOID    *SmiStack,
 757   IN UINTN   StackSize,
 758   IN UINTN   GdtBase,
 759   IN UINTN   GdtSize,
 760   IN UINTN   IdtBase,
 761   IN UINTN   IdtSize,
 762   IN UINT32  Cr3
 763   );
 764
 765 /**
 766   Search module name by input IP address and output it.
 767
 768   @param CallerIpAddress   Caller instruction pointer.
 769
 770 **/
 771 VOID
 772 DumpModuleInfoByIp (
 773   IN  UINTN              CallerIpAddress
 774   );
 775
 776 /**
 777   This API provides a way to allocate memory for page table.
 778
 779   This API can be called more once to allocate memory for page tables.
 780
 781   Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
 782   allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
 783   is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
 784   returned.
 785
 786   @param  Pages                 The number of 4 KB pages to allocate.
 787
 788   @return A pointer to the allocated buffer or NULL if allocation fails.
 789
 790 **/
 791 VOID *
 792 AllocatePageTableMemory (
 793   IN UINTN           Pages
 794   );
 795
 796 #endif