UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h

   1 /** @file
   2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
   3
   4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_PISMMCPUDXESMM_H_
  16 #define _CPU_PISMMCPUDXESMM_H_
  17
  18 #include <PiSmm.h>
  19
  20 #include <Protocol/MpService.h>
  21 #include <Protocol/SmmConfiguration.h>
  22 #include <Protocol/SmmCpu.h>
  23 #include <Protocol/SmmAccess2.h>
  24 #include <Protocol/SmmReadyToLock.h>
  25 #include <Protocol/SmmCpuService.h>
  26
  27 #include <Guid/AcpiS3Context.h>
  28
  29 #include <Library/BaseLib.h>
  30 #include <Library/IoLib.h>
  31 #include <Library/TimerLib.h>
  32 #include <Library/SynchronizationLib.h>
  33 #include <Library/DebugLib.h>
  34 #include <Library/BaseMemoryLib.h>
  35 #include <Library/PcdLib.h>
  36 #include <Library/CacheMaintenanceLib.h>
  37 #include <Library/MtrrLib.h>
  38 #include <Library/SmmCpuPlatformHookLib.h>
  39 #include <Library/SmmServicesTableLib.h>
  40 #include <Library/MemoryAllocationLib.h>
  41 #include <Library/UefiBootServicesTableLib.h>
  42 #include <Library/UefiRuntimeServicesTableLib.h>
  43 #include <Library/DebugAgentLib.h>
  44 #include <Library/HobLib.h>
  45 #include <Library/LocalApicLib.h>
  46 #include <Library/UefiCpuLib.h>
  47 #include <Library/CpuExceptionHandlerLib.h>
  48 #include <Library/ReportStatusCodeLib.h>
  49 #include <Library/SmmCpuFeaturesLib.h>
  50 #include <Library/PeCoffGetEntryPointLib.h>
  51
  52 #include <AcpiCpuData.h>
  53 #include <CpuHotPlugData.h>
  54
  55 #include <Register/Cpuid.h>
  56 #include <Register/Msr.h>
  57
  58 #include "CpuService.h"
  59 #include "SmmProfile.h"
  60
  61 //
  62 // MSRs required for configuration of SMM Code Access Check
  63 //
  64 #define EFI_MSR_SMM_MCA_CAP                    0x17D
  65 #define  SMM_CODE_ACCESS_CHK_BIT               BIT58
  66
  67 #define  SMM_FEATURE_CONTROL_LOCK_BIT          BIT0
  68 #define  SMM_CODE_CHK_EN_BIT                   BIT2
  69
  70 ///
  71 /// Page Table Entry
  72 ///
  73 #define IA32_PG_P                   BIT0
  74 #define IA32_PG_RW                  BIT1
  75 #define IA32_PG_U                   BIT2
  76 #define IA32_PG_WT                  BIT3
  77 #define IA32_PG_CD                  BIT4
  78 #define IA32_PG_A                   BIT5
  79 #define IA32_PG_D                   BIT6
  80 #define IA32_PG_PS                  BIT7
  81 #define IA32_PG_PAT_2M              BIT12
  82 #define IA32_PG_PAT_4K              IA32_PG_PS
  83 #define IA32_PG_PMNT                BIT62
  84 #define IA32_PG_NX                  BIT63
  85
  86 #define PAGE_ATTRIBUTE_BITS         (IA32_PG_RW | IA32_PG_P)
  87 //
  88 // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE
  89 // X64 PAE PDPTE does not have such restriction
  90 //
  91 #define IA32_PAE_PDPTE_ATTRIBUTE_BITS    (IA32_PG_P)
  92
  93 //
  94 // Size of Task-State Segment defined in IA32 Manual
  95 //
  96 #define TSS_SIZE              104
  97 #define TSS_X64_IST1_OFFSET   36
  98 #define TSS_IA32_CR3_OFFSET   28
  99 #define TSS_IA32_ESP_OFFSET   56
 100
 101 //
 102 // Code select value
 103 //
 104 #define PROTECT_MODE_CODE_SEGMENT          0x08
 105 #define LONG_MODE_CODE_SEGMENT             0x38
 106
 107 //
 108 // The size 0x20 must be bigger than
 109 // the size of template code of SmmInit. Currently,
 110 // the size of SmmInit requires the 0x16 Bytes buffer
 111 // at least.
 112 //
 113 #define BACK_BUF_SIZE  0x20
 114
 115 #define EXCEPTION_VECTOR_NUMBER     0x20
 116
 117 #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
 118
 119 typedef UINT32                              SMM_CPU_ARRIVAL_EXCEPTIONS;
 120 #define ARRIVAL_EXCEPTION_BLOCKED           0x1
 121 #define ARRIVAL_EXCEPTION_DELAYED           0x2
 122 #define ARRIVAL_EXCEPTION_SMI_DISABLED      0x4
 123
 124 //
 125 // Private structure for the SMM CPU module that is stored in DXE Runtime memory
 126 // Contains the SMM Configuration Protocols that is produced.
 127 // Contains a mix of DXE and SMM contents.  All the fields must be used properly.
 128 //
 129 #define SMM_CPU_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('s', 'c', 'p', 'u')
 130
 131 typedef struct {
 132   UINTN                           Signature;
 133
 134   EFI_HANDLE                      SmmCpuHandle;
 135
 136   EFI_PROCESSOR_INFORMATION       *ProcessorInfo;
 137   SMM_CPU_OPERATION               *Operation;
 138   UINTN                           *CpuSaveStateSize;
 139   VOID                            **CpuSaveState;
 140
 141   EFI_SMM_RESERVED_SMRAM_REGION   SmmReservedSmramRegion[1];
 142   EFI_SMM_ENTRY_CONTEXT           SmmCoreEntryContext;
 143   EFI_SMM_ENTRY_POINT             SmmCoreEntry;
 144
 145   EFI_SMM_CONFIGURATION_PROTOCOL  SmmConfiguration;
 146 } SMM_CPU_PRIVATE_DATA;
 147
 148 extern SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate;
 149 extern CPU_HOT_PLUG_DATA      mCpuHotPlugData;
 150 extern UINTN                  mMaxNumberOfCpus;
 151 extern UINTN                  mNumberOfCpus;
 152 extern BOOLEAN                mRestoreSmmConfigurationInS3;
 153 extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;
 154
 155 ///
 156 /// The mode of the CPU at the time an SMI occurs
 157 ///
 158 extern UINT8  mSmmSaveStateRegisterLma;
 159
 160
 161 //
 162 // SMM CPU Protocol function prototypes.
 163 //
 164
 165 /**
 166   Read information from the CPU save state.
 167
 168   @param  This      EFI_SMM_CPU_PROTOCOL instance
 169   @param  Width     The number of bytes to read from the CPU save state.
 170   @param  Register  Specifies the CPU register to read form the save state.
 171   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 172   @param  Buffer    Upon return, this holds the CPU register value read from the save state.
 173
 174   @retval EFI_SUCCESS   The register was read from Save State
 175   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 176   @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.
 177
 178 **/
 179 EFI_STATUS
 180 EFIAPI
 181 SmmReadSaveState (
 182   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 183   IN UINTN                              Width,
 184   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 185   IN UINTN                              CpuIndex,
 186   OUT VOID                              *Buffer
 187   );
 188
 189 /**
 190   Write data to the CPU save state.
 191
 192   @param  This      EFI_SMM_CPU_PROTOCOL instance
 193   @param  Width     The number of bytes to read from the CPU save state.
 194   @param  Register  Specifies the CPU register to write to the save state.
 195   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 196   @param  Buffer    Upon entry, this holds the new CPU register value.
 197
 198   @retval EFI_SUCCESS   The register was written from Save State
 199   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 200   @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct
 201
 202 **/
 203 EFI_STATUS
 204 EFIAPI
 205 SmmWriteSaveState (
 206   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 207   IN UINTN                              Width,
 208   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 209   IN UINTN                              CpuIndex,
 210   IN CONST VOID                         *Buffer
 211   );
 212
 213 /**
 214 Read a CPU Save State register on the target processor.
 215
 216 This function abstracts the differences that whether the CPU Save State register is in the
 217 IA32 CPU Save State Map or X64 CPU Save State Map.
 218
 219 This function supports reading a CPU Save State register in SMBase relocation handler.
 220
 221 @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
 222 @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 223 @param[in]  Width          The number of bytes to read from the CPU save state.
 224 @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
 225
 226 @retval EFI_SUCCESS           The register was read from Save State.
 227 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 228 @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
 229
 230 **/
 231 EFI_STATUS
 232 EFIAPI
 233 ReadSaveStateRegister (
 234   IN UINTN                        CpuIndex,
 235   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 236   IN UINTN                        Width,
 237   OUT VOID                        *Buffer
 238   );
 239
 240 /**
 241 Write value to a CPU Save State register on the target processor.
 242
 243 This function abstracts the differences that whether the CPU Save State register is in the
 244 IA32 CPU Save State Map or X64 CPU Save State Map.
 245
 246 This function supports writing a CPU Save State register in SMBase relocation handler.
 247
 248 @param[in] CpuIndex       Specifies the zero-based index of the CPU save state.
 249 @param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 250 @param[in] Width          The number of bytes to read from the CPU save state.
 251 @param[in] Buffer         Upon entry, this holds the new CPU register value.
 252
 253 @retval EFI_SUCCESS           The register was written to Save State.
 254 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 255 @retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.
 256
 257 **/
 258 EFI_STATUS
 259 EFIAPI
 260 WriteSaveStateRegister (
 261   IN UINTN                        CpuIndex,
 262   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 263   IN UINTN                        Width,
 264   IN CONST VOID                   *Buffer
 265   );
 266
 267 //
 268 //
 269 //
 270 typedef struct {
 271   UINT32                            Offset;
 272   UINT16                            Segment;
 273   UINT16                            Reserved;
 274 } IA32_FAR_ADDRESS;
 275
 276 extern IA32_FAR_ADDRESS             gSmmJmpAddr;
 277
 278 extern CONST UINT8                  gcSmmInitTemplate[];
 279 extern CONST UINT16                 gcSmmInitSize;
 280 extern UINT32                       gSmmCr0;
 281 extern UINT32                       gSmmCr3;
 282 extern UINT32                       gSmmCr4;
 283 extern UINTN                        gSmmInitStack;
 284
 285 /**
 286   Semaphore operation for all processor relocate SMMBase.
 287 **/
 288 VOID
 289 EFIAPI
 290 SmmRelocationSemaphoreComplete (
 291   VOID
 292   );
 293
 294 ///
 295 /// The type of SMM CPU Information
 296 ///
 297 typedef struct {
 298   SPIN_LOCK                         Busy;
 299   volatile EFI_AP_PROCEDURE         Procedure;
 300   volatile VOID                     *Parameter;
 301   volatile UINT32                   Run;
 302   volatile BOOLEAN                  Present;
 303 } SMM_CPU_DATA_BLOCK;
 304
 305 typedef enum {
 306   SmmCpuSyncModeTradition,
 307   SmmCpuSyncModeRelaxedAp,
 308   SmmCpuSyncModeMax
 309 } SMM_CPU_SYNC_MODE;
 310
 311 typedef struct {
 312   //
 313   // Pointer to an array. The array should be located immediately after this structure
 314   // so that UC cache-ability can be set together.
 315   //
 316   SMM_CPU_DATA_BLOCK            *CpuData;
 317   volatile UINT32               Counter;
 318   volatile UINT32               BspIndex;
 319   volatile BOOLEAN              InsideSmm;
 320   volatile BOOLEAN              AllCpusInSync;
 321   volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;
 322   volatile BOOLEAN              SwitchBsp;
 323   volatile BOOLEAN              *CandidateBsp;
 324 } SMM_DISPATCHER_MP_SYNC_DATA;
 325
 326 typedef struct {
 327   SPIN_LOCK    SpinLock;
 328   UINT32       MsrIndex;
 329 } MP_MSR_LOCK;
 330
 331 #define SMM_PSD_OFFSET              0xfb00
 332
 333 typedef struct {
 334   UINT64                            Signature;              // Offset 0x00
 335   UINT16                            Reserved1;              // Offset 0x08
 336   UINT16                            Reserved2;              // Offset 0x0A
 337   UINT16                            Reserved3;              // Offset 0x0C
 338   UINT16                            SmmCs;                  // Offset 0x0E
 339   UINT16                            SmmDs;                  // Offset 0x10
 340   UINT16                            SmmSs;                  // Offset 0x12
 341   UINT16                            SmmOtherSegment;        // Offset 0x14
 342   UINT16                            Reserved4;              // Offset 0x16
 343   UINT64                            Reserved5;              // Offset 0x18
 344   UINT64                            Reserved6;              // Offset 0x20
 345   UINT64                            Reserved7;              // Offset 0x28
 346   UINT64                            SmmGdtPtr;              // Offset 0x30
 347   UINT32                            SmmGdtSize;             // Offset 0x38
 348   UINT32                            Reserved8;              // Offset 0x3C
 349   UINT64                            Reserved9;              // Offset 0x40
 350   UINT64                            Reserved10;             // Offset 0x48
 351   UINT16                            Reserved11;             // Offset 0x50
 352   UINT16                            Reserved12;             // Offset 0x52
 353   UINT32                            Reserved13;             // Offset 0x54
 354   UINT64                            MtrrBaseMaskPtr;        // Offset 0x58
 355 } PROCESSOR_SMM_DESCRIPTOR;
 356
 357 extern IA32_DESCRIPTOR                     gcSmiGdtr;
 358 extern IA32_DESCRIPTOR                     gcSmiIdtr;
 359 extern VOID                                *gcSmiIdtrPtr;
 360 extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;
 361 extern UINT64                              gPhyMask;
 362 extern ACPI_CPU_DATA                       mAcpiCpuData;
 363 extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;
 364 extern VOID                                *mGdtForAp;
 365 extern VOID                                *mIdtForAp;
 366 extern VOID                                *mMachineCheckHandlerForAp;
 367 extern UINTN                               mSmmStackArrayBase;
 368 extern UINTN                               mSmmStackArrayEnd;
 369 extern UINTN                               mSmmStackSize;
 370 extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;
 371 extern IA32_DESCRIPTOR                     gcSmiInitGdtr;
 372
 373 /**
 374   Create 4G PageTable in SMRAM.
 375
 376   @param          ExtraPages       Additional page numbers besides for 4G memory
 377   @param          Is32BitPageTable Whether the page table is 32-bit PAE
 378   @return         PageTable Address
 379
 380 **/
 381 UINT32
 382 Gen4GPageTable (
 383   IN      UINTN                     ExtraPages,
 384   IN      BOOLEAN                   Is32BitPageTable
 385   );
 386
 387
 388 /**
 389   Initialize global data for MP synchronization.
 390
 391   @param Stacks       Base address of SMI stack buffer for all processors.
 392   @param StackSize    Stack size for each processor in SMM.
 393
 394 **/
 395 UINT32
 396 InitializeMpServiceData (
 397   IN VOID        *Stacks,
 398   IN UINTN       StackSize
 399   );
 400
 401 /**
 402   Initialize Timer for SMM AP Sync.
 403
 404 **/
 405 VOID
 406 InitializeSmmTimer (
 407   VOID
 408   );
 409
 410 /**
 411   Start Timer for SMM AP Sync.
 412
 413 **/
 414 UINT64
 415 EFIAPI
 416 StartSyncTimer (
 417   VOID
 418   );
 419
 420 /**
 421   Check if the SMM AP Sync timer is timeout.
 422
 423   @param Timer  The start timer from the begin.
 424
 425 **/
 426 BOOLEAN
 427 EFIAPI
 428 IsSyncTimerTimeout (
 429   IN      UINT64                    Timer
 430   );
 431
 432 /**
 433   Initialize IDT for SMM Stack Guard.
 434
 435 **/
 436 VOID
 437 EFIAPI
 438 InitializeIDTSmmStackGuard (
 439   VOID
 440   );
 441
 442 /**
 443   Initialize Gdt for all processors.
 444
 445   @param[in]   Cr3          CR3 value.
 446   @param[out]  GdtStepSize  The step size for GDT table.
 447
 448   @return GdtBase for processor 0.
 449           GdtBase for processor X is: GdtBase + (GdtStepSize * X)
 450 **/
 451 VOID *
 452 InitGdt (
 453   IN  UINTN  Cr3,
 454   OUT UINTN  *GdtStepSize
 455   );
 456
 457 /**
 458
 459   Register the SMM Foundation entry point.
 460
 461   @param          This              Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
 462   @param          SmmEntryPoint     SMM Foundation EntryPoint
 463
 464   @retval         EFI_SUCCESS       Successfully to register SMM foundation entry point
 465
 466 **/
 467 EFI_STATUS
 468 EFIAPI
 469 RegisterSmmEntry (
 470   IN CONST EFI_SMM_CONFIGURATION_PROTOCOL  *This,
 471   IN EFI_SMM_ENTRY_POINT                   SmmEntryPoint
 472   );
 473
 474 /**
 475   Create PageTable for SMM use.
 476
 477   @return     PageTable Address
 478
 479 **/
 480 UINT32
 481 SmmInitPageTable (
 482   VOID
 483   );
 484
 485 /**
 486   Schedule a procedure to run on the specified CPU.
 487
 488   @param   Procedure        The address of the procedure to run
 489   @param   CpuIndex         Target CPU number
 490   @param   ProcArguments    The parameter to pass to the procedure
 491
 492   @retval   EFI_INVALID_PARAMETER    CpuNumber not valid
 493   @retval   EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 494   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 495   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 496   @retval   EFI_SUCCESS - The procedure has been successfully scheduled
 497
 498 **/
 499 EFI_STATUS
 500 EFIAPI
 501 SmmStartupThisAp (
 502   IN      EFI_AP_PROCEDURE          Procedure,
 503   IN      UINTN                     CpuIndex,
 504   IN OUT  VOID                      *ProcArguments OPTIONAL
 505   );
 506
 507 /**
 508   Schedule a procedure to run on the specified CPU in a blocking fashion.
 509
 510   @param  Procedure                The address of the procedure to run
 511   @param  CpuIndex                 Target CPU Index
 512   @param  ProcArguments            The parameter to pass to the procedure
 513
 514   @retval EFI_INVALID_PARAMETER    CpuNumber not valid
 515   @retval EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 516   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 517   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 518   @retval EFI_SUCCESS              The procedure has been successfully scheduled
 519
 520 **/
 521 EFI_STATUS
 522 EFIAPI
 523 SmmBlockingStartupThisAp (
 524   IN      EFI_AP_PROCEDURE          Procedure,
 525   IN      UINTN                     CpuIndex,
 526   IN OUT  VOID                      *ProcArguments OPTIONAL
 527   );
 528
 529 /**
 530   Initialize MP synchronization data.
 531
 532 **/
 533 VOID
 534 EFIAPI
 535 InitializeMpSyncData (
 536   VOID
 537   );
 538
 539 /**
 540
 541   Find out SMRAM information including SMRR base and SMRR size.
 542
 543   @param          SmrrBase          SMRR base
 544   @param          SmrrSize          SMRR size
 545
 546 **/
 547 VOID
 548 FindSmramInfo (
 549   OUT UINT32   *SmrrBase,
 550   OUT UINT32   *SmrrSize
 551   );
 552
 553 /**
 554   The function is invoked before SMBASE relocation in S3 path to restores CPU status.
 555
 556   The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
 557   and restores MTRRs for both BSP and APs.
 558
 559 **/
 560 VOID
 561 EarlyInitializeCpu (
 562   VOID
 563   );
 564
 565 /**
 566   The function is invoked after SMBASE relocation in S3 path to restores CPU status.
 567
 568   The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
 569   data saved by normal boot path for both BSP and APs.
 570
 571 **/
 572 VOID
 573 InitializeCpu (
 574   VOID
 575   );
 576
 577 /**
 578   Page Fault handler for SMM use.
 579
 580   @param  InterruptType    Defines the type of interrupt or exception that
 581                            occurred on the processor.This parameter is processor architecture specific.
 582   @param  SystemContext    A pointer to the processor context when
 583                            the interrupt occurred on the processor.
 584 **/
 585 VOID
 586 EFIAPI
 587 SmiPFHandler (
 588     IN EFI_EXCEPTION_TYPE   InterruptType,
 589     IN EFI_SYSTEM_CONTEXT   SystemContext
 590   );
 591
 592 /**
 593   Perform the remaining tasks.
 594
 595 **/
 596 VOID
 597 PerformRemainingTasks (
 598   VOID
 599   );
 600
 601 /**
 602   Perform the pre tasks.
 603
 604 **/
 605 VOID
 606 PerformPreTasks (
 607   VOID
 608   );
 609
 610 /**
 611   Initialize MSR spin lock by MSR index.
 612
 613   @param  MsrIndex       MSR index value.
 614
 615 **/
 616 VOID
 617 InitMsrSpinLockByIndex (
 618   IN UINT32      MsrIndex
 619   );
 620
 621 /**
 622   Hook return address of SMM Save State so that semaphore code
 623   can be executed immediately after AP exits SMM to indicate to
 624   the BSP that an AP has exited SMM after SMBASE relocation.
 625
 626   @param[in] CpuIndex     The processor index.
 627   @param[in] RebasedFlag  A pointer to a flag that is set to TRUE
 628                           immediately after AP exits SMM.
 629
 630 **/
 631 VOID
 632 SemaphoreHook (
 633   IN UINTN             CpuIndex,
 634   IN volatile BOOLEAN  *RebasedFlag
 635   );
 636
 637 /**
 638 Configure SMM Code Access Check feature for all processors.
 639 SMM Feature Control MSR will be locked after configuration.
 640 **/
 641 VOID
 642 ConfigSmmCodeAccessCheck (
 643   VOID
 644   );
 645
 646 /**
 647   Hook the code executed immediately after an RSM instruction on the currently
 648   executing CPU.  The mode of code executed immediately after RSM must be
 649   detected, and the appropriate hook must be selected.  Always clear the auto
 650   HALT restart flag if it is set.
 651
 652   @param[in] CpuIndex                 The processor index for the currently
 653                                       executing CPU.
 654   @param[in] CpuState                 Pointer to SMRAM Save State Map for the
 655                                       currently executing CPU.
 656   @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
 657                                       32-bit mode from 64-bit SMM.
 658   @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
 659                                       same mode as SMM.
 660
 661   @retval The value of the original instruction pointer before it was hooked.
 662
 663 **/
 664 UINT64
 665 EFIAPI
 666 HookReturnFromSmm (
 667   IN UINTN              CpuIndex,
 668   SMRAM_SAVE_STATE_MAP  *CpuState,
 669   UINT64                NewInstructionPointer32,
 670   UINT64                NewInstructionPointer
 671   );
 672
 673 /**
 674   Get the size of the SMI Handler in bytes.
 675
 676   @retval The size, in bytes, of the SMI Handler.
 677
 678 **/
 679 UINTN
 680 EFIAPI
 681 GetSmiHandlerSize (
 682   VOID
 683   );
 684
 685 /**
 686   Install the SMI handler for the CPU specified by CpuIndex.  This function
 687   is called by the CPU that was elected as monarch during System Management
 688   Mode initialization.
 689
 690   @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
 691                         The value must be between 0 and the NumberOfCpus field
 692                         in the System Management System Table (SMST).
 693   @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
 694   @param[in] SmiStack   The stack to use when an SMI is processed by the
 695                         the CPU specified by CpuIndex.
 696   @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
 697                         processed by the CPU specified by CpuIndex.
 698   @param[in] GdtBase    The base address of the GDT to use when an SMI is
 699                         processed by the CPU specified by CpuIndex.
 700   @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
 701                         processed by the CPU specified by CpuIndex.
 702   @param[in] IdtBase    The base address of the IDT to use when an SMI is
 703                         processed by the CPU specified by CpuIndex.
 704   @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
 705                         processed by the CPU specified by CpuIndex.
 706   @param[in] Cr3        The base address of the page tables to use when an SMI
 707                         is processed by the CPU specified by CpuIndex.
 708 **/
 709 VOID
 710 EFIAPI
 711 InstallSmiHandler (
 712   IN UINTN   CpuIndex,
 713   IN UINT32  SmBase,
 714   IN VOID    *SmiStack,
 715   IN UINTN   StackSize,
 716   IN UINTN   GdtBase,
 717   IN UINTN   GdtSize,
 718   IN UINTN   IdtBase,
 719   IN UINTN   IdtSize,
 720   IN UINT32  Cr3
 721   );
 722
 723 /**
 724   Search module name by input IP address and output it.
 725
 726   @param CallerIpAddress   Caller instruction pointer.
 727
 728 **/
 729 VOID
 730 DumpModuleInfoByIp (
 731   IN  UINTN              CallerIpAddress
 732   );
 733
 734 /**
 735   This API provides a way to allocate memory for page table.
 736
 737   This API can be called more once to allocate memory for page tables.
 738
 739   Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
 740   allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
 741   is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
 742   returned.
 743
 744   @param  Pages                 The number of 4 KB pages to allocate.
 745
 746   @return A pointer to the allocated buffer or NULL if allocation fails.
 747
 748 **/
 749 VOID *
 750 AllocatePageTableMemory (
 751   IN UINTN           Pages
 752   );
 753
 754 #endif