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UefiCpuPkg/PiSmmCpuDxeSmm: Add EFIAPI to CheckFeatureSupported()
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / SmmProfile.c
1 /** @file
2 Enable SMM profile.
3
4 Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PiSmmCpuDxeSmm.h"
16 #include "SmmProfileInternal.h"
17
18 UINT32 mSmmProfileCr3;
19
20 SMM_PROFILE_HEADER *mSmmProfileBase;
21 MSR_DS_AREA_STRUCT *mMsrDsAreaBase;
22 //
23 // The buffer to store SMM profile data.
24 //
25 UINTN mSmmProfileSize;
26
27 //
28 // The buffer to enable branch trace store.
29 //
30 UINTN mMsrDsAreaSize = SMM_PROFILE_DTS_SIZE;
31
32 //
33 // The flag indicates if execute-disable is supported by processor.
34 //
35 BOOLEAN mXdSupported = FALSE;
36
37 //
38 // The flag indicates if execute-disable is enabled on processor.
39 //
40 BOOLEAN mXdEnabled = FALSE;
41
42 //
43 // The flag indicates if BTS is supported by processor.
44 //
45 BOOLEAN mBtsSupported = FALSE;
46
47 //
48 // The flag indicates if SMM profile starts to record data.
49 //
50 BOOLEAN mSmmProfileStart = FALSE;
51
52 //
53 // Record the page fault exception count for one instruction execution.
54 //
55 UINTN *mPFEntryCount;
56
57 UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
58 UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];
59
60 MSR_DS_AREA_STRUCT **mMsrDsArea;
61 BRANCH_TRACE_RECORD **mMsrBTSRecord;
62 UINTN mBTSRecordNumber;
63 PEBS_RECORD **mMsrPEBSRecord;
64
65 //
66 // These memory ranges are always present, they does not generate the access type of page fault exception,
67 // but they possibly generate instruction fetch type of page fault exception.
68 //
69 MEMORY_PROTECTION_RANGE *mProtectionMemRange = NULL;
70 UINTN mProtectionMemRangeCount = 0;
71
72 //
73 // Some predefined memory ranges.
74 //
75 MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {
76 //
77 // SMRAM range (to be fixed in runtime).
78 // It is always present and instruction fetches are allowed.
79 //
80 {{0x00000000, 0x00000000},TRUE,FALSE},
81
82 //
83 // SMM profile data range( to be fixed in runtime).
84 // It is always present and instruction fetches are not allowed.
85 //
86 {{0x00000000, 0x00000000},TRUE,TRUE},
87
88 //
89 // Future extended range could be added here.
90 //
91
92 //
93 // PCI MMIO ranges (to be added in runtime).
94 // They are always present and instruction fetches are not allowed.
95 //
96 };
97
98 //
99 // These memory ranges are mapped by 4KB-page instead of 2MB-page.
100 //
101 MEMORY_RANGE *mSplitMemRange = NULL;
102 UINTN mSplitMemRangeCount = 0;
103
104 //
105 // SMI command port.
106 //
107 UINT32 mSmiCommandPort;
108
109 /**
110 Disable branch trace store.
111
112 **/
113 VOID
114 DisableBTS (
115 VOID
116 )
117 {
118 AsmMsrAnd64 (MSR_DEBUG_CTL, ~((UINT64)(MSR_DEBUG_CTL_BTS | MSR_DEBUG_CTL_TR)));
119 }
120
121 /**
122 Enable branch trace store.
123
124 **/
125 VOID
126 EnableBTS (
127 VOID
128 )
129 {
130 AsmMsrOr64 (MSR_DEBUG_CTL, (MSR_DEBUG_CTL_BTS | MSR_DEBUG_CTL_TR));
131 }
132
133 /**
134 Get CPU Index from APIC ID.
135
136 **/
137 UINTN
138 GetCpuIndex (
139 VOID
140 )
141 {
142 UINTN Index;
143 UINT32 ApicId;
144
145 ApicId = GetApicId ();
146
147 for (Index = 0; Index < PcdGet32 (PcdCpuMaxLogicalProcessorNumber); Index++) {
148 if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == ApicId) {
149 return Index;
150 }
151 }
152 ASSERT (FALSE);
153 return 0;
154 }
155
156 /**
157 Get the source of IP after execute-disable exception is triggered.
158
159 @param CpuIndex The index of CPU.
160 @param DestinationIP The destination address.
161
162 **/
163 UINT64
164 GetSourceFromDestinationOnBts (
165 UINTN CpuIndex,
166 UINT64 DestinationIP
167 )
168 {
169 BRANCH_TRACE_RECORD *CurrentBTSRecord;
170 UINTN Index;
171 BOOLEAN FirstMatch;
172
173 FirstMatch = FALSE;
174
175 CurrentBTSRecord = (BRANCH_TRACE_RECORD *)mMsrDsArea[CpuIndex]->BTSIndex;
176 for (Index = 0; Index < mBTSRecordNumber; Index++) {
177 if ((UINTN)CurrentBTSRecord < (UINTN)mMsrBTSRecord[CpuIndex]) {
178 //
179 // Underflow
180 //
181 CurrentBTSRecord = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[CpuIndex]->BTSAbsoluteMaximum - 1);
182 CurrentBTSRecord --;
183 }
184 if (CurrentBTSRecord->LastBranchTo == DestinationIP) {
185 //
186 // Good! find 1st one, then find 2nd one.
187 //
188 if (!FirstMatch) {
189 //
190 // The first one is DEBUG exception
191 //
192 FirstMatch = TRUE;
193 } else {
194 //
195 // Good find proper one.
196 //
197 return CurrentBTSRecord->LastBranchFrom;
198 }
199 }
200 CurrentBTSRecord--;
201 }
202
203 return 0;
204 }
205
206 /**
207 SMM profile specific INT 1 (single-step) exception handler.
208
209 @param InterruptType Defines the type of interrupt or exception that
210 occurred on the processor.This parameter is processor architecture specific.
211 @param SystemContext A pointer to the processor context when
212 the interrupt occurred on the processor.
213 **/
214 VOID
215 EFIAPI
216 DebugExceptionHandler (
217 IN EFI_EXCEPTION_TYPE InterruptType,
218 IN EFI_SYSTEM_CONTEXT SystemContext
219 )
220 {
221 UINTN CpuIndex;
222 UINTN PFEntry;
223
224 if (!mSmmProfileStart) {
225 return;
226 }
227 CpuIndex = GetCpuIndex ();
228
229 //
230 // Clear last PF entries
231 //
232 for (PFEntry = 0; PFEntry < mPFEntryCount[CpuIndex]; PFEntry++) {
233 *mLastPFEntryPointer[CpuIndex][PFEntry] = mLastPFEntryValue[CpuIndex][PFEntry];
234 }
235
236 //
237 // Reset page fault exception count for next page fault.
238 //
239 mPFEntryCount[CpuIndex] = 0;
240
241 //
242 // Flush TLB
243 //
244 CpuFlushTlb ();
245
246 //
247 // Clear TF in EFLAGS
248 //
249 ClearTrapFlag (SystemContext);
250 }
251
252 /**
253 Check if the memory address will be mapped by 4KB-page.
254
255 @param Address The address of Memory.
256 @param Nx The flag indicates if the memory is execute-disable.
257
258 **/
259 BOOLEAN
260 IsAddressValid (
261 IN EFI_PHYSICAL_ADDRESS Address,
262 IN BOOLEAN *Nx
263 )
264 {
265 UINTN Index;
266
267 *Nx = FALSE;
268 if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
269 //
270 // Check configuration
271 //
272 for (Index = 0; Index < mProtectionMemRangeCount; Index++) {
273 if ((Address >= mProtectionMemRange[Index].Range.Base) && (Address < mProtectionMemRange[Index].Range.Top)) {
274 *Nx = mProtectionMemRange[Index].Nx;
275 return mProtectionMemRange[Index].Present;
276 }
277 }
278 *Nx = TRUE;
279 return FALSE;
280
281 } else {
282 if ((Address < mCpuHotPlugData.SmrrBase) ||
283 (Address >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
284 *Nx = TRUE;
285 }
286 return TRUE;
287 }
288 }
289
290 /**
291 Check if the memory address will be mapped by 4KB-page.
292
293 @param Address The address of Memory.
294
295 **/
296 BOOLEAN
297 IsAddressSplit (
298 IN EFI_PHYSICAL_ADDRESS Address
299 )
300 {
301 UINTN Index;
302
303 if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
304 //
305 // Check configuration
306 //
307 for (Index = 0; Index < mSplitMemRangeCount; Index++) {
308 if ((Address >= mSplitMemRange[Index].Base) && (Address < mSplitMemRange[Index].Top)) {
309 return TRUE;
310 }
311 }
312 } else {
313 if (Address < mCpuHotPlugData.SmrrBase) {
314 if ((mCpuHotPlugData.SmrrBase - Address) < BASE_2MB) {
315 return TRUE;
316 }
317 } else if (Address > (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) {
318 if ((Address - (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) < BASE_2MB) {
319 return TRUE;
320 }
321 }
322 }
323 //
324 // Return default
325 //
326 return FALSE;
327 }
328
329 /**
330 Initialize the protected memory ranges and the 4KB-page mapped memory ranges.
331
332 **/
333 VOID
334 InitProtectedMemRange (
335 VOID
336 )
337 {
338 UINTN Index;
339 UINTN NumberOfDescriptors;
340 UINTN NumberOfMmioDescriptors;
341 UINTN NumberOfProtectRange;
342 UINTN NumberOfSpliteRange;
343 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
344 UINTN TotalSize;
345 EFI_STATUS Status;
346 EFI_PHYSICAL_ADDRESS ProtectBaseAddress;
347 EFI_PHYSICAL_ADDRESS ProtectEndAddress;
348 EFI_PHYSICAL_ADDRESS Top2MBAlignedAddress;
349 EFI_PHYSICAL_ADDRESS Base2MBAlignedAddress;
350 UINT64 High4KBPageSize;
351 UINT64 Low4KBPageSize;
352
353 NumberOfDescriptors = 0;
354 NumberOfMmioDescriptors = 0;
355 NumberOfSpliteRange = 0;
356 MemorySpaceMap = NULL;
357
358 //
359 // Get MMIO ranges from GCD and add them into protected memory ranges.
360 //
361 Status = gDS->GetMemorySpaceMap (
362 &NumberOfDescriptors,
363 &MemorySpaceMap
364 );
365 for (Index = 0; Index < NumberOfDescriptors; Index++) {
366 if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) {
367 NumberOfMmioDescriptors++;
368 }
369 }
370
371 if (NumberOfMmioDescriptors != 0) {
372 TotalSize = NumberOfMmioDescriptors * sizeof (MEMORY_PROTECTION_RANGE) + sizeof (mProtectionMemRangeTemplate);
373 mProtectionMemRange = (MEMORY_PROTECTION_RANGE *) AllocateZeroPool (TotalSize);
374 ASSERT (mProtectionMemRange != NULL);
375 mProtectionMemRangeCount = TotalSize / sizeof (MEMORY_PROTECTION_RANGE);
376
377 //
378 // Copy existing ranges.
379 //
380 CopyMem (mProtectionMemRange, mProtectionMemRangeTemplate, sizeof (mProtectionMemRangeTemplate));
381
382 //
383 // Create split ranges which come from protected ranges.
384 //
385 TotalSize = (TotalSize / sizeof (MEMORY_PROTECTION_RANGE)) * sizeof (MEMORY_RANGE);
386 mSplitMemRange = (MEMORY_RANGE *) AllocateZeroPool (TotalSize);
387 ASSERT (mSplitMemRange != NULL);
388
389 //
390 // Create MMIO ranges which are set to present and execution-disable.
391 //
392 NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof (MEMORY_PROTECTION_RANGE);
393 for (Index = 0; Index < NumberOfDescriptors; Index++) {
394 if (MemorySpaceMap[Index].GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo) {
395 continue;
396 }
397 mProtectionMemRange[NumberOfProtectRange].Range.Base = MemorySpaceMap[Index].BaseAddress;
398 mProtectionMemRange[NumberOfProtectRange].Range.Top = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length;
399 mProtectionMemRange[NumberOfProtectRange].Present = TRUE;
400 mProtectionMemRange[NumberOfProtectRange].Nx = TRUE;
401 NumberOfProtectRange++;
402 }
403 }
404
405 //
406 // According to protected ranges, create the ranges which will be mapped by 2KB page.
407 //
408 NumberOfSpliteRange = 0;
409 NumberOfProtectRange = mProtectionMemRangeCount;
410 for (Index = 0; Index < NumberOfProtectRange; Index++) {
411 //
412 // If MMIO base address is not 2MB alignment, make 2MB alignment for create 4KB page in page table.
413 //
414 ProtectBaseAddress = mProtectionMemRange[Index].Range.Base;
415 ProtectEndAddress = mProtectionMemRange[Index].Range.Top;
416 if (((ProtectBaseAddress & (SIZE_2MB - 1)) != 0) || ((ProtectEndAddress & (SIZE_2MB - 1)) != 0)) {
417 //
418 // Check if it is possible to create 4KB-page for not 2MB-aligned range and to create 2MB-page for 2MB-aligned range.
419 // A mix of 4KB and 2MB page could save SMRAM space.
420 //
421 Top2MBAlignedAddress = ProtectEndAddress & ~(SIZE_2MB - 1);
422 Base2MBAlignedAddress = (ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);
423 if ((Top2MBAlignedAddress > Base2MBAlignedAddress) &&
424 ((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB)) {
425 //
426 // There is an range which could be mapped by 2MB-page.
427 //
428 High4KBPageSize = ((ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1)) - (ProtectEndAddress & ~(SIZE_2MB - 1));
429 Low4KBPageSize = ((ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1)) - (ProtectBaseAddress & ~(SIZE_2MB - 1));
430 if (High4KBPageSize != 0) {
431 //
432 // Add not 2MB-aligned range to be mapped by 4KB-page.
433 //
434 mSplitMemRange[NumberOfSpliteRange].Base = ProtectEndAddress & ~(SIZE_2MB - 1);
435 mSplitMemRange[NumberOfSpliteRange].Top = (ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);
436 NumberOfSpliteRange++;
437 }
438 if (Low4KBPageSize != 0) {
439 //
440 // Add not 2MB-aligned range to be mapped by 4KB-page.
441 //
442 mSplitMemRange[NumberOfSpliteRange].Base = ProtectBaseAddress & ~(SIZE_2MB - 1);
443 mSplitMemRange[NumberOfSpliteRange].Top = (ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);
444 NumberOfSpliteRange++;
445 }
446 } else {
447 //
448 // The range could only be mapped by 4KB-page.
449 //
450 mSplitMemRange[NumberOfSpliteRange].Base = ProtectBaseAddress & ~(SIZE_2MB - 1);
451 mSplitMemRange[NumberOfSpliteRange].Top = (ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);
452 NumberOfSpliteRange++;
453 }
454 }
455 }
456
457 mSplitMemRangeCount = NumberOfSpliteRange;
458
459 DEBUG ((EFI_D_INFO, "SMM Profile Memory Ranges:\n"));
460 for (Index = 0; Index < mProtectionMemRangeCount; Index++) {
461 DEBUG ((EFI_D_INFO, "mProtectionMemRange[%d].Base = %lx\n", Index, mProtectionMemRange[Index].Range.Base));
462 DEBUG ((EFI_D_INFO, "mProtectionMemRange[%d].Top = %lx\n", Index, mProtectionMemRange[Index].Range.Top));
463 }
464 for (Index = 0; Index < mSplitMemRangeCount; Index++) {
465 DEBUG ((EFI_D_INFO, "mSplitMemRange[%d].Base = %lx\n", Index, mSplitMemRange[Index].Base));
466 DEBUG ((EFI_D_INFO, "mSplitMemRange[%d].Top = %lx\n", Index, mSplitMemRange[Index].Top));
467 }
468 }
469
470 /**
471 Update page table according to protected memory ranges and the 4KB-page mapped memory ranges.
472
473 **/
474 VOID
475 InitPaging (
476 VOID
477 )
478 {
479 UINT64 *Pml4;
480 UINT64 *Pde;
481 UINT64 *Pte;
482 UINT64 *Pt;
483 UINTN Address;
484 UINTN Level1;
485 UINTN Level2;
486 UINTN Level3;
487 UINTN Level4;
488 UINTN NumberOfPdpEntries;
489 UINTN NumberOfPml4Entries;
490 UINTN SizeOfMemorySpace;
491 BOOLEAN Nx;
492
493 if (sizeof (UINTN) == sizeof (UINT64)) {
494 Pml4 = (UINT64*)(UINTN)mSmmProfileCr3;
495 SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1;
496 //
497 // Calculate the table entries of PML4E and PDPTE.
498 //
499 if (SizeOfMemorySpace <= 39 ) {
500 NumberOfPml4Entries = 1;
501 NumberOfPdpEntries = (UINT32)LShiftU64 (1, (SizeOfMemorySpace - 30));
502 } else {
503 NumberOfPml4Entries = (UINT32)LShiftU64 (1, (SizeOfMemorySpace - 39));
504 NumberOfPdpEntries = 512;
505 }
506 } else {
507 NumberOfPml4Entries = 1;
508 NumberOfPdpEntries = 4;
509 }
510
511 //
512 // Go through page table and change 2MB-page into 4KB-page.
513 //
514 for (Level1 = 0; Level1 < NumberOfPml4Entries; Level1++) {
515 if (sizeof (UINTN) == sizeof (UINT64)) {
516 if ((Pml4[Level1] & IA32_PG_P) == 0) {
517 //
518 // If Pml4 entry does not exist, skip it
519 //
520 continue;
521 }
522 Pde = (UINT64 *)(UINTN)(Pml4[Level1] & PHYSICAL_ADDRESS_MASK);
523 } else {
524 Pde = (UINT64*)(UINTN)mSmmProfileCr3;
525 }
526 for (Level2 = 0; Level2 < NumberOfPdpEntries; Level2++, Pde++) {
527 if ((*Pde & IA32_PG_P) == 0) {
528 //
529 // If PDE entry does not exist, skip it
530 //
531 continue;
532 }
533 Pte = (UINT64 *)(UINTN)(*Pde & PHYSICAL_ADDRESS_MASK);
534 if (Pte == 0) {
535 continue;
536 }
537 for (Level3 = 0; Level3 < SIZE_4KB / sizeof (*Pte); Level3++, Pte++) {
538 if ((*Pte & IA32_PG_P) == 0) {
539 //
540 // If PTE entry does not exist, skip it
541 //
542 continue;
543 }
544 Address = (((Level2 << 9) + Level3) << 21);
545
546 //
547 // If it is 2M page, check IsAddressSplit()
548 //
549 if (((*Pte & IA32_PG_PS) != 0) && IsAddressSplit (Address)) {
550 //
551 // Based on current page table, create 4KB page table for split area.
552 //
553 ASSERT (Address == (*Pte & PHYSICAL_ADDRESS_MASK));
554
555 Pt = AllocatePageTableMemory (1);
556 ASSERT (Pt != NULL);
557
558 // Split it
559 for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) {
560 Pt[Level4] = Address + ((Level4 << 12) | PAGE_ATTRIBUTE_BITS);
561 } // end for PT
562 *Pte = (UINTN)Pt | PAGE_ATTRIBUTE_BITS;
563 } // end if IsAddressSplit
564 } // end for PTE
565 } // end for PDE
566 }
567
568 //
569 // Go through page table and set several page table entries to absent or execute-disable.
570 //
571 DEBUG ((EFI_D_INFO, "Patch page table start ...\n"));
572 for (Level1 = 0; Level1 < NumberOfPml4Entries; Level1++) {
573 if (sizeof (UINTN) == sizeof (UINT64)) {
574 if ((Pml4[Level1] & IA32_PG_P) == 0) {
575 //
576 // If Pml4 entry does not exist, skip it
577 //
578 continue;
579 }
580 Pde = (UINT64 *)(UINTN)(Pml4[Level1] & PHYSICAL_ADDRESS_MASK);
581 } else {
582 Pde = (UINT64*)(UINTN)mSmmProfileCr3;
583 }
584 for (Level2 = 0; Level2 < NumberOfPdpEntries; Level2++, Pde++) {
585 if ((*Pde & IA32_PG_P) == 0) {
586 //
587 // If PDE entry does not exist, skip it
588 //
589 continue;
590 }
591 Pte = (UINT64 *)(UINTN)(*Pde & PHYSICAL_ADDRESS_MASK);
592 if (Pte == 0) {
593 continue;
594 }
595 for (Level3 = 0; Level3 < SIZE_4KB / sizeof (*Pte); Level3++, Pte++) {
596 if ((*Pte & IA32_PG_P) == 0) {
597 //
598 // If PTE entry does not exist, skip it
599 //
600 continue;
601 }
602 Address = (((Level2 << 9) + Level3) << 21);
603
604 if ((*Pte & IA32_PG_PS) != 0) {
605 // 2MB page
606
607 if (!IsAddressValid (Address, &Nx)) {
608 //
609 // Patch to remove Present flag and RW flag
610 //
611 *Pte = *Pte & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
612 }
613 if (Nx && mXdSupported) {
614 *Pte = *Pte | IA32_PG_NX;
615 }
616 } else {
617 // 4KB page
618 Pt = (UINT64 *)(UINTN)(*Pte & PHYSICAL_ADDRESS_MASK);
619 if (Pt == 0) {
620 continue;
621 }
622 for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++, Pt++) {
623 if (!IsAddressValid (Address, &Nx)) {
624 *Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
625 }
626 if (Nx && mXdSupported) {
627 *Pt = *Pt | IA32_PG_NX;
628 }
629 Address += SIZE_4KB;
630 } // end for PT
631 } // end if PS
632 } // end for PTE
633 } // end for PDE
634 }
635
636 //
637 // Flush TLB
638 //
639 CpuFlushTlb ();
640 DEBUG ((EFI_D_INFO, "Patch page table done!\n"));
641 //
642 // Set execute-disable flag
643 //
644 mXdEnabled = TRUE;
645
646 return ;
647 }
648
649 /**
650 To find FADT in ACPI tables.
651
652 @param AcpiTableGuid The GUID used to find ACPI table in UEFI ConfigurationTable.
653
654 @return FADT table pointer.
655 **/
656 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *
657 FindAcpiFadtTableByAcpiGuid (
658 IN EFI_GUID *AcpiTableGuid
659 )
660 {
661 EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp;
662 EFI_ACPI_DESCRIPTION_HEADER *Rsdt;
663 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
664 UINTN Index;
665 UINT32 Data32;
666 Rsdp = NULL;
667 Rsdt = NULL;
668 Fadt = NULL;
669 //
670 // found ACPI table RSD_PTR from system table
671 //
672 for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {
673 if (CompareGuid (&(gST->ConfigurationTable[Index].VendorGuid), AcpiTableGuid)) {
674 //
675 // A match was found.
676 //
677 Rsdp = gST->ConfigurationTable[Index].VendorTable;
678 break;
679 }
680 }
681
682 if (Rsdp == NULL) {
683 return NULL;
684 }
685
686 Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN) Rsdp->RsdtAddress;
687 if (Rsdt == NULL || Rsdt->Signature != EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
688 return NULL;
689 }
690
691 for (Index = sizeof (EFI_ACPI_DESCRIPTION_HEADER); Index < Rsdt->Length; Index = Index + sizeof (UINT32)) {
692
693 Data32 = *(UINT32 *) ((UINT8 *) Rsdt + Index);
694 Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) (UINT32 *) (UINTN) Data32;
695 if (Fadt->Header.Signature == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
696 break;
697 }
698 }
699
700 if (Fadt == NULL || Fadt->Header.Signature != EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
701 return NULL;
702 }
703
704 return Fadt;
705 }
706
707 /**
708 To find FADT in ACPI tables.
709
710 @return FADT table pointer.
711 **/
712 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *
713 FindAcpiFadtTable (
714 VOID
715 )
716 {
717 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
718
719 Fadt = FindAcpiFadtTableByAcpiGuid (&gEfiAcpi20TableGuid);
720 if (Fadt != NULL) {
721 return Fadt;
722 }
723
724 return FindAcpiFadtTableByAcpiGuid (&gEfiAcpi10TableGuid);
725 }
726
727 /**
728 To get system port address of the SMI Command Port in FADT table.
729
730 **/
731 VOID
732 GetSmiCommandPort (
733 VOID
734 )
735 {
736 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
737
738 Fadt = FindAcpiFadtTable ();
739 ASSERT (Fadt != NULL);
740
741 mSmiCommandPort = Fadt->SmiCmd;
742 DEBUG ((EFI_D_INFO, "mSmiCommandPort = %x\n", mSmiCommandPort));
743 }
744
745 /**
746 Updates page table to make some memory ranges (like system memory) absent
747 and make some memory ranges (like MMIO) present and execute disable. It also
748 update 2MB-page to 4KB-page for some memory ranges.
749
750 **/
751 VOID
752 SmmProfileStart (
753 VOID
754 )
755 {
756 //
757 // The flag indicates SMM profile starts to work.
758 //
759 mSmmProfileStart = TRUE;
760 }
761
762 /**
763 Initialize SMM profile in SmmReadyToLock protocol callback function.
764
765 @param Protocol Points to the protocol's unique identifier.
766 @param Interface Points to the interface instance.
767 @param Handle The handle on which the interface was installed.
768
769 @retval EFI_SUCCESS SmmReadyToLock protocol callback runs successfully.
770 **/
771 EFI_STATUS
772 EFIAPI
773 InitSmmProfileCallBack (
774 IN CONST EFI_GUID *Protocol,
775 IN VOID *Interface,
776 IN EFI_HANDLE Handle
777 )
778 {
779 EFI_STATUS Status;
780
781 //
782 // Save to variable so that SMM profile data can be found.
783 //
784 Status = gRT->SetVariable (
785 SMM_PROFILE_NAME,
786 &gEfiCallerIdGuid,
787 EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
788 sizeof(mSmmProfileBase),
789 &mSmmProfileBase
790 );
791
792 //
793 // Get Software SMI from FADT
794 //
795 GetSmiCommandPort ();
796
797 //
798 // Initialize protected memory range for patching page table later.
799 //
800 InitProtectedMemRange ();
801
802 return EFI_SUCCESS;
803 }
804
805 /**
806 Initialize SMM profile data structures.
807
808 **/
809 VOID
810 InitSmmProfileInternal (
811 VOID
812 )
813 {
814 EFI_STATUS Status;
815 EFI_PHYSICAL_ADDRESS Base;
816 VOID *Registration;
817 UINTN Index;
818 UINTN MsrDsAreaSizePerCpu;
819 UINTN TotalSize;
820
821 mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
822 ASSERT (mPFEntryCount != NULL);
823 mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (
824 sizeof (mLastPFEntryValue[0]) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
825 ASSERT (mLastPFEntryValue != NULL);
826 mLastPFEntryPointer = (UINT64 *(*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (
827 sizeof (mLastPFEntryPointer[0]) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
828 ASSERT (mLastPFEntryPointer != NULL);
829
830 //
831 // Allocate memory for SmmProfile below 4GB.
832 // The base address
833 //
834 mSmmProfileSize = PcdGet32 (PcdCpuSmmProfileSize);
835 ASSERT ((mSmmProfileSize & 0xFFF) == 0);
836
837 if (mBtsSupported) {
838 TotalSize = mSmmProfileSize + mMsrDsAreaSize;
839 } else {
840 TotalSize = mSmmProfileSize;
841 }
842
843 Base = 0xFFFFFFFF;
844 Status = gBS->AllocatePages (
845 AllocateMaxAddress,
846 EfiReservedMemoryType,
847 EFI_SIZE_TO_PAGES (TotalSize),
848 &Base
849 );
850 ASSERT_EFI_ERROR (Status);
851 ZeroMem ((VOID *)(UINTN)Base, TotalSize);
852 mSmmProfileBase = (SMM_PROFILE_HEADER *)(UINTN)Base;
853
854 //
855 // Initialize SMM profile data header.
856 //
857 mSmmProfileBase->HeaderSize = sizeof (SMM_PROFILE_HEADER);
858 mSmmProfileBase->MaxDataEntries = (UINT64)((mSmmProfileSize - sizeof(SMM_PROFILE_HEADER)) / sizeof (SMM_PROFILE_ENTRY));
859 mSmmProfileBase->MaxDataSize = MultU64x64 (mSmmProfileBase->MaxDataEntries, sizeof(SMM_PROFILE_ENTRY));
860 mSmmProfileBase->CurDataEntries = 0;
861 mSmmProfileBase->CurDataSize = 0;
862 mSmmProfileBase->TsegStart = mCpuHotPlugData.SmrrBase;
863 mSmmProfileBase->TsegSize = mCpuHotPlugData.SmrrSize;
864 mSmmProfileBase->NumSmis = 0;
865 mSmmProfileBase->NumCpus = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
866
867 if (mBtsSupported) {
868 mMsrDsArea = (MSR_DS_AREA_STRUCT **)AllocateZeroPool (sizeof (MSR_DS_AREA_STRUCT *) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
869 ASSERT (mMsrDsArea != NULL);
870 mMsrBTSRecord = (BRANCH_TRACE_RECORD **)AllocateZeroPool (sizeof (BRANCH_TRACE_RECORD *) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
871 ASSERT (mMsrBTSRecord != NULL);
872 mMsrPEBSRecord = (PEBS_RECORD **)AllocateZeroPool (sizeof (PEBS_RECORD *) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
873 ASSERT (mMsrPEBSRecord != NULL);
874
875 mMsrDsAreaBase = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize);
876 MsrDsAreaSizePerCpu = mMsrDsAreaSize / PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
877 mBTSRecordNumber = (MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof(MSR_DS_AREA_STRUCT)) / sizeof(BRANCH_TRACE_RECORD);
878 for (Index = 0; Index < PcdGet32 (PcdCpuMaxLogicalProcessorNumber); Index++) {
879 mMsrDsArea[Index] = (MSR_DS_AREA_STRUCT *)((UINTN)mMsrDsAreaBase + MsrDsAreaSizePerCpu * Index);
880 mMsrBTSRecord[Index] = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof(MSR_DS_AREA_STRUCT));
881 mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER);
882
883 mMsrDsArea[Index]->BTSBufferBase = (UINTN)mMsrBTSRecord[Index];
884 mMsrDsArea[Index]->BTSIndex = mMsrDsArea[Index]->BTSBufferBase;
885 mMsrDsArea[Index]->BTSAbsoluteMaximum = mMsrDsArea[Index]->BTSBufferBase + mBTSRecordNumber * sizeof(BRANCH_TRACE_RECORD) + 1;
886 mMsrDsArea[Index]->BTSInterruptThreshold = mMsrDsArea[Index]->BTSAbsoluteMaximum + 1;
887
888 mMsrDsArea[Index]->PEBSBufferBase = (UINTN)mMsrPEBSRecord[Index];
889 mMsrDsArea[Index]->PEBSIndex = mMsrDsArea[Index]->PEBSBufferBase;
890 mMsrDsArea[Index]->PEBSAbsoluteMaximum = mMsrDsArea[Index]->PEBSBufferBase + PEBS_RECORD_NUMBER * sizeof(PEBS_RECORD) + 1;
891 mMsrDsArea[Index]->PEBSInterruptThreshold = mMsrDsArea[Index]->PEBSAbsoluteMaximum + 1;
892 }
893 }
894
895 mProtectionMemRange = mProtectionMemRangeTemplate;
896 mProtectionMemRangeCount = sizeof (mProtectionMemRangeTemplate) / sizeof (MEMORY_PROTECTION_RANGE);
897
898 //
899 // Update TSeg entry.
900 //
901 mProtectionMemRange[0].Range.Base = mCpuHotPlugData.SmrrBase;
902 mProtectionMemRange[0].Range.Top = mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize;
903
904 //
905 // Update SMM profile entry.
906 //
907 mProtectionMemRange[1].Range.Base = (EFI_PHYSICAL_ADDRESS)(UINTN)mSmmProfileBase;
908 mProtectionMemRange[1].Range.Top = (EFI_PHYSICAL_ADDRESS)(UINTN)mSmmProfileBase + TotalSize;
909
910 //
911 // Allocate memory reserved for creating 4KB pages.
912 //
913 InitPagesForPFHandler ();
914
915 //
916 // Start SMM profile when SmmReadyToLock protocol is installed.
917 //
918 Status = gSmst->SmmRegisterProtocolNotify (
919 &gEfiSmmReadyToLockProtocolGuid,
920 InitSmmProfileCallBack,
921 &Registration
922 );
923 ASSERT_EFI_ERROR (Status);
924
925 return ;
926 }
927
928 /**
929 Check if XD feature is supported by a processor.
930
931 @param[in,out] Buffer The pointer to private data buffer.
932
933 **/
934 VOID
935 EFIAPI
936 CheckFeatureSupported (
937 IN OUT VOID *Buffer
938 )
939 {
940 UINT32 RegEax;
941 UINT32 RegEdx;
942
943 if (mXdSupported) {
944 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
945 if (RegEax <= CPUID_EXTENDED_FUNCTION) {
946 //
947 // Extended CPUID functions are not supported on this processor.
948 //
949 mXdSupported = FALSE;
950 }
951
952 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
953 if ((RegEdx & CPUID1_EDX_XD_SUPPORT) == 0) {
954 //
955 // Execute Disable Bit feature is not supported on this processor.
956 //
957 mXdSupported = FALSE;
958 }
959 }
960
961 if (mBtsSupported) {
962 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
963 if ((RegEdx & CPUID1_EDX_BTS_AVAILABLE) != 0) {
964 //
965 // Per IA32 manuals:
966 // When CPUID.1:EDX[21] is set, the following BTS facilities are available:
967 // 1. The BTS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates the
968 // availability of the BTS facilities, including the ability to set the BTS and
969 // BTINT bits in the MSR_DEBUGCTLA MSR.
970 // 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area.
971 //
972 if ((AsmMsrBitFieldRead64 (MSR_IA32_MISC_ENABLE, 11, 11) == 0) &&
973 (AsmMsrBitFieldRead64 (MSR_IA32_MISC_ENABLE, 12, 12) == 0)) {
974 //
975 // BTS facilities is supported.
976 //
977 mBtsSupported = FALSE;
978 }
979 }
980 }
981 }
982
983 /**
984 Check if XD and BTS features are supported by all processors.
985
986 **/
987 VOID
988 CheckProcessorFeature (
989 VOID
990 )
991 {
992 EFI_STATUS Status;
993 EFI_MP_SERVICES_PROTOCOL *MpServices;
994
995 Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices);
996 ASSERT_EFI_ERROR (Status);
997
998 //
999 // First detect if XD and BTS are supported
1000 //
1001 mXdSupported = TRUE;
1002 mBtsSupported = TRUE;
1003
1004 //
1005 // Check if XD and BTS are supported on all processors.
1006 //
1007 CheckFeatureSupported (NULL);
1008
1009 //
1010 //Check on other processors if BSP supports this
1011 //
1012 if (mXdSupported || mBtsSupported) {
1013 MpServices->StartupAllAPs (
1014 MpServices,
1015 CheckFeatureSupported,
1016 TRUE,
1017 NULL,
1018 0,
1019 NULL,
1020 NULL
1021 );
1022 }
1023 }
1024
1025 /**
1026 Enable XD feature.
1027
1028 **/
1029 VOID
1030 ActivateXd (
1031 VOID
1032 )
1033 {
1034 UINT64 MsrRegisters;
1035
1036 MsrRegisters = AsmReadMsr64 (MSR_EFER);
1037 if ((MsrRegisters & MSR_EFER_XD) != 0) {
1038 return ;
1039 }
1040 MsrRegisters |= MSR_EFER_XD;
1041 AsmWriteMsr64 (MSR_EFER, MsrRegisters);
1042 }
1043
1044 /**
1045 Enable single step.
1046
1047 **/
1048 VOID
1049 ActivateSingleStepDB (
1050 VOID
1051 )
1052 {
1053 UINTN Dr6;
1054
1055 Dr6 = AsmReadDr6 ();
1056 if ((Dr6 & DR6_SINGLE_STEP) != 0) {
1057 return;
1058 }
1059 Dr6 |= DR6_SINGLE_STEP;
1060 AsmWriteDr6 (Dr6);
1061 }
1062
1063 /**
1064 Enable last branch.
1065
1066 **/
1067 VOID
1068 ActivateLBR (
1069 VOID
1070 )
1071 {
1072 UINT64 DebugCtl;
1073
1074 DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);
1075 if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) {
1076 return ;
1077 }
1078 AsmWriteMsr64 (MSR_LER_FROM_LIP, 0);
1079 AsmWriteMsr64 (MSR_LER_TO_LIP, 0);
1080 DebugCtl |= MSR_DEBUG_CTL_LBR;
1081 AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);
1082 }
1083
1084 /**
1085 Enable branch trace store.
1086
1087 @param CpuIndex The index of the processor.
1088
1089 **/
1090 VOID
1091 ActivateBTS (
1092 IN UINTN CpuIndex
1093 )
1094 {
1095 UINT64 DebugCtl;
1096
1097 DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);
1098 if ((DebugCtl & MSR_DEBUG_CTL_BTS) != 0) {
1099 return ;
1100 }
1101
1102 AsmWriteMsr64 (MSR_DS_AREA, (UINT64)(UINTN)mMsrDsArea[CpuIndex]);
1103 DebugCtl |= (UINT64)(MSR_DEBUG_CTL_BTS | MSR_DEBUG_CTL_TR);
1104 DebugCtl &= ~((UINT64)MSR_DEBUG_CTL_BTINT);
1105 AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);
1106 }
1107
1108 /**
1109 Increase SMI number in each SMI entry.
1110
1111 **/
1112 VOID
1113 SmmProfileRecordSmiNum (
1114 VOID
1115 )
1116 {
1117 if (mSmmProfileStart) {
1118 mSmmProfileBase->NumSmis++;
1119 }
1120 }
1121
1122 /**
1123 Initialize processor environment for SMM profile.
1124
1125 @param CpuIndex The index of the processor.
1126
1127 **/
1128 VOID
1129 ActivateSmmProfile (
1130 IN UINTN CpuIndex
1131 )
1132 {
1133 //
1134 // Enable Single Step DB#
1135 //
1136 ActivateSingleStepDB ();
1137
1138 if (mBtsSupported) {
1139 //
1140 // We can not get useful information from LER, so we have to use BTS.
1141 //
1142 ActivateLBR ();
1143
1144 //
1145 // Enable BTS
1146 //
1147 ActivateBTS (CpuIndex);
1148 }
1149 }
1150
1151 /**
1152 Initialize SMM profile in SMM CPU entry point.
1153
1154 @param[in] Cr3 The base address of the page tables to use in SMM.
1155
1156 **/
1157 VOID
1158 InitSmmProfile (
1159 UINT32 Cr3
1160 )
1161 {
1162 //
1163 // Save Cr3
1164 //
1165 mSmmProfileCr3 = Cr3;
1166
1167 //
1168 // Skip SMM profile initialization if feature is disabled
1169 //
1170 if (!FeaturePcdGet (PcdCpuSmmProfileEnable)) {
1171 return;
1172 }
1173
1174 //
1175 // Initialize SmmProfile here
1176 //
1177 InitSmmProfileInternal ();
1178
1179 //
1180 // Initialize profile IDT.
1181 //
1182 InitIdtr ();
1183 }
1184
1185 /**
1186 Update page table to map the memory correctly in order to make the instruction
1187 which caused page fault execute successfully. And it also save the original page
1188 table to be restored in single-step exception.
1189
1190 @param PageTable PageTable Address.
1191 @param PFAddress The memory address which caused page fault exception.
1192 @param CpuIndex The index of the processor.
1193 @param ErrorCode The Error code of exception.
1194
1195 **/
1196 VOID
1197 RestorePageTableBelow4G (
1198 UINT64 *PageTable,
1199 UINT64 PFAddress,
1200 UINTN CpuIndex,
1201 UINTN ErrorCode
1202 )
1203 {
1204 UINTN PTIndex;
1205 UINTN PFIndex;
1206
1207 //
1208 // PML4
1209 //
1210 if (sizeof(UINT64) == sizeof(UINTN)) {
1211 PTIndex = (UINTN)BitFieldRead64 (PFAddress, 39, 47);
1212 ASSERT (PageTable[PTIndex] != 0);
1213 PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
1214 }
1215
1216 //
1217 // PDPTE
1218 //
1219 PTIndex = (UINTN)BitFieldRead64 (PFAddress, 30, 38);
1220 ASSERT (PageTable[PTIndex] != 0);
1221 PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
1222
1223 //
1224 // PD
1225 //
1226 PTIndex = (UINTN)BitFieldRead64 (PFAddress, 21, 29);
1227 if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {
1228 //
1229 // Large page
1230 //
1231
1232 //
1233 // Record old entries with non-present status
1234 // Old entries include the memory which instruction is at and the memory which instruction access.
1235 //
1236 //
1237 ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);
1238 if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {
1239 PFIndex = mPFEntryCount[CpuIndex];
1240 mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex];
1241 mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];
1242 mPFEntryCount[CpuIndex]++;
1243 }
1244
1245 //
1246 // Set new entry
1247 //
1248 PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));
1249 PageTable[PTIndex] |= (UINT64)IA32_PG_PS;
1250 PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;
1251 if ((ErrorCode & IA32_PF_EC_ID) != 0) {
1252 PageTable[PTIndex] &= ~IA32_PG_NX;
1253 }
1254 } else {
1255 //
1256 // Small page
1257 //
1258 ASSERT (PageTable[PTIndex] != 0);
1259 PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
1260
1261 //
1262 // 4K PTE
1263 //
1264 PTIndex = (UINTN)BitFieldRead64 (PFAddress, 12, 20);
1265
1266 //
1267 // Record old entries with non-present status
1268 // Old entries include the memory which instruction is at and the memory which instruction access.
1269 //
1270 //
1271 ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);
1272 if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {
1273 PFIndex = mPFEntryCount[CpuIndex];
1274 mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex];
1275 mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];
1276 mPFEntryCount[CpuIndex]++;
1277 }
1278
1279 //
1280 // Set new entry
1281 //
1282 PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));
1283 PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;
1284 if ((ErrorCode & IA32_PF_EC_ID) != 0) {
1285 PageTable[PTIndex] &= ~IA32_PG_NX;
1286 }
1287 }
1288 }
1289
1290 /**
1291 The Page fault handler to save SMM profile data.
1292
1293 @param Rip The RIP when exception happens.
1294 @param ErrorCode The Error code of exception.
1295
1296 **/
1297 VOID
1298 SmmProfilePFHandler (
1299 UINTN Rip,
1300 UINTN ErrorCode
1301 )
1302 {
1303 UINT64 *PageTable;
1304 UINT64 PFAddress;
1305 UINTN CpuIndex;
1306 UINTN Index;
1307 UINT64 InstructionAddress;
1308 UINTN MaxEntryNumber;
1309 UINTN CurrentEntryNumber;
1310 BOOLEAN IsValidPFAddress;
1311 SMM_PROFILE_ENTRY *SmmProfileEntry;
1312 UINT64 SmiCommand;
1313 EFI_STATUS Status;
1314 UINTN SwSmiCpuIndex;
1315 UINT8 SoftSmiValue;
1316 EFI_SMM_SAVE_STATE_IO_INFO IoInfo;
1317
1318 if (!mSmmProfileStart) {
1319 //
1320 // If SMM profile does not start, call original page fault handler.
1321 //
1322 SmiDefaultPFHandler ();
1323 return;
1324 }
1325
1326 if (mBtsSupported) {
1327 DisableBTS ();
1328 }
1329
1330 IsValidPFAddress = FALSE;
1331 PageTable = (UINT64 *)AsmReadCr3 ();
1332 PFAddress = AsmReadCr2 ();
1333 CpuIndex = GetCpuIndex ();
1334
1335 if (PFAddress <= 0xFFFFFFFF) {
1336 RestorePageTableBelow4G (PageTable, PFAddress, CpuIndex, ErrorCode);
1337 } else {
1338 RestorePageTableAbove4G (PageTable, PFAddress, CpuIndex, ErrorCode, &IsValidPFAddress);
1339 }
1340
1341 if (!IsValidPFAddress) {
1342 InstructionAddress = Rip;
1343 if ((ErrorCode & IA32_PF_EC_ID) != 0 && (mBtsSupported)) {
1344 //
1345 // If it is instruction fetch failure, get the correct IP from BTS.
1346 //
1347 InstructionAddress = GetSourceFromDestinationOnBts (CpuIndex, Rip);
1348 if (InstructionAddress == 0) {
1349 //
1350 // It indicates the instruction which caused page fault is not a jump instruction,
1351 // set instruction address same as the page fault address.
1352 //
1353 InstructionAddress = PFAddress;
1354 }
1355 }
1356
1357 //
1358 // Try to find which CPU trigger SWSMI
1359 //
1360 SwSmiCpuIndex = 0;
1361 //
1362 // Indicate it is not software SMI
1363 //
1364 SmiCommand = 0xFFFFFFFFFFFFFFFFULL;
1365 for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
1366 Status = SmmReadSaveState(&mSmmCpu, sizeof(IoInfo), EFI_SMM_SAVE_STATE_REGISTER_IO, Index, &IoInfo);
1367 if (EFI_ERROR (Status)) {
1368 continue;
1369 }
1370 if (IoInfo.IoPort == mSmiCommandPort) {
1371 //
1372 // Great! Find it.
1373 //
1374 SwSmiCpuIndex = Index;
1375 //
1376 // A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port.
1377 //
1378 SoftSmiValue = IoRead8 (mSmiCommandPort);
1379 SmiCommand = (UINT64)SoftSmiValue;
1380 break;
1381 }
1382 }
1383
1384 SmmProfileEntry = (SMM_PROFILE_ENTRY *)(UINTN)(mSmmProfileBase + 1);
1385 //
1386 // Check if there is already a same entry in profile data.
1387 //
1388 for (Index = 0; Index < (UINTN) mSmmProfileBase->CurDataEntries; Index++) {
1389 if ((SmmProfileEntry[Index].ErrorCode == (UINT64)ErrorCode) &&
1390 (SmmProfileEntry[Index].Address == PFAddress) &&
1391 (SmmProfileEntry[Index].CpuNum == (UINT64)CpuIndex) &&
1392 (SmmProfileEntry[Index].Instruction == InstructionAddress) &&
1393 (SmmProfileEntry[Index].SmiCmd == SmiCommand)) {
1394 //
1395 // Same record exist, need not save again.
1396 //
1397 break;
1398 }
1399 }
1400 if (Index == mSmmProfileBase->CurDataEntries) {
1401 CurrentEntryNumber = (UINTN) mSmmProfileBase->CurDataEntries;
1402 MaxEntryNumber = (UINTN) mSmmProfileBase->MaxDataEntries;
1403 if (FeaturePcdGet (PcdCpuSmmProfileRingBuffer)) {
1404 CurrentEntryNumber = CurrentEntryNumber % MaxEntryNumber;
1405 }
1406 if (CurrentEntryNumber < MaxEntryNumber) {
1407 //
1408 // Log the new entry
1409 //
1410 SmmProfileEntry[CurrentEntryNumber].SmiNum = mSmmProfileBase->NumSmis;
1411 SmmProfileEntry[CurrentEntryNumber].ErrorCode = (UINT64)ErrorCode;
1412 SmmProfileEntry[CurrentEntryNumber].ApicId = (UINT64)GetApicId ();
1413 SmmProfileEntry[CurrentEntryNumber].CpuNum = (UINT64)CpuIndex;
1414 SmmProfileEntry[CurrentEntryNumber].Address = PFAddress;
1415 SmmProfileEntry[CurrentEntryNumber].Instruction = InstructionAddress;
1416 SmmProfileEntry[CurrentEntryNumber].SmiCmd = SmiCommand;
1417 //
1418 // Update current entry index and data size in the header.
1419 //
1420 mSmmProfileBase->CurDataEntries++;
1421 mSmmProfileBase->CurDataSize = MultU64x64 (mSmmProfileBase->CurDataEntries, sizeof (SMM_PROFILE_ENTRY));
1422 }
1423 }
1424 }
1425 //
1426 // Flush TLB
1427 //
1428 CpuFlushTlb ();
1429
1430 if (mBtsSupported) {
1431 EnableBTS ();
1432 }
1433 }
1434
1435 /**
1436 Replace INT1 exception handler to restore page table to absent/execute-disable state
1437 in order to trigger page fault again to save SMM profile data..
1438
1439 **/
1440 VOID
1441 InitIdtr (
1442 VOID
1443 )
1444 {
1445 SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_DEBUG, DebugExceptionHandler);
1446 }
EFI Development Kit II mirror for PVE