4 Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
11 #include "PiSmmCpuDxeSmm.h"
12 #include "SmmProfileInternal.h"
14 UINT32 mSmmProfileCr3
;
16 SMM_PROFILE_HEADER
*mSmmProfileBase
;
17 MSR_DS_AREA_STRUCT
*mMsrDsAreaBase
;
19 // The buffer to store SMM profile data.
21 UINTN mSmmProfileSize
;
24 // The buffer to enable branch trace store.
26 UINTN mMsrDsAreaSize
= SMM_PROFILE_DTS_SIZE
;
29 // The flag indicates if execute-disable is supported by processor.
31 BOOLEAN mXdSupported
= TRUE
;
34 // The flag indicates if execute-disable is enabled on processor.
36 BOOLEAN mXdEnabled
= FALSE
;
39 // The flag indicates if BTS is supported by processor.
41 BOOLEAN mBtsSupported
= TRUE
;
44 // The flag indicates if SMM profile starts to record data.
46 BOOLEAN mSmmProfileStart
= FALSE
;
49 // The flag indicates if #DB will be setup in #PF handler.
51 BOOLEAN mSetupDebugTrap
= FALSE
;
54 // Record the page fault exception count for one instruction execution.
58 UINT64 (*mLastPFEntryValue
)[MAX_PF_ENTRY_COUNT
];
59 UINT64
*(*mLastPFEntryPointer
)[MAX_PF_ENTRY_COUNT
];
61 MSR_DS_AREA_STRUCT
**mMsrDsArea
;
62 BRANCH_TRACE_RECORD
**mMsrBTSRecord
;
63 UINTN mBTSRecordNumber
;
64 PEBS_RECORD
**mMsrPEBSRecord
;
67 // These memory ranges are always present, they does not generate the access type of page fault exception,
68 // but they possibly generate instruction fetch type of page fault exception.
70 MEMORY_PROTECTION_RANGE
*mProtectionMemRange
= NULL
;
71 UINTN mProtectionMemRangeCount
= 0;
74 // Some predefined memory ranges.
76 MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate
[] = {
78 // SMRAM range (to be fixed in runtime).
79 // It is always present and instruction fetches are allowed.
81 {{0x00000000, 0x00000000},TRUE
,FALSE
},
84 // SMM profile data range( to be fixed in runtime).
85 // It is always present and instruction fetches are not allowed.
87 {{0x00000000, 0x00000000},TRUE
,TRUE
},
90 // SMRAM ranges not covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime).
91 // It is always present and instruction fetches are allowed.
92 // {{0x00000000, 0x00000000},TRUE,FALSE},
96 // Future extended range could be added here.
100 // PCI MMIO ranges (to be added in runtime).
101 // They are always present and instruction fetches are not allowed.
106 // These memory ranges are mapped by 4KB-page instead of 2MB-page.
108 MEMORY_RANGE
*mSplitMemRange
= NULL
;
109 UINTN mSplitMemRangeCount
= 0;
114 UINT32 mSmiCommandPort
;
117 Disable branch trace store.
125 AsmMsrAnd64 (MSR_DEBUG_CTL
, ~((UINT64
)(MSR_DEBUG_CTL_BTS
| MSR_DEBUG_CTL_TR
)));
129 Enable branch trace store.
137 AsmMsrOr64 (MSR_DEBUG_CTL
, (MSR_DEBUG_CTL_BTS
| MSR_DEBUG_CTL_TR
));
141 Get CPU Index from APIC ID.
152 ApicId
= GetApicId ();
154 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
155 if (gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
== ApicId
) {
164 Get the source of IP after execute-disable exception is triggered.
166 @param CpuIndex The index of CPU.
167 @param DestinationIP The destination address.
171 GetSourceFromDestinationOnBts (
176 BRANCH_TRACE_RECORD
*CurrentBTSRecord
;
182 CurrentBTSRecord
= (BRANCH_TRACE_RECORD
*)mMsrDsArea
[CpuIndex
]->BTSIndex
;
183 for (Index
= 0; Index
< mBTSRecordNumber
; Index
++) {
184 if ((UINTN
)CurrentBTSRecord
< (UINTN
)mMsrBTSRecord
[CpuIndex
]) {
188 CurrentBTSRecord
= (BRANCH_TRACE_RECORD
*)((UINTN
)mMsrDsArea
[CpuIndex
]->BTSAbsoluteMaximum
- 1);
191 if (CurrentBTSRecord
->LastBranchTo
== DestinationIP
) {
193 // Good! find 1st one, then find 2nd one.
197 // The first one is DEBUG exception
202 // Good find proper one.
204 return CurrentBTSRecord
->LastBranchFrom
;
214 SMM profile specific INT 1 (single-step) exception handler.
216 @param InterruptType Defines the type of interrupt or exception that
217 occurred on the processor.This parameter is processor architecture specific.
218 @param SystemContext A pointer to the processor context when
219 the interrupt occurred on the processor.
223 DebugExceptionHandler (
224 IN EFI_EXCEPTION_TYPE InterruptType
,
225 IN EFI_SYSTEM_CONTEXT SystemContext
231 if (!mSmmProfileStart
&&
232 !HEAP_GUARD_NONSTOP_MODE
&&
233 !NULL_DETECTION_NONSTOP_MODE
) {
236 CpuIndex
= GetCpuIndex ();
239 // Clear last PF entries
241 for (PFEntry
= 0; PFEntry
< mPFEntryCount
[CpuIndex
]; PFEntry
++) {
242 *mLastPFEntryPointer
[CpuIndex
][PFEntry
] = mLastPFEntryValue
[CpuIndex
][PFEntry
];
246 // Reset page fault exception count for next page fault.
248 mPFEntryCount
[CpuIndex
] = 0;
256 // Clear TF in EFLAGS
258 ClearTrapFlag (SystemContext
);
262 Check if the input address is in SMM ranges.
264 @param[in] Address The input address.
266 @retval TRUE The input address is in SMM.
267 @retval FALSE The input address is not in SMM.
271 IN EFI_PHYSICAL_ADDRESS Address
276 if ((Address
>= mCpuHotPlugData
.SmrrBase
) && (Address
< mCpuHotPlugData
.SmrrBase
+ mCpuHotPlugData
.SmrrSize
)) {
279 for (Index
= 0; Index
< mSmmCpuSmramRangeCount
; Index
++) {
280 if (Address
>= mSmmCpuSmramRanges
[Index
].CpuStart
&&
281 Address
< mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
) {
289 Check if the memory address will be mapped by 4KB-page.
291 @param Address The address of Memory.
292 @param Nx The flag indicates if the memory is execute-disable.
297 IN EFI_PHYSICAL_ADDRESS Address
,
303 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
305 // Check configuration
307 for (Index
= 0; Index
< mProtectionMemRangeCount
; Index
++) {
308 if ((Address
>= mProtectionMemRange
[Index
].Range
.Base
) && (Address
< mProtectionMemRange
[Index
].Range
.Top
)) {
309 *Nx
= mProtectionMemRange
[Index
].Nx
;
310 return mProtectionMemRange
[Index
].Present
;
318 if (IsInSmmRanges (Address
)) {
326 Check if the memory address will be mapped by 4KB-page.
328 @param Address The address of Memory.
333 IN EFI_PHYSICAL_ADDRESS Address
338 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
340 // Check configuration
342 for (Index
= 0; Index
< mSplitMemRangeCount
; Index
++) {
343 if ((Address
>= mSplitMemRange
[Index
].Base
) && (Address
< mSplitMemRange
[Index
].Top
)) {
348 if (Address
< mCpuHotPlugData
.SmrrBase
) {
349 if ((mCpuHotPlugData
.SmrrBase
- Address
) < BASE_2MB
) {
352 } else if (Address
> (mCpuHotPlugData
.SmrrBase
+ mCpuHotPlugData
.SmrrSize
- BASE_2MB
)) {
353 if ((Address
- (mCpuHotPlugData
.SmrrBase
+ mCpuHotPlugData
.SmrrSize
- BASE_2MB
)) < BASE_2MB
) {
365 Initialize the protected memory ranges and the 4KB-page mapped memory ranges.
369 InitProtectedMemRange (
374 UINTN NumberOfDescriptors
;
375 UINTN NumberOfAddedDescriptors
;
376 UINTN NumberOfProtectRange
;
377 UINTN NumberOfSpliteRange
;
378 EFI_GCD_MEMORY_SPACE_DESCRIPTOR
*MemorySpaceMap
;
380 EFI_PHYSICAL_ADDRESS ProtectBaseAddress
;
381 EFI_PHYSICAL_ADDRESS ProtectEndAddress
;
382 EFI_PHYSICAL_ADDRESS Top2MBAlignedAddress
;
383 EFI_PHYSICAL_ADDRESS Base2MBAlignedAddress
;
384 UINT64 High4KBPageSize
;
385 UINT64 Low4KBPageSize
;
387 NumberOfDescriptors
= 0;
388 NumberOfAddedDescriptors
= mSmmCpuSmramRangeCount
;
389 NumberOfSpliteRange
= 0;
390 MemorySpaceMap
= NULL
;
393 // Get MMIO ranges from GCD and add them into protected memory ranges.
395 gDS
->GetMemorySpaceMap (
396 &NumberOfDescriptors
,
399 for (Index
= 0; Index
< NumberOfDescriptors
; Index
++) {
400 if (MemorySpaceMap
[Index
].GcdMemoryType
== EfiGcdMemoryTypeMemoryMappedIo
) {
401 NumberOfAddedDescriptors
++;
405 if (NumberOfAddedDescriptors
!= 0) {
406 TotalSize
= NumberOfAddedDescriptors
* sizeof (MEMORY_PROTECTION_RANGE
) + sizeof (mProtectionMemRangeTemplate
);
407 mProtectionMemRange
= (MEMORY_PROTECTION_RANGE
*) AllocateZeroPool (TotalSize
);
408 ASSERT (mProtectionMemRange
!= NULL
);
409 mProtectionMemRangeCount
= TotalSize
/ sizeof (MEMORY_PROTECTION_RANGE
);
412 // Copy existing ranges.
414 CopyMem (mProtectionMemRange
, mProtectionMemRangeTemplate
, sizeof (mProtectionMemRangeTemplate
));
417 // Create split ranges which come from protected ranges.
419 TotalSize
= (TotalSize
/ sizeof (MEMORY_PROTECTION_RANGE
)) * sizeof (MEMORY_RANGE
);
420 mSplitMemRange
= (MEMORY_RANGE
*) AllocateZeroPool (TotalSize
);
421 ASSERT (mSplitMemRange
!= NULL
);
424 // Create SMM ranges which are set to present and execution-enable.
426 NumberOfProtectRange
= sizeof (mProtectionMemRangeTemplate
) / sizeof (MEMORY_PROTECTION_RANGE
);
427 for (Index
= 0; Index
< mSmmCpuSmramRangeCount
; Index
++) {
428 if (mSmmCpuSmramRanges
[Index
].CpuStart
>= mProtectionMemRange
[0].Range
.Base
&&
429 mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
< mProtectionMemRange
[0].Range
.Top
) {
431 // If the address have been already covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz
435 mProtectionMemRange
[NumberOfProtectRange
].Range
.Base
= mSmmCpuSmramRanges
[Index
].CpuStart
;
436 mProtectionMemRange
[NumberOfProtectRange
].Range
.Top
= mSmmCpuSmramRanges
[Index
].CpuStart
+ mSmmCpuSmramRanges
[Index
].PhysicalSize
;
437 mProtectionMemRange
[NumberOfProtectRange
].Present
= TRUE
;
438 mProtectionMemRange
[NumberOfProtectRange
].Nx
= FALSE
;
439 NumberOfProtectRange
++;
443 // Create MMIO ranges which are set to present and execution-disable.
445 for (Index
= 0; Index
< NumberOfDescriptors
; Index
++) {
446 if (MemorySpaceMap
[Index
].GcdMemoryType
!= EfiGcdMemoryTypeMemoryMappedIo
) {
449 mProtectionMemRange
[NumberOfProtectRange
].Range
.Base
= MemorySpaceMap
[Index
].BaseAddress
;
450 mProtectionMemRange
[NumberOfProtectRange
].Range
.Top
= MemorySpaceMap
[Index
].BaseAddress
+ MemorySpaceMap
[Index
].Length
;
451 mProtectionMemRange
[NumberOfProtectRange
].Present
= TRUE
;
452 mProtectionMemRange
[NumberOfProtectRange
].Nx
= TRUE
;
453 NumberOfProtectRange
++;
457 // Check and updated actual protected memory ranges count
459 ASSERT (NumberOfProtectRange
<= mProtectionMemRangeCount
);
460 mProtectionMemRangeCount
= NumberOfProtectRange
;
464 // According to protected ranges, create the ranges which will be mapped by 2KB page.
466 NumberOfSpliteRange
= 0;
467 NumberOfProtectRange
= mProtectionMemRangeCount
;
468 for (Index
= 0; Index
< NumberOfProtectRange
; Index
++) {
470 // If MMIO base address is not 2MB alignment, make 2MB alignment for create 4KB page in page table.
472 ProtectBaseAddress
= mProtectionMemRange
[Index
].Range
.Base
;
473 ProtectEndAddress
= mProtectionMemRange
[Index
].Range
.Top
;
474 if (((ProtectBaseAddress
& (SIZE_2MB
- 1)) != 0) || ((ProtectEndAddress
& (SIZE_2MB
- 1)) != 0)) {
476 // Check if it is possible to create 4KB-page for not 2MB-aligned range and to create 2MB-page for 2MB-aligned range.
477 // A mix of 4KB and 2MB page could save SMRAM space.
479 Top2MBAlignedAddress
= ProtectEndAddress
& ~(SIZE_2MB
- 1);
480 Base2MBAlignedAddress
= (ProtectBaseAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1);
481 if ((Top2MBAlignedAddress
> Base2MBAlignedAddress
) &&
482 ((Top2MBAlignedAddress
- Base2MBAlignedAddress
) >= SIZE_2MB
)) {
484 // There is an range which could be mapped by 2MB-page.
486 High4KBPageSize
= ((ProtectEndAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1)) - (ProtectEndAddress
& ~(SIZE_2MB
- 1));
487 Low4KBPageSize
= ((ProtectBaseAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1)) - (ProtectBaseAddress
& ~(SIZE_2MB
- 1));
488 if (High4KBPageSize
!= 0) {
490 // Add not 2MB-aligned range to be mapped by 4KB-page.
492 mSplitMemRange
[NumberOfSpliteRange
].Base
= ProtectEndAddress
& ~(SIZE_2MB
- 1);
493 mSplitMemRange
[NumberOfSpliteRange
].Top
= (ProtectEndAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1);
494 NumberOfSpliteRange
++;
496 if (Low4KBPageSize
!= 0) {
498 // Add not 2MB-aligned range to be mapped by 4KB-page.
500 mSplitMemRange
[NumberOfSpliteRange
].Base
= ProtectBaseAddress
& ~(SIZE_2MB
- 1);
501 mSplitMemRange
[NumberOfSpliteRange
].Top
= (ProtectBaseAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1);
502 NumberOfSpliteRange
++;
506 // The range could only be mapped by 4KB-page.
508 mSplitMemRange
[NumberOfSpliteRange
].Base
= ProtectBaseAddress
& ~(SIZE_2MB
- 1);
509 mSplitMemRange
[NumberOfSpliteRange
].Top
= (ProtectEndAddress
+ SIZE_2MB
- 1) & ~(SIZE_2MB
- 1);
510 NumberOfSpliteRange
++;
515 mSplitMemRangeCount
= NumberOfSpliteRange
;
517 DEBUG ((EFI_D_INFO
, "SMM Profile Memory Ranges:\n"));
518 for (Index
= 0; Index
< mProtectionMemRangeCount
; Index
++) {
519 DEBUG ((EFI_D_INFO
, "mProtectionMemRange[%d].Base = %lx\n", Index
, mProtectionMemRange
[Index
].Range
.Base
));
520 DEBUG ((EFI_D_INFO
, "mProtectionMemRange[%d].Top = %lx\n", Index
, mProtectionMemRange
[Index
].Range
.Top
));
522 for (Index
= 0; Index
< mSplitMemRangeCount
; Index
++) {
523 DEBUG ((EFI_D_INFO
, "mSplitMemRange[%d].Base = %lx\n", Index
, mSplitMemRange
[Index
].Base
));
524 DEBUG ((EFI_D_INFO
, "mSplitMemRange[%d].Top = %lx\n", Index
, mSplitMemRange
[Index
].Top
));
529 Update page table according to protected memory ranges and the 4KB-page mapped memory ranges.
550 UINTN NumberOfPdptEntries
;
551 UINTN NumberOfPml4Entries
;
552 UINTN NumberOfPml5Entries
;
553 UINTN SizeOfMemorySpace
;
556 BOOLEAN Enable5LevelPaging
;
558 Cr4
.UintN
= AsmReadCr4 ();
559 Enable5LevelPaging
= (BOOLEAN
) (Cr4
.Bits
.LA57
== 1);
561 if (sizeof (UINTN
) == sizeof (UINT64
)) {
562 if (!Enable5LevelPaging
) {
563 Pml5Entry
= (UINTN
) mSmmProfileCr3
| IA32_PG_P
;
566 Pml5
= (UINT64
*) (UINTN
) mSmmProfileCr3
;
568 SizeOfMemorySpace
= HighBitSet64 (gPhyMask
) + 1;
570 // Calculate the table entries of PML4E and PDPTE.
572 NumberOfPml5Entries
= 1;
573 if (SizeOfMemorySpace
> 48) {
574 NumberOfPml5Entries
= (UINTN
) LShiftU64 (1, SizeOfMemorySpace
- 48);
575 SizeOfMemorySpace
= 48;
578 NumberOfPml4Entries
= 1;
579 if (SizeOfMemorySpace
> 39) {
580 NumberOfPml4Entries
= (UINTN
) LShiftU64 (1, SizeOfMemorySpace
- 39);
581 SizeOfMemorySpace
= 39;
584 NumberOfPdptEntries
= 1;
585 ASSERT (SizeOfMemorySpace
> 30);
586 NumberOfPdptEntries
= (UINTN
) LShiftU64 (1, SizeOfMemorySpace
- 30);
588 Pml4Entry
= (UINTN
) mSmmProfileCr3
| IA32_PG_P
;
590 Pml5Entry
= (UINTN
) Pml4
| IA32_PG_P
;
592 NumberOfPml5Entries
= 1;
593 NumberOfPml4Entries
= 1;
594 NumberOfPdptEntries
= 4;
598 // Go through page table and change 2MB-page into 4KB-page.
600 for (Pml5Index
= 0; Pml5Index
< NumberOfPml5Entries
; Pml5Index
++) {
601 if ((Pml5
[Pml5Index
] & IA32_PG_P
) == 0) {
603 // If PML5 entry does not exist, skip it
607 Pml4
= (UINT64
*) (UINTN
) (Pml5
[Pml5Index
] & PHYSICAL_ADDRESS_MASK
);
608 for (Pml4Index
= 0; Pml4Index
< NumberOfPml4Entries
; Pml4Index
++) {
609 if ((Pml4
[Pml4Index
] & IA32_PG_P
) == 0) {
611 // If PML4 entry does not exist, skip it
615 Pdpt
= (UINT64
*)(UINTN
)(Pml4
[Pml4Index
] & ~mAddressEncMask
& PHYSICAL_ADDRESS_MASK
);
616 for (PdptIndex
= 0; PdptIndex
< NumberOfPdptEntries
; PdptIndex
++, Pdpt
++) {
617 if ((*Pdpt
& IA32_PG_P
) == 0) {
619 // If PDPT entry does not exist, skip it
623 if ((*Pdpt
& IA32_PG_PS
) != 0) {
625 // This is 1G entry, skip it
629 Pd
= (UINT64
*)(UINTN
)(*Pdpt
& ~mAddressEncMask
& PHYSICAL_ADDRESS_MASK
);
633 for (PdIndex
= 0; PdIndex
< SIZE_4KB
/ sizeof (*Pd
); PdIndex
++, Pd
++) {
634 if ((*Pd
& IA32_PG_P
) == 0) {
636 // If PD entry does not exist, skip it
640 Address
= (UINTN
) LShiftU64 (
642 LShiftU64 ((Pml5Index
<< 9) + Pml4Index
, 9) + PdptIndex
,
649 // If it is 2M page, check IsAddressSplit()
651 if (((*Pd
& IA32_PG_PS
) != 0) && IsAddressSplit (Address
)) {
653 // Based on current page table, create 4KB page table for split area.
655 ASSERT (Address
== (*Pd
& PHYSICAL_ADDRESS_MASK
));
657 Pt
= AllocatePageTableMemory (1);
660 *Pd
= (UINTN
) Pt
| IA32_PG_RW
| IA32_PG_P
;
663 for (PtIndex
= 0; PtIndex
< SIZE_4KB
/ sizeof(*Pt
); PtIndex
++, Pt
++) {
664 *Pt
= Address
+ ((PtIndex
<< 12) | mAddressEncMask
| PAGE_ATTRIBUTE_BITS
);
666 *Pd
= (UINT64
)(UINTN
)Pt
| mAddressEncMask
| PAGE_ATTRIBUTE_BITS
;
667 } // end if IsAddressSplit
674 // Go through page table and set several page table entries to absent or execute-disable.
676 DEBUG ((EFI_D_INFO
, "Patch page table start ...\n"));
677 for (Pml5Index
= 0; Pml5Index
< NumberOfPml5Entries
; Pml5Index
++) {
678 if ((Pml5
[Pml5Index
] & IA32_PG_P
) == 0) {
680 // If PML5 entry does not exist, skip it
684 Pml4
= (UINT64
*) (UINTN
) (Pml5
[Pml5Index
] & PHYSICAL_ADDRESS_MASK
);
685 for (Pml4Index
= 0; Pml4Index
< NumberOfPml4Entries
; Pml4Index
++) {
686 if ((Pml4
[Pml4Index
] & IA32_PG_P
) == 0) {
688 // If PML4 entry does not exist, skip it
692 Pdpt
= (UINT64
*)(UINTN
)(Pml4
[Pml4Index
] & ~mAddressEncMask
& PHYSICAL_ADDRESS_MASK
);
693 for (PdptIndex
= 0; PdptIndex
< NumberOfPdptEntries
; PdptIndex
++, Pdpt
++) {
694 if ((*Pdpt
& IA32_PG_P
) == 0) {
696 // If PDPT entry does not exist, skip it
700 if ((*Pdpt
& IA32_PG_PS
) != 0) {
702 // This is 1G entry, set NX bit and skip it
705 *Pdpt
= *Pdpt
| IA32_PG_NX
;
709 Pd
= (UINT64
*)(UINTN
)(*Pdpt
& ~mAddressEncMask
& PHYSICAL_ADDRESS_MASK
);
713 for (PdIndex
= 0; PdIndex
< SIZE_4KB
/ sizeof (*Pd
); PdIndex
++, Pd
++) {
714 if ((*Pd
& IA32_PG_P
) == 0) {
716 // If PD entry does not exist, skip it
720 Address
= (UINTN
) LShiftU64 (
722 LShiftU64 ((Pml5Index
<< 9) + Pml4Index
, 9) + PdptIndex
,
728 if ((*Pd
& IA32_PG_PS
) != 0) {
731 if (!IsAddressValid (Address
, &Nx
)) {
733 // Patch to remove Present flag and RW flag
735 *Pd
= *Pd
& (INTN
)(INT32
)(~PAGE_ATTRIBUTE_BITS
);
737 if (Nx
&& mXdSupported
) {
738 *Pd
= *Pd
| IA32_PG_NX
;
742 Pt
= (UINT64
*)(UINTN
)(*Pd
& ~mAddressEncMask
& PHYSICAL_ADDRESS_MASK
);
746 for (PtIndex
= 0; PtIndex
< SIZE_4KB
/ sizeof(*Pt
); PtIndex
++, Pt
++) {
747 if (!IsAddressValid (Address
, &Nx
)) {
748 *Pt
= *Pt
& (INTN
)(INT32
)(~PAGE_ATTRIBUTE_BITS
);
750 if (Nx
&& mXdSupported
) {
751 *Pt
= *Pt
| IA32_PG_NX
;
765 DEBUG ((EFI_D_INFO
, "Patch page table done!\n"));
767 // Set execute-disable flag
775 To get system port address of the SMI Command Port in FADT table.
783 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE
*Fadt
;
785 Fadt
= (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE
*) EfiLocateFirstAcpiTable (
786 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE
788 ASSERT (Fadt
!= NULL
);
790 mSmiCommandPort
= Fadt
->SmiCmd
;
791 DEBUG ((EFI_D_INFO
, "mSmiCommandPort = %x\n", mSmiCommandPort
));
795 Updates page table to make some memory ranges (like system memory) absent
796 and make some memory ranges (like MMIO) present and execute disable. It also
797 update 2MB-page to 4KB-page for some memory ranges.
806 // The flag indicates SMM profile starts to work.
808 mSmmProfileStart
= TRUE
;
812 Initialize SMM profile in SmmReadyToLock protocol callback function.
814 @param Protocol Points to the protocol's unique identifier.
815 @param Interface Points to the interface instance.
816 @param Handle The handle on which the interface was installed.
818 @retval EFI_SUCCESS SmmReadyToLock protocol callback runs successfully.
822 InitSmmProfileCallBack (
823 IN CONST EFI_GUID
*Protocol
,
829 // Save to variable so that SMM profile data can be found.
834 EFI_VARIABLE_BOOTSERVICE_ACCESS
| EFI_VARIABLE_RUNTIME_ACCESS
,
835 sizeof(mSmmProfileBase
),
840 // Get Software SMI from FADT
842 GetSmiCommandPort ();
845 // Initialize protected memory range for patching page table later.
847 InitProtectedMemRange ();
853 Initialize SMM profile data structures.
857 InitSmmProfileInternal (
862 EFI_PHYSICAL_ADDRESS Base
;
865 UINTN MsrDsAreaSizePerCpu
;
868 mPFEntryCount
= (UINTN
*)AllocateZeroPool (sizeof (UINTN
) * mMaxNumberOfCpus
);
869 ASSERT (mPFEntryCount
!= NULL
);
870 mLastPFEntryValue
= (UINT64 (*)[MAX_PF_ENTRY_COUNT
])AllocateZeroPool (
871 sizeof (mLastPFEntryValue
[0]) * mMaxNumberOfCpus
);
872 ASSERT (mLastPFEntryValue
!= NULL
);
873 mLastPFEntryPointer
= (UINT64
*(*)[MAX_PF_ENTRY_COUNT
])AllocateZeroPool (
874 sizeof (mLastPFEntryPointer
[0]) * mMaxNumberOfCpus
);
875 ASSERT (mLastPFEntryPointer
!= NULL
);
878 // Allocate memory for SmmProfile below 4GB.
881 mSmmProfileSize
= PcdGet32 (PcdCpuSmmProfileSize
);
882 ASSERT ((mSmmProfileSize
& 0xFFF) == 0);
885 TotalSize
= mSmmProfileSize
+ mMsrDsAreaSize
;
887 TotalSize
= mSmmProfileSize
;
891 Status
= gBS
->AllocatePages (
893 EfiReservedMemoryType
,
894 EFI_SIZE_TO_PAGES (TotalSize
),
897 ASSERT_EFI_ERROR (Status
);
898 ZeroMem ((VOID
*)(UINTN
)Base
, TotalSize
);
899 mSmmProfileBase
= (SMM_PROFILE_HEADER
*)(UINTN
)Base
;
902 // Initialize SMM profile data header.
904 mSmmProfileBase
->HeaderSize
= sizeof (SMM_PROFILE_HEADER
);
905 mSmmProfileBase
->MaxDataEntries
= (UINT64
)((mSmmProfileSize
- sizeof(SMM_PROFILE_HEADER
)) / sizeof (SMM_PROFILE_ENTRY
));
906 mSmmProfileBase
->MaxDataSize
= MultU64x64 (mSmmProfileBase
->MaxDataEntries
, sizeof(SMM_PROFILE_ENTRY
));
907 mSmmProfileBase
->CurDataEntries
= 0;
908 mSmmProfileBase
->CurDataSize
= 0;
909 mSmmProfileBase
->TsegStart
= mCpuHotPlugData
.SmrrBase
;
910 mSmmProfileBase
->TsegSize
= mCpuHotPlugData
.SmrrSize
;
911 mSmmProfileBase
->NumSmis
= 0;
912 mSmmProfileBase
->NumCpus
= gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
;
915 mMsrDsArea
= (MSR_DS_AREA_STRUCT
**)AllocateZeroPool (sizeof (MSR_DS_AREA_STRUCT
*) * mMaxNumberOfCpus
);
916 ASSERT (mMsrDsArea
!= NULL
);
917 mMsrBTSRecord
= (BRANCH_TRACE_RECORD
**)AllocateZeroPool (sizeof (BRANCH_TRACE_RECORD
*) * mMaxNumberOfCpus
);
918 ASSERT (mMsrBTSRecord
!= NULL
);
919 mMsrPEBSRecord
= (PEBS_RECORD
**)AllocateZeroPool (sizeof (PEBS_RECORD
*) * mMaxNumberOfCpus
);
920 ASSERT (mMsrPEBSRecord
!= NULL
);
922 mMsrDsAreaBase
= (MSR_DS_AREA_STRUCT
*)((UINTN
)Base
+ mSmmProfileSize
);
923 MsrDsAreaSizePerCpu
= mMsrDsAreaSize
/ mMaxNumberOfCpus
;
924 mBTSRecordNumber
= (MsrDsAreaSizePerCpu
- sizeof(PEBS_RECORD
) * PEBS_RECORD_NUMBER
- sizeof(MSR_DS_AREA_STRUCT
)) / sizeof(BRANCH_TRACE_RECORD
);
925 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
926 mMsrDsArea
[Index
] = (MSR_DS_AREA_STRUCT
*)((UINTN
)mMsrDsAreaBase
+ MsrDsAreaSizePerCpu
* Index
);
927 mMsrBTSRecord
[Index
] = (BRANCH_TRACE_RECORD
*)((UINTN
)mMsrDsArea
[Index
] + sizeof(MSR_DS_AREA_STRUCT
));
928 mMsrPEBSRecord
[Index
] = (PEBS_RECORD
*)((UINTN
)mMsrDsArea
[Index
] + MsrDsAreaSizePerCpu
- sizeof(PEBS_RECORD
) * PEBS_RECORD_NUMBER
);
930 mMsrDsArea
[Index
]->BTSBufferBase
= (UINTN
)mMsrBTSRecord
[Index
];
931 mMsrDsArea
[Index
]->BTSIndex
= mMsrDsArea
[Index
]->BTSBufferBase
;
932 mMsrDsArea
[Index
]->BTSAbsoluteMaximum
= mMsrDsArea
[Index
]->BTSBufferBase
+ mBTSRecordNumber
* sizeof(BRANCH_TRACE_RECORD
) + 1;
933 mMsrDsArea
[Index
]->BTSInterruptThreshold
= mMsrDsArea
[Index
]->BTSAbsoluteMaximum
+ 1;
935 mMsrDsArea
[Index
]->PEBSBufferBase
= (UINTN
)mMsrPEBSRecord
[Index
];
936 mMsrDsArea
[Index
]->PEBSIndex
= mMsrDsArea
[Index
]->PEBSBufferBase
;
937 mMsrDsArea
[Index
]->PEBSAbsoluteMaximum
= mMsrDsArea
[Index
]->PEBSBufferBase
+ PEBS_RECORD_NUMBER
* sizeof(PEBS_RECORD
) + 1;
938 mMsrDsArea
[Index
]->PEBSInterruptThreshold
= mMsrDsArea
[Index
]->PEBSAbsoluteMaximum
+ 1;
942 mProtectionMemRange
= mProtectionMemRangeTemplate
;
943 mProtectionMemRangeCount
= sizeof (mProtectionMemRangeTemplate
) / sizeof (MEMORY_PROTECTION_RANGE
);
946 // Update TSeg entry.
948 mProtectionMemRange
[0].Range
.Base
= mCpuHotPlugData
.SmrrBase
;
949 mProtectionMemRange
[0].Range
.Top
= mCpuHotPlugData
.SmrrBase
+ mCpuHotPlugData
.SmrrSize
;
952 // Update SMM profile entry.
954 mProtectionMemRange
[1].Range
.Base
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)mSmmProfileBase
;
955 mProtectionMemRange
[1].Range
.Top
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)mSmmProfileBase
+ TotalSize
;
958 // Allocate memory reserved for creating 4KB pages.
960 InitPagesForPFHandler ();
963 // Start SMM profile when SmmReadyToLock protocol is installed.
965 Status
= gSmst
->SmmRegisterProtocolNotify (
966 &gEfiSmmReadyToLockProtocolGuid
,
967 InitSmmProfileCallBack
,
970 ASSERT_EFI_ERROR (Status
);
976 Check if feature is supported by a processor.
980 CheckFeatureSupported (
987 MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr
;
989 if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask
) != 0) && mCetSupported
) {
990 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
991 if (RegEax
<= CPUID_EXTENDED_FUNCTION
) {
992 mCetSupported
= FALSE
;
993 PatchInstructionX86 (mPatchCetSupported
, mCetSupported
, 1);
995 AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO
, NULL
, NULL
, &RegEcx
, NULL
);
996 if ((RegEcx
& CPUID_CET_SS
) == 0) {
997 mCetSupported
= FALSE
;
998 PatchInstructionX86 (mPatchCetSupported
, mCetSupported
, 1);
1003 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
1004 if (RegEax
<= CPUID_EXTENDED_FUNCTION
) {
1006 // Extended CPUID functions are not supported on this processor.
1008 mXdSupported
= FALSE
;
1009 PatchInstructionX86 (gPatchXdSupported
, mXdSupported
, 1);
1012 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
1013 if ((RegEdx
& CPUID1_EDX_XD_SUPPORT
) == 0) {
1015 // Execute Disable Bit feature is not supported on this processor.
1017 mXdSupported
= FALSE
;
1018 PatchInstructionX86 (gPatchXdSupported
, mXdSupported
, 1);
1022 if (mBtsSupported
) {
1023 AsmCpuid (CPUID_VERSION_INFO
, NULL
, NULL
, NULL
, &RegEdx
);
1024 if ((RegEdx
& CPUID1_EDX_BTS_AVAILABLE
) != 0) {
1026 // Per IA32 manuals:
1027 // When CPUID.1:EDX[21] is set, the following BTS facilities are available:
1028 // 1. The BTS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates the
1029 // availability of the BTS facilities, including the ability to set the BTS and
1030 // BTINT bits in the MSR_DEBUGCTLA MSR.
1031 // 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area.
1033 MiscEnableMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_MISC_ENABLE
);
1034 if (MiscEnableMsr
.Bits
.BTS
== 1) {
1036 // BTS facilities is not supported if MSR_IA32_MISC_ENABLE.BTS bit is set.
1038 mBtsSupported
= FALSE
;
1049 ActivateSingleStepDB (
1055 Dr6
= AsmReadDr6 ();
1056 if ((Dr6
& DR6_SINGLE_STEP
) != 0) {
1059 Dr6
|= DR6_SINGLE_STEP
;
1074 DebugCtl
= AsmReadMsr64 (MSR_DEBUG_CTL
);
1075 if ((DebugCtl
& MSR_DEBUG_CTL_LBR
) != 0) {
1078 DebugCtl
|= MSR_DEBUG_CTL_LBR
;
1079 AsmWriteMsr64 (MSR_DEBUG_CTL
, DebugCtl
);
1083 Enable branch trace store.
1085 @param CpuIndex The index of the processor.
1095 DebugCtl
= AsmReadMsr64 (MSR_DEBUG_CTL
);
1096 if ((DebugCtl
& MSR_DEBUG_CTL_BTS
) != 0) {
1100 AsmWriteMsr64 (MSR_DS_AREA
, (UINT64
)(UINTN
)mMsrDsArea
[CpuIndex
]);
1101 DebugCtl
|= (UINT64
)(MSR_DEBUG_CTL_BTS
| MSR_DEBUG_CTL_TR
);
1102 DebugCtl
&= ~((UINT64
)MSR_DEBUG_CTL_BTINT
);
1103 AsmWriteMsr64 (MSR_DEBUG_CTL
, DebugCtl
);
1107 Increase SMI number in each SMI entry.
1111 SmmProfileRecordSmiNum (
1115 if (mSmmProfileStart
) {
1116 mSmmProfileBase
->NumSmis
++;
1121 Initialize processor environment for SMM profile.
1123 @param CpuIndex The index of the processor.
1127 ActivateSmmProfile (
1132 // Enable Single Step DB#
1134 ActivateSingleStepDB ();
1136 if (mBtsSupported
) {
1138 // We can not get useful information from LER, so we have to use BTS.
1145 ActivateBTS (CpuIndex
);
1150 Initialize SMM profile in SMM CPU entry point.
1152 @param[in] Cr3 The base address of the page tables to use in SMM.
1163 mSmmProfileCr3
= Cr3
;
1166 // Skip SMM profile initialization if feature is disabled
1168 if (!FeaturePcdGet (PcdCpuSmmProfileEnable
) &&
1169 !HEAP_GUARD_NONSTOP_MODE
&&
1170 !NULL_DETECTION_NONSTOP_MODE
) {
1175 // Initialize SmmProfile here
1177 InitSmmProfileInternal ();
1180 // Initialize profile IDT.
1185 // Tell #PF handler to prepare a #DB subsequently.
1187 mSetupDebugTrap
= TRUE
;
1191 Update page table to map the memory correctly in order to make the instruction
1192 which caused page fault execute successfully. And it also save the original page
1193 table to be restored in single-step exception.
1195 @param PageTable PageTable Address.
1196 @param PFAddress The memory address which caused page fault exception.
1197 @param CpuIndex The index of the processor.
1198 @param ErrorCode The Error code of exception.
1202 RestorePageTableBelow4G (
1212 BOOLEAN Enable5LevelPaging
;
1214 Cr4
.UintN
= AsmReadCr4 ();
1215 Enable5LevelPaging
= (BOOLEAN
) (Cr4
.Bits
.LA57
== 1);
1220 if (Enable5LevelPaging
) {
1221 PTIndex
= (UINTN
)BitFieldRead64 (PFAddress
, 48, 56);
1222 ASSERT (PageTable
[PTIndex
] != 0);
1223 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
1229 if (sizeof(UINT64
) == sizeof(UINTN
)) {
1230 PTIndex
= (UINTN
)BitFieldRead64 (PFAddress
, 39, 47);
1231 ASSERT (PageTable
[PTIndex
] != 0);
1232 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
1238 PTIndex
= (UINTN
)BitFieldRead64 (PFAddress
, 30, 38);
1239 ASSERT (PageTable
[PTIndex
] != 0);
1240 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
1245 PTIndex
= (UINTN
)BitFieldRead64 (PFAddress
, 21, 29);
1246 if ((PageTable
[PTIndex
] & IA32_PG_PS
) != 0) {
1252 // Record old entries with non-present status
1253 // Old entries include the memory which instruction is at and the memory which instruction access.
1256 ASSERT (mPFEntryCount
[CpuIndex
] < MAX_PF_ENTRY_COUNT
);
1257 if (mPFEntryCount
[CpuIndex
] < MAX_PF_ENTRY_COUNT
) {
1258 PFIndex
= mPFEntryCount
[CpuIndex
];
1259 mLastPFEntryValue
[CpuIndex
][PFIndex
] = PageTable
[PTIndex
];
1260 mLastPFEntryPointer
[CpuIndex
][PFIndex
] = &PageTable
[PTIndex
];
1261 mPFEntryCount
[CpuIndex
]++;
1267 PageTable
[PTIndex
] = (PFAddress
& ~((1ull << 21) - 1));
1268 PageTable
[PTIndex
] |= (UINT64
)IA32_PG_PS
;
1269 PageTable
[PTIndex
] |= (UINT64
)PAGE_ATTRIBUTE_BITS
;
1270 if ((ErrorCode
& IA32_PF_EC_ID
) != 0) {
1271 PageTable
[PTIndex
] &= ~IA32_PG_NX
;
1277 ASSERT (PageTable
[PTIndex
] != 0);
1278 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
1283 PTIndex
= (UINTN
)BitFieldRead64 (PFAddress
, 12, 20);
1286 // Record old entries with non-present status
1287 // Old entries include the memory which instruction is at and the memory which instruction access.
1290 ASSERT (mPFEntryCount
[CpuIndex
] < MAX_PF_ENTRY_COUNT
);
1291 if (mPFEntryCount
[CpuIndex
] < MAX_PF_ENTRY_COUNT
) {
1292 PFIndex
= mPFEntryCount
[CpuIndex
];
1293 mLastPFEntryValue
[CpuIndex
][PFIndex
] = PageTable
[PTIndex
];
1294 mLastPFEntryPointer
[CpuIndex
][PFIndex
] = &PageTable
[PTIndex
];
1295 mPFEntryCount
[CpuIndex
]++;
1301 PageTable
[PTIndex
] = (PFAddress
& ~((1ull << 12) - 1));
1302 PageTable
[PTIndex
] |= (UINT64
)PAGE_ATTRIBUTE_BITS
;
1303 if ((ErrorCode
& IA32_PF_EC_ID
) != 0) {
1304 PageTable
[PTIndex
] &= ~IA32_PG_NX
;
1310 Handler for Page Fault triggered by Guard page.
1312 @param ErrorCode The Error code of exception.
1316 GuardPagePFHandler (
1322 UINT64 RestoreAddress
;
1323 UINTN RestorePageNumber
;
1326 PageTable
= (UINT64
*)AsmReadCr3 ();
1327 PFAddress
= AsmReadCr2 ();
1328 CpuIndex
= GetCpuIndex ();
1331 // Memory operation cross pages, like "rep mov" instruction, will cause
1332 // infinite loop between this and Debug Trap handler. We have to make sure
1333 // that current page and the page followed are both in PRESENT state.
1335 RestorePageNumber
= 2;
1336 RestoreAddress
= PFAddress
;
1337 while (RestorePageNumber
> 0) {
1338 RestorePageTableBelow4G (PageTable
, RestoreAddress
, CpuIndex
, ErrorCode
);
1339 RestoreAddress
+= EFI_PAGE_SIZE
;
1340 RestorePageNumber
--;
1350 The Page fault handler to save SMM profile data.
1352 @param Rip The RIP when exception happens.
1353 @param ErrorCode The Error code of exception.
1357 SmmProfilePFHandler (
1364 UINT64 RestoreAddress
;
1365 UINTN RestorePageNumber
;
1368 UINT64 InstructionAddress
;
1369 UINTN MaxEntryNumber
;
1370 UINTN CurrentEntryNumber
;
1371 BOOLEAN IsValidPFAddress
;
1372 SMM_PROFILE_ENTRY
*SmmProfileEntry
;
1376 EFI_SMM_SAVE_STATE_IO_INFO IoInfo
;
1378 if (!mSmmProfileStart
) {
1380 // If SMM profile does not start, call original page fault handler.
1382 SmiDefaultPFHandler ();
1386 if (mBtsSupported
) {
1390 IsValidPFAddress
= FALSE
;
1391 PageTable
= (UINT64
*)AsmReadCr3 ();
1392 PFAddress
= AsmReadCr2 ();
1393 CpuIndex
= GetCpuIndex ();
1396 // Memory operation cross pages, like "rep mov" instruction, will cause
1397 // infinite loop between this and Debug Trap handler. We have to make sure
1398 // that current page and the page followed are both in PRESENT state.
1400 RestorePageNumber
= 2;
1401 RestoreAddress
= PFAddress
;
1402 while (RestorePageNumber
> 0) {
1403 if (RestoreAddress
<= 0xFFFFFFFF) {
1404 RestorePageTableBelow4G (PageTable
, RestoreAddress
, CpuIndex
, ErrorCode
);
1406 RestorePageTableAbove4G (PageTable
, RestoreAddress
, CpuIndex
, ErrorCode
, &IsValidPFAddress
);
1408 RestoreAddress
+= EFI_PAGE_SIZE
;
1409 RestorePageNumber
--;
1412 if (!IsValidPFAddress
) {
1413 InstructionAddress
= Rip
;
1414 if ((ErrorCode
& IA32_PF_EC_ID
) != 0 && (mBtsSupported
)) {
1416 // If it is instruction fetch failure, get the correct IP from BTS.
1418 InstructionAddress
= GetSourceFromDestinationOnBts (CpuIndex
, Rip
);
1419 if (InstructionAddress
== 0) {
1421 // It indicates the instruction which caused page fault is not a jump instruction,
1422 // set instruction address same as the page fault address.
1424 InstructionAddress
= PFAddress
;
1429 // Indicate it is not software SMI
1431 SmiCommand
= 0xFFFFFFFFFFFFFFFFULL
;
1432 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1433 Status
= SmmReadSaveState(&mSmmCpu
, sizeof(IoInfo
), EFI_SMM_SAVE_STATE_REGISTER_IO
, Index
, &IoInfo
);
1434 if (EFI_ERROR (Status
)) {
1437 if (IoInfo
.IoPort
== mSmiCommandPort
) {
1439 // A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port.
1441 SoftSmiValue
= IoRead8 (mSmiCommandPort
);
1442 SmiCommand
= (UINT64
)SoftSmiValue
;
1447 SmmProfileEntry
= (SMM_PROFILE_ENTRY
*)(UINTN
)(mSmmProfileBase
+ 1);
1449 // Check if there is already a same entry in profile data.
1451 for (Index
= 0; Index
< (UINTN
) mSmmProfileBase
->CurDataEntries
; Index
++) {
1452 if ((SmmProfileEntry
[Index
].ErrorCode
== (UINT64
)ErrorCode
) &&
1453 (SmmProfileEntry
[Index
].Address
== PFAddress
) &&
1454 (SmmProfileEntry
[Index
].CpuNum
== (UINT64
)CpuIndex
) &&
1455 (SmmProfileEntry
[Index
].Instruction
== InstructionAddress
) &&
1456 (SmmProfileEntry
[Index
].SmiCmd
== SmiCommand
)) {
1458 // Same record exist, need not save again.
1463 if (Index
== mSmmProfileBase
->CurDataEntries
) {
1464 CurrentEntryNumber
= (UINTN
) mSmmProfileBase
->CurDataEntries
;
1465 MaxEntryNumber
= (UINTN
) mSmmProfileBase
->MaxDataEntries
;
1466 if (FeaturePcdGet (PcdCpuSmmProfileRingBuffer
)) {
1467 CurrentEntryNumber
= CurrentEntryNumber
% MaxEntryNumber
;
1469 if (CurrentEntryNumber
< MaxEntryNumber
) {
1471 // Log the new entry
1473 SmmProfileEntry
[CurrentEntryNumber
].SmiNum
= mSmmProfileBase
->NumSmis
;
1474 SmmProfileEntry
[CurrentEntryNumber
].ErrorCode
= (UINT64
)ErrorCode
;
1475 SmmProfileEntry
[CurrentEntryNumber
].ApicId
= (UINT64
)GetApicId ();
1476 SmmProfileEntry
[CurrentEntryNumber
].CpuNum
= (UINT64
)CpuIndex
;
1477 SmmProfileEntry
[CurrentEntryNumber
].Address
= PFAddress
;
1478 SmmProfileEntry
[CurrentEntryNumber
].Instruction
= InstructionAddress
;
1479 SmmProfileEntry
[CurrentEntryNumber
].SmiCmd
= SmiCommand
;
1481 // Update current entry index and data size in the header.
1483 mSmmProfileBase
->CurDataEntries
++;
1484 mSmmProfileBase
->CurDataSize
= MultU64x64 (mSmmProfileBase
->CurDataEntries
, sizeof (SMM_PROFILE_ENTRY
));
1493 if (mBtsSupported
) {
1499 Replace INT1 exception handler to restore page table to absent/execute-disable state
1500 in order to trigger page fault again to save SMM profile data..
1510 Status
= SmmRegisterExceptionHandler (&mSmmCpuService
, EXCEPT_IA32_DEBUG
, DebugExceptionHandler
);
1511 ASSERT_EFI_ERROR (Status
);