UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h

   1 /** @file
   2 SMM profile internal header file.
   3
   4 Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _SMM_PROFILE_INTERNAL_H_
  16 #define _SMM_PROFILE_INTERNAL_H_
  17
  18 #include <Guid/Acpi.h>
  19 #include <Protocol/SmmReadyToLock.h>
  20 #include <Library/UefiRuntimeServicesTableLib.h>
  21 #include <Library/DxeServicesTableLib.h>
  22 #include <Library/CpuLib.h>
  23 #include <IndustryStandard/Acpi.h>
  24
  25 #include "SmmProfileArch.h"
  26
  27 //
  28 // Configure the SMM_PROFILE DTS region size
  29 //
  30 #define SMM_PROFILE_DTS_SIZE       (4 * 1024 * 1024) // 4M
  31
  32 #define MAX_PF_PAGE_COUNT           0x2
  33
  34 #define PEBS_RECORD_NUMBER          0x2
  35
  36 #define MAX_PF_ENTRY_COUNT          10
  37
  38 //
  39 // This MACRO just enable unit test for the profile
  40 // Please disable it.
  41 //
  42
  43 #define IA32_PF_EC_ID               (1u << 4)
  44
  45 #define SMM_PROFILE_NAME            L"SmmProfileData"
  46
  47 //
  48 // CPU generic definition
  49 //
  50 #define   CPUID1_EDX_XD_SUPPORT      0x100000
  51 #define   MSR_EFER                   0xc0000080
  52 #define   MSR_EFER_XD                0x800
  53
  54 #define   CPUID1_EDX_BTS_AVAILABLE   0x200000
  55
  56 #define   DR6_SINGLE_STEP            0x4000
  57 #define   RFLAG_TF                   0x100
  58
  59 #define MSR_DEBUG_CTL                0x1D9
  60 #define   MSR_DEBUG_CTL_LBR          0x1
  61 #define   MSR_DEBUG_CTL_TR           0x40
  62 #define   MSR_DEBUG_CTL_BTS          0x80
  63 #define   MSR_DEBUG_CTL_BTINT        0x100
  64 #define MSR_DS_AREA                  0x600
  65
  66 #define HEAP_GUARD_NONSTOP_MODE      \
  67         ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)
  68
  69 #define NULL_DETECTION_NONSTOP_MODE  \
  70         ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6)
  71
  72 typedef struct {
  73   EFI_PHYSICAL_ADDRESS   Base;
  74   EFI_PHYSICAL_ADDRESS   Top;
  75 } MEMORY_RANGE;
  76
  77 typedef struct {
  78   MEMORY_RANGE   Range;
  79   BOOLEAN        Present;
  80   BOOLEAN        Nx;
  81 } MEMORY_PROTECTION_RANGE;
  82
  83 typedef struct {
  84   UINT64  HeaderSize;
  85   UINT64  MaxDataEntries;
  86   UINT64  MaxDataSize;
  87   UINT64  CurDataEntries;
  88   UINT64  CurDataSize;
  89   UINT64  TsegStart;
  90   UINT64  TsegSize;
  91   UINT64  NumSmis;
  92   UINT64  NumCpus;
  93 } SMM_PROFILE_HEADER;
  94
  95 typedef struct {
  96   UINT64  SmiNum;
  97   UINT64  CpuNum;
  98   UINT64  ApicId;
  99   UINT64  ErrorCode;
 100   UINT64  Instruction;
 101   UINT64  Address;
 102   UINT64  SmiCmd;
 103 } SMM_PROFILE_ENTRY;
 104
 105 extern SMM_S3_RESUME_STATE       *mSmmS3ResumeState;
 106 extern UINTN                     gSmiExceptionHandlers[];
 107 extern BOOLEAN                   mXdSupported;
 108 X86_ASSEMBLY_PATCH_LABEL         gPatchXdSupported;
 109 extern UINTN                     *mPFEntryCount;
 110 extern UINT64                    (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
 111 extern UINT64                    *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];
 112
 113 //
 114 // Internal functions
 115 //
 116
 117 /**
 118   Update IDT table to replace page fault handler and INT 1 handler.
 119
 120 **/
 121 VOID
 122 InitIdtr (
 123   VOID
 124   );
 125
 126 /**
 127   Check if the memory address will be mapped by 4KB-page.
 128
 129   @param  Address  The address of Memory.
 130
 131 **/
 132 BOOLEAN
 133 IsAddressSplit (
 134   IN EFI_PHYSICAL_ADDRESS   Address
 135   );
 136
 137 /**
 138   Check if the memory address will be mapped by 4KB-page.
 139
 140   @param  Address  The address of Memory.
 141   @param  Nx       The flag indicates if the memory is execute-disable.
 142
 143 **/
 144 BOOLEAN
 145 IsAddressValid (
 146   IN EFI_PHYSICAL_ADDRESS   Address,
 147   IN BOOLEAN                *Nx
 148   );
 149
 150 /**
 151   Page Fault handler for SMM use.
 152
 153 **/
 154 VOID
 155 SmiDefaultPFHandler (
 156   VOID
 157   );
 158
 159 /**
 160   Clear TF in FLAGS.
 161
 162   @param  SystemContext    A pointer to the processor context when
 163                            the interrupt occurred on the processor.
 164
 165 **/
 166 VOID
 167 ClearTrapFlag (
 168   IN OUT EFI_SYSTEM_CONTEXT   SystemContext
 169   );
 170
 171 #endif // _SMM_PROFILE_H_