2 SMM profile internal header file.
4 Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef _SMM_PROFILE_INTERNAL_H_
16 #define _SMM_PROFILE_INTERNAL_H_
18 #include <Guid/GlobalVariable.h>
19 #include <Guid/Acpi.h>
20 #include <Protocol/SmmReadyToLock.h>
21 #include <Library/UefiRuntimeServicesTableLib.h>
22 #include <Library/DxeServicesTableLib.h>
23 #include <Library/CpuLib.h>
24 #include <IndustryStandard/Acpi.h>
26 #include "SmmProfileArch.h"
29 // Configure the SMM_PROFILE DTS region size
31 #define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M
33 #define MAX_PF_PAGE_COUNT 0x2
35 #define PEBS_RECORD_NUMBER 0x2
37 #define MAX_PF_ENTRY_COUNT 10
40 // This MACRO just enable unit test for the profile
44 #define IA32_PF_EC_ID (1u << 4)
46 #define SMM_PROFILE_NAME L"SmmProfileData"
49 // CPU generic definition
51 #define CPUID1_EDX_XD_SUPPORT 0x100000
52 #define MSR_EFER 0xc0000080
53 #define MSR_EFER_XD 0x800
55 #define CPUID1_EDX_BTS_AVAILABLE 0x200000
57 #define DR6_SINGLE_STEP 0x4000
58 #define RFLAG_TF 0x100
60 #define MSR_DEBUG_CTL 0x1D9
61 #define MSR_DEBUG_CTL_LBR 0x1
62 #define MSR_DEBUG_CTL_TR 0x40
63 #define MSR_DEBUG_CTL_BTS 0x80
64 #define MSR_DEBUG_CTL_BTINT 0x100
65 #define MSR_DS_AREA 0x600
67 #define HEAP_GUARD_NONSTOP_MODE \
68 ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)
70 #define NULL_DETECTION_NONSTOP_MODE \
71 ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6)
74 EFI_PHYSICAL_ADDRESS Base
;
75 EFI_PHYSICAL_ADDRESS Top
;
82 } MEMORY_PROTECTION_RANGE
;
86 UINT64 MaxDataEntries
;
88 UINT64 CurDataEntries
;
106 extern SMM_S3_RESUME_STATE
*mSmmS3ResumeState
;
107 extern UINTN gSmiExceptionHandlers
[];
108 extern BOOLEAN mXdSupported
;
109 X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported
;
110 extern UINTN
*mPFEntryCount
;
111 extern UINT64 (*mLastPFEntryValue
)[MAX_PF_ENTRY_COUNT
];
112 extern UINT64
*(*mLastPFEntryPointer
)[MAX_PF_ENTRY_COUNT
];
115 // Internal functions
119 Update IDT table to replace page fault handler and INT 1 handler.
128 Check if the memory address will be mapped by 4KB-page.
130 @param Address The address of Memory.
135 IN EFI_PHYSICAL_ADDRESS Address
139 Check if the memory address will be mapped by 4KB-page.
141 @param Address The address of Memory.
142 @param Nx The flag indicates if the memory is execute-disable.
147 IN EFI_PHYSICAL_ADDRESS Address
,
152 Page Fault handler for SMM use.
156 SmiDefaultPFHandler (
163 @param SystemContext A pointer to the processor context when
164 the interrupt occurred on the processor.
169 IN OUT EFI_SYSTEM_CONTEXT SystemContext
172 #endif // _SMM_PROFILE_H_