UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h

   1 /** @file
   2 SMM profile internal header file.
   3
   4 Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _SMM_PROFILE_INTERNAL_H_
  16 #define _SMM_PROFILE_INTERNAL_H_
  17
  18 #include <Protocol/SmmReadyToLock.h>
  19 #include <Library/UefiRuntimeServicesTableLib.h>
  20 #include <Library/DxeServicesTableLib.h>
  21 #include <Library/CpuLib.h>
  22 #include <IndustryStandard/Acpi.h>
  23
  24 #include "SmmProfileArch.h"
  25
  26 //
  27 // Configure the SMM_PROFILE DTS region size
  28 //
  29 #define SMM_PROFILE_DTS_SIZE       (4 * 1024 * 1024) // 4M
  30
  31 #define MAX_PF_PAGE_COUNT           0x2
  32
  33 #define PEBS_RECORD_NUMBER          0x2
  34
  35 #define MAX_PF_ENTRY_COUNT          10
  36
  37 //
  38 // This MACRO just enable unit test for the profile
  39 // Please disable it.
  40 //
  41
  42 #define IA32_PF_EC_ID               (1u << 4)
  43
  44 #define SMM_PROFILE_NAME            L"SmmProfileData"
  45
  46 //
  47 // CPU generic definition
  48 //
  49 #define   CPUID1_EDX_XD_SUPPORT      0x100000
  50 #define   MSR_EFER                   0xc0000080
  51 #define   MSR_EFER_XD                0x800
  52
  53 #define   CPUID1_EDX_BTS_AVAILABLE   0x200000
  54
  55 #define   DR6_SINGLE_STEP            0x4000
  56 #define   RFLAG_TF                   0x100
  57
  58 #define MSR_DEBUG_CTL                0x1D9
  59 #define   MSR_DEBUG_CTL_LBR          0x1
  60 #define   MSR_DEBUG_CTL_TR           0x40
  61 #define   MSR_DEBUG_CTL_BTS          0x80
  62 #define   MSR_DEBUG_CTL_BTINT        0x100
  63 #define MSR_DS_AREA                  0x600
  64
  65 #define HEAP_GUARD_NONSTOP_MODE      \
  66         ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)
  67
  68 #define NULL_DETECTION_NONSTOP_MODE  \
  69         ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6)
  70
  71 typedef struct {
  72   EFI_PHYSICAL_ADDRESS   Base;
  73   EFI_PHYSICAL_ADDRESS   Top;
  74 } MEMORY_RANGE;
  75
  76 typedef struct {
  77   MEMORY_RANGE   Range;
  78   BOOLEAN        Present;
  79   BOOLEAN        Nx;
  80 } MEMORY_PROTECTION_RANGE;
  81
  82 typedef struct {
  83   UINT64  HeaderSize;
  84   UINT64  MaxDataEntries;
  85   UINT64  MaxDataSize;
  86   UINT64  CurDataEntries;
  87   UINT64  CurDataSize;
  88   UINT64  TsegStart;
  89   UINT64  TsegSize;
  90   UINT64  NumSmis;
  91   UINT64  NumCpus;
  92 } SMM_PROFILE_HEADER;
  93
  94 typedef struct {
  95   UINT64  SmiNum;
  96   UINT64  CpuNum;
  97   UINT64  ApicId;
  98   UINT64  ErrorCode;
  99   UINT64  Instruction;
 100   UINT64  Address;
 101   UINT64  SmiCmd;
 102 } SMM_PROFILE_ENTRY;
 103
 104 extern SMM_S3_RESUME_STATE       *mSmmS3ResumeState;
 105 extern UINTN                     gSmiExceptionHandlers[];
 106 extern BOOLEAN                   mXdSupported;
 107 X86_ASSEMBLY_PATCH_LABEL         gPatchXdSupported;
 108 extern UINTN                     *mPFEntryCount;
 109 extern UINT64                    (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
 110 extern UINT64                    *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];
 111
 112 //
 113 // Internal functions
 114 //
 115
 116 /**
 117   Update IDT table to replace page fault handler and INT 1 handler.
 118
 119 **/
 120 VOID
 121 InitIdtr (
 122   VOID
 123   );
 124
 125 /**
 126   Check if the memory address will be mapped by 4KB-page.
 127
 128   @param  Address  The address of Memory.
 129
 130 **/
 131 BOOLEAN
 132 IsAddressSplit (
 133   IN EFI_PHYSICAL_ADDRESS   Address
 134   );
 135
 136 /**
 137   Check if the memory address will be mapped by 4KB-page.
 138
 139   @param  Address  The address of Memory.
 140   @param  Nx       The flag indicates if the memory is execute-disable.
 141
 142 **/
 143 BOOLEAN
 144 IsAddressValid (
 145   IN EFI_PHYSICAL_ADDRESS   Address,
 146   IN BOOLEAN                *Nx
 147   );
 148
 149 /**
 150   Page Fault handler for SMM use.
 151
 152 **/
 153 VOID
 154 SmiDefaultPFHandler (
 155   VOID
 156   );
 157
 158 /**
 159   Clear TF in FLAGS.
 160
 161   @param  SystemContext    A pointer to the processor context when
 162                            the interrupt occurred on the processor.
 163
 164 **/
 165 VOID
 166 ClearTrapFlag (
 167   IN OUT EFI_SYSTEM_CONTEXT   SystemContext
 168   );
 169
 170 #endif // _SMM_PROFILE_H_