UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   SmmInit.nasm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   Functions for relocating SMBASE's for all processors
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21 %include "StuffRsbNasm.inc"
  22
  23 extern ASM_PFX(SmmInitHandler)
  24 extern ASM_PFX(mRebasedFlag)
  25 extern ASM_PFX(mSmmRelocationOriginalAddress)
  26
  27 global ASM_PFX(gPatchSmmCr3)
  28 global ASM_PFX(gPatchSmmCr4)
  29 global ASM_PFX(gPatchSmmCr0)
  30 global ASM_PFX(gPatchSmmInitStack)
  31 global ASM_PFX(gcSmiInitGdtr)
  32 global ASM_PFX(gcSmmInitSize)
  33 global ASM_PFX(gcSmmInitTemplate)
  34 global ASM_PFX(gPatchRebasedFlagAddr32)
  35 global ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32)
  36
  37 %define LONG_MODE_CS 0x38
  38
  39     DEFAULT REL
  40     SECTION .text
  41
  42 ASM_PFX(gcSmiInitGdtr):
  43             DW      0
  44             DQ      0
  45
  46 global ASM_PFX(SmmStartup)
  47
  48 BITS 16
  49 ASM_PFX(SmmStartup):
  50     mov     eax, 0x80000001             ; read capability
  51     cpuid
  52     mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.
  53     mov     eax, strict dword 0         ; source operand will be patched
  54 ASM_PFX(gPatchSmmCr3):
  55     mov     cr3, eax
  56 o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
  57     mov     eax, strict dword 0         ; source operand will be patched
  58 ASM_PFX(gPatchSmmCr4):
  59     or      ah,  2                      ; enable XMM registers access
  60     mov     cr4, eax
  61     mov     ecx, 0xc0000080             ; IA32_EFER MSR
  62     rdmsr
  63     or      ah, BIT0                    ; set LME bit
  64     test    ebx, BIT20                  ; check NXE capability
  65     jz      .1
  66     or      ah, BIT3                    ; set NXE bit
  67 .1:
  68     wrmsr
  69     mov     eax, strict dword 0         ; source operand will be patched
  70 ASM_PFX(gPatchSmmCr0):
  71     mov     cr0, eax                    ; enable protected mode & paging
  72     jmp     LONG_MODE_CS : dword 0      ; offset will be patched to @LongMode
  73 @PatchLongModeOffset:
  74
  75 BITS 64
  76 @LongMode:                              ; long-mode starts here
  77     mov     rsp, strict qword 0         ; source operand will be patched
  78 ASM_PFX(gPatchSmmInitStack):
  79     and     sp, 0xfff0                  ; make sure RSP is 16-byte aligned
  80     ;
  81     ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
  82     ; them before calling C-function.
  83     ;
  84     sub     rsp, 0x60
  85     movdqa  [rsp], xmm0
  86     movdqa  [rsp + 0x10], xmm1
  87     movdqa  [rsp + 0x20], xmm2
  88     movdqa  [rsp + 0x30], xmm3
  89     movdqa  [rsp + 0x40], xmm4
  90     movdqa  [rsp + 0x50], xmm5
  91
  92     add     rsp, -0x20
  93     call    ASM_PFX(SmmInitHandler)
  94     add     rsp, 0x20
  95
  96     ;
  97     ; Restore XMM0~5 after calling C-function.
  98     ;
  99     movdqa  xmm0, [rsp]
 100     movdqa  xmm1, [rsp + 0x10]
 101     movdqa  xmm2, [rsp + 0x20]
 102     movdqa  xmm3, [rsp + 0x30]
 103     movdqa  xmm4, [rsp + 0x40]
 104     movdqa  xmm5, [rsp + 0x50]
 105
 106     StuffRsb64
 107     rsm
 108
 109 BITS 16
 110 ASM_PFX(gcSmmInitTemplate):
 111     mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
 112     sub ebp, 0x30000
 113     jmp ebp
 114 @L1:
 115     DQ     0; ASM_PFX(SmmStartup)
 116
 117 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
 118
 119 BITS 64
 120 global ASM_PFX(SmmRelocationSemaphoreComplete)
 121 ASM_PFX(SmmRelocationSemaphoreComplete):
 122     push    rax
 123     mov     rax, [ASM_PFX(mRebasedFlag)]
 124     mov     byte [rax], 1
 125     pop     rax
 126     jmp     [ASM_PFX(mSmmRelocationOriginalAddress)]
 127
 128 ;
 129 ; Semaphore code running in 32-bit mode
 130 ;
 131 BITS 32
 132 global ASM_PFX(SmmRelocationSemaphoreComplete32)
 133 ASM_PFX(SmmRelocationSemaphoreComplete32):
 134     push    eax
 135     mov     eax, strict dword 0                ; source operand will be patched
 136 ASM_PFX(gPatchRebasedFlagAddr32):
 137     mov     byte [eax], 1
 138     pop     eax
 139     jmp     dword [dword 0]                    ; destination will be patched
 140 ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32):
 141
 142 BITS 64
 143 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
 144 ASM_PFX(PiSmmCpuSmmInitFixupAddress):
 145     lea    rax, [@LongMode]
 146     lea    rcx, [@PatchLongModeOffset - 6]
 147     mov    dword [rcx], eax
 148
 149     lea    rax, [ASM_PFX(SmmStartup)]
 150     lea    rcx, [@L1]
 151     mov    qword [rcx], rax
 152     ret