UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
   3 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   4 ;
   5 ; Module Name:
   6 ;
   7 ;   SmmInit.nasm
   8 ;
   9 ; Abstract:
  10 ;
  11 ;   Functions for relocating SMBASE's for all processors
  12 ;
  13 ;-------------------------------------------------------------------------------
  14
  15 %include "StuffRsbNasm.inc"
  16
  17 extern ASM_PFX(SmmInitHandler)
  18 extern ASM_PFX(mRebasedFlag)
  19 extern ASM_PFX(mSmmRelocationOriginalAddress)
  20
  21 global ASM_PFX(gPatchSmmCr3)
  22 global ASM_PFX(gPatchSmmCr4)
  23 global ASM_PFX(gPatchSmmCr0)
  24 global ASM_PFX(gPatchSmmInitStack)
  25 global ASM_PFX(gcSmiInitGdtr)
  26 global ASM_PFX(gcSmmInitSize)
  27 global ASM_PFX(gcSmmInitTemplate)
  28 global ASM_PFX(gPatchRebasedFlagAddr32)
  29 global ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32)
  30
  31 %define LONG_MODE_CS 0x38
  32
  33     DEFAULT REL
  34     SECTION .text
  35
  36 ASM_PFX(gcSmiInitGdtr):
  37             DW      0
  38             DQ      0
  39
  40 global ASM_PFX(SmmStartup)
  41
  42 BITS 16
  43 ASM_PFX(SmmStartup):
  44     mov     eax, 0x80000001             ; read capability
  45     cpuid
  46     mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.
  47     mov     eax, strict dword 0         ; source operand will be patched
  48 ASM_PFX(gPatchSmmCr3):
  49     mov     cr3, eax
  50 o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
  51     mov     eax, strict dword 0         ; source operand will be patched
  52 ASM_PFX(gPatchSmmCr4):
  53     or      ah,  2                      ; enable XMM registers access
  54     mov     cr4, eax
  55     mov     ecx, 0xc0000080             ; IA32_EFER MSR
  56     rdmsr
  57     or      ah, BIT0                    ; set LME bit
  58     test    ebx, BIT20                  ; check NXE capability
  59     jz      .1
  60     or      ah, BIT3                    ; set NXE bit
  61 .1:
  62     wrmsr
  63     mov     eax, strict dword 0         ; source operand will be patched
  64 ASM_PFX(gPatchSmmCr0):
  65     mov     cr0, eax                    ; enable protected mode & paging
  66     jmp     LONG_MODE_CS : dword 0      ; offset will be patched to @LongMode
  67 @PatchLongModeOffset:
  68
  69 BITS 64
  70 @LongMode:                              ; long-mode starts here
  71     mov     rsp, strict qword 0         ; source operand will be patched
  72 ASM_PFX(gPatchSmmInitStack):
  73     and     sp, 0xfff0                  ; make sure RSP is 16-byte aligned
  74     ;
  75     ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
  76     ; them before calling C-function.
  77     ;
  78     sub     rsp, 0x60
  79     movdqa  [rsp], xmm0
  80     movdqa  [rsp + 0x10], xmm1
  81     movdqa  [rsp + 0x20], xmm2
  82     movdqa  [rsp + 0x30], xmm3
  83     movdqa  [rsp + 0x40], xmm4
  84     movdqa  [rsp + 0x50], xmm5
  85
  86     add     rsp, -0x20
  87     call    ASM_PFX(SmmInitHandler)
  88     add     rsp, 0x20
  89
  90     ;
  91     ; Restore XMM0~5 after calling C-function.
  92     ;
  93     movdqa  xmm0, [rsp]
  94     movdqa  xmm1, [rsp + 0x10]
  95     movdqa  xmm2, [rsp + 0x20]
  96     movdqa  xmm3, [rsp + 0x30]
  97     movdqa  xmm4, [rsp + 0x40]
  98     movdqa  xmm5, [rsp + 0x50]
  99
 100     StuffRsb64
 101     rsm
 102
 103 BITS 16
 104 ASM_PFX(gcSmmInitTemplate):
 105     mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
 106     sub ebp, 0x30000
 107     jmp ebp
 108 @L1:
 109     DQ     0; ASM_PFX(SmmStartup)
 110
 111 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
 112
 113 BITS 64
 114 global ASM_PFX(SmmRelocationSemaphoreComplete)
 115 ASM_PFX(SmmRelocationSemaphoreComplete):
 116     push    rax
 117     mov     rax, [ASM_PFX(mRebasedFlag)]
 118     mov     byte [rax], 1
 119     pop     rax
 120     jmp     [ASM_PFX(mSmmRelocationOriginalAddress)]
 121
 122 ;
 123 ; Semaphore code running in 32-bit mode
 124 ;
 125 BITS 32
 126 global ASM_PFX(SmmRelocationSemaphoreComplete32)
 127 ASM_PFX(SmmRelocationSemaphoreComplete32):
 128     push    eax
 129     mov     eax, strict dword 0                ; source operand will be patched
 130 ASM_PFX(gPatchRebasedFlagAddr32):
 131     mov     byte [eax], 1
 132     pop     eax
 133     jmp     dword [dword 0]                    ; destination will be patched
 134 ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32):
 135
 136 BITS 64
 137 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
 138 ASM_PFX(PiSmmCpuSmmInitFixupAddress):
 139     lea    rax, [@LongMode]
 140     lea    rcx, [@PatchLongModeOffset - 6]
 141     mov    dword [rcx], eax
 142
 143     lea    rax, [ASM_PFX(SmmStartup)]
 144     lea    rcx, [@L1]
 145     mov    qword [rcx], rax
 146     ret