2 X64 processor specific functions to enable SMM profile.
4 Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PiSmmCpuDxeSmm.h"
16 #include "SmmProfileInternal.h"
19 // Current page index.
24 // Pool for dynamically creating page table in page fault handler.
29 // Store the uplink information for each page being used.
31 UINT64
*mPFPageUplink
[MAX_PF_PAGE_COUNT
];
34 Create SMM page table for S3 path.
42 EFI_PHYSICAL_ADDRESS Pages
;
46 // Generate PAE page table for the first 4GB memory space
48 Pages
= Gen4GPageTable (1, FALSE
);
51 // Fill Page-Table-Level4 (PML4) entry
53 PTEntry
= (UINT64
*)(UINTN
)(Pages
- EFI_PAGES_TO_SIZE (1));
54 *PTEntry
= Pages
| PAGE_ATTRIBUTE_BITS
;
55 ZeroMem (PTEntry
+ 1, EFI_PAGE_SIZE
- sizeof (*PTEntry
));
58 // Return the address of PML4 (to set CR3)
60 mSmmS3ResumeState
->SmmS3Cr3
= (UINT32
)(UINTN
)PTEntry
;
66 Allocate pages for creating 4KB-page based on 2MB-page when page fault happens.
70 InitPagesForPFHandler (
77 // Pre-Allocate memory for page fault handler
80 Address
= AllocatePages (MAX_PF_PAGE_COUNT
);
81 ASSERT (Address
!= NULL
);
83 mPFPageBuffer
= (UINT64
)(UINTN
) Address
;
85 ZeroMem ((VOID
*) (UINTN
) mPFPageBuffer
, EFI_PAGE_SIZE
* MAX_PF_PAGE_COUNT
);
86 ZeroMem (mPFPageUplink
, sizeof (mPFPageUplink
));
92 Allocate one page for creating 4KB-page based on 2MB-page.
94 @param Uplink The address of Page-Directory entry.
107 Address
= mPFPageBuffer
+ EFI_PAGES_TO_SIZE (mPFPageIndex
);
108 ZeroMem ((VOID
*) (UINTN
) Address
, EFI_PAGE_SIZE
);
111 // Cut the previous uplink if it exists and wasn't overwritten
113 if ((mPFPageUplink
[mPFPageIndex
] != NULL
) && ((*mPFPageUplink
[mPFPageIndex
] & PHYSICAL_ADDRESS_MASK
) == Address
)) {
114 *mPFPageUplink
[mPFPageIndex
] = 0;
118 // Link & Record the current uplink
120 *Uplink
= Address
| PAGE_ATTRIBUTE_BITS
;
121 mPFPageUplink
[mPFPageIndex
] = Uplink
;
123 mPFPageIndex
= (mPFPageIndex
+ 1) % MAX_PF_PAGE_COUNT
;
127 Update page table to map the memory correctly in order to make the instruction
128 which caused page fault execute successfully. And it also save the original page
129 table to be restored in single-step exception.
131 @param PageTable PageTable Address.
132 @param PFAddress The memory address which caused page fault exception.
133 @param CpuIndex The index of the processor.
134 @param ErrorCode The Error code of exception.
135 @param IsValidPFAddress The flag indicates if SMM profile data need be added.
139 RestorePageTableAbove4G (
144 BOOLEAN
*IsValidPFAddress
154 ASSERT ((PageTable
!= NULL
) && (IsValidPFAddress
!= NULL
));
157 // If page fault address is 4GB above.
161 // Check if page fault address has existed in page table.
162 // If it exists in page table but page fault is generated,
163 // there are 2 possible reasons: 1. present flag is set to 0; 2. instruction fetch in protected memory range.
166 PageTable
= (UINT64
*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK
);
167 PTIndex
= BitFieldRead64 (PFAddress
, 39, 47);
168 if ((PageTable
[PTIndex
] & IA32_PG_P
) != 0) {
170 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
171 PTIndex
= BitFieldRead64 (PFAddress
, 30, 38);
172 if ((PageTable
[PTIndex
] & IA32_PG_P
) != 0) {
174 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
175 PTIndex
= BitFieldRead64 (PFAddress
, 21, 29);
177 if ((PageTable
[PTIndex
] & IA32_PG_PS
) != 0) {
181 Address
= (UINT64
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
182 if ((Address
& PHYSICAL_ADDRESS_MASK
& ~((1ull << 21) - 1)) == ((PFAddress
& PHYSICAL_ADDRESS_MASK
& ~((1ull << 21) - 1)))) {
189 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
190 if (PageTable
!= 0) {
192 // When there is a valid entry to map to 4KB page, need not create a new entry to map 2MB.
194 PTIndex
= BitFieldRead64 (PFAddress
, 12, 20);
195 Address
= (UINT64
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
196 if ((Address
& PHYSICAL_ADDRESS_MASK
& ~((1ull << 12) - 1)) == (PFAddress
& PHYSICAL_ADDRESS_MASK
& ~((1ull << 12) - 1))) {
205 // If page entry does not existed in page table at all, create a new entry.
209 if (IsAddressValid (PFAddress
, &Nx
)) {
211 // If page fault address above 4GB is in protected range but it causes a page fault exception,
212 // Will create a page entry for this page fault address, make page table entry as present/rw and execution-disable.
213 // this access is not saved into SMM profile data.
215 *IsValidPFAddress
= TRUE
;
219 // Create one entry in page table for page fault address.
221 SmiDefaultPFHandler ();
223 // Find the page table entry created just now.
225 PageTable
= (UINT64
*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK
);
226 PFAddress
= AsmReadCr2 ();
228 PTIndex
= BitFieldRead64 (PFAddress
, 39, 47);
229 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
231 PTIndex
= BitFieldRead64 (PFAddress
, 30, 38);
232 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
234 PTIndex
= BitFieldRead64 (PFAddress
, 21, 29);
235 Address
= PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
;
237 // Check if 2MB-page entry need be changed to 4KB-page entry.
239 if (IsAddressSplit (Address
)) {
240 AcquirePage (&PageTable
[PTIndex
]);
243 PageTable
= (UINT64
*)(UINTN
)(PageTable
[PTIndex
] & PHYSICAL_ADDRESS_MASK
);
244 for (Index
= 0; Index
< 512; Index
++) {
245 PageTable
[Index
] = Address
| PAGE_ATTRIBUTE_BITS
;
246 if (!IsAddressValid (Address
, &Nx
)) {
247 PageTable
[Index
] = PageTable
[Index
] & (INTN
)(INT32
)(~PAGE_ATTRIBUTE_BITS
);
249 if (Nx
&& mXdSupported
) {
250 PageTable
[Index
] = PageTable
[Index
] | IA32_PG_NX
;
252 if (Address
== (PFAddress
& PHYSICAL_ADDRESS_MASK
& ~((1ull << 12) - 1))) {
259 // Update 2MB page entry.
261 if (!IsAddressValid (Address
, &Nx
)) {
263 // Patch to remove present flag and rw flag.
265 PageTable
[PTIndex
] = PageTable
[PTIndex
] & (INTN
)(INT32
)(~PAGE_ATTRIBUTE_BITS
);
270 if (Nx
&& mXdSupported
) {
271 PageTable
[PTIndex
] = PageTable
[PTIndex
] | IA32_PG_NX
;
277 // Record old entries with non-present status
278 // Old entries include the memory which instruction is at and the memory which instruction access.
281 ASSERT (mPFEntryCount
[CpuIndex
] < MAX_PF_ENTRY_COUNT
);
282 if (mPFEntryCount
[CpuIndex
] < MAX_PF_ENTRY_COUNT
) {
283 PFIndex
= mPFEntryCount
[CpuIndex
];
284 mLastPFEntryValue
[CpuIndex
][PFIndex
] = PageTable
[PTIndex
];
285 mLastPFEntryPointer
[CpuIndex
][PFIndex
] = &PageTable
[PTIndex
];
286 mPFEntryCount
[CpuIndex
]++;
290 // Add present flag or clear XD flag to make page fault handler succeed.
292 PageTable
[PTIndex
] |= (UINT64
)(PAGE_ATTRIBUTE_BITS
);
293 if ((ErrorCode
& IA32_PF_EC_ID
) != 0) {
295 // If page fault is caused by instruction fetch, clear XD bit in the entry.
297 PageTable
[PTIndex
] &= ~IA32_PG_NX
;
306 @param SystemContext A pointer to the processor context when
307 the interrupt occurred on the processor.
312 IN OUT EFI_SYSTEM_CONTEXT SystemContext
315 SystemContext
.SystemContextX64
->Rflags
&= (UINTN
) ~BIT8
;