UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c

   1 /** @file
   2 X64 processor specific functions to enable SMM profile.
   3
   4 Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.<BR>
   5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
   6
   7 SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #include "PiSmmCpuDxeSmm.h"
  12 #include "SmmProfileInternal.h"
  13
  14 //
  15 // Current page index.
  16 //
  17 UINTN  mPFPageIndex;
  18
  19 //
  20 // Pool for dynamically creating page table in page fault handler.
  21 //
  22 UINT64  mPFPageBuffer;
  23
  24 //
  25 // Store the uplink information for each page being used.
  26 //
  27 UINT64  *mPFPageUplink[MAX_PF_PAGE_COUNT];
  28
  29 /**
  30   Create SMM page table for S3 path.
  31
  32 **/
  33 VOID
  34 InitSmmS3Cr3 (
  35   VOID
  36   )
  37 {
  38   EFI_PHYSICAL_ADDRESS  Pages;
  39   UINT64                *PTEntry;
  40
  41   //
  42   // Generate PAE page table for the first 4GB memory space
  43   //
  44   Pages = Gen4GPageTable (FALSE);
  45
  46   //
  47   // Fill Page-Table-Level4 (PML4) entry
  48   //
  49   PTEntry = (UINT64 *)AllocatePageTableMemory (1);
  50   ASSERT (PTEntry != NULL);
  51   *PTEntry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
  52   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));
  53
  54   //
  55   // Return the address of PML4 (to set CR3)
  56   //
  57   mSmmS3ResumeState->SmmS3Cr3 = (UINT32)(UINTN)PTEntry;
  58
  59   return;
  60 }
  61
  62 /**
  63   Allocate pages for creating 4KB-page based on 2MB-page when page fault happens.
  64
  65 **/
  66 VOID
  67 InitPagesForPFHandler (
  68   VOID
  69   )
  70 {
  71   VOID  *Address;
  72
  73   //
  74   // Pre-Allocate memory for page fault handler
  75   //
  76   Address = NULL;
  77   Address = AllocatePages (MAX_PF_PAGE_COUNT);
  78   ASSERT (Address != NULL);
  79
  80   mPFPageBuffer =  (UINT64)(UINTN)Address;
  81   mPFPageIndex  = 0;
  82   ZeroMem ((VOID *)(UINTN)mPFPageBuffer, EFI_PAGE_SIZE * MAX_PF_PAGE_COUNT);
  83   ZeroMem (mPFPageUplink, sizeof (mPFPageUplink));
  84
  85   return;
  86 }
  87
  88 /**
  89   Allocate one page for creating 4KB-page based on 2MB-page.
  90
  91   @param  Uplink   The address of Page-Directory entry.
  92
  93 **/
  94 VOID
  95 AcquirePage (
  96   UINT64  *Uplink
  97   )
  98 {
  99   UINT64  Address;
 100
 101   //
 102   // Get the buffer
 103   //
 104   Address = mPFPageBuffer + EFI_PAGES_TO_SIZE (mPFPageIndex);
 105   ZeroMem ((VOID *)(UINTN)Address, EFI_PAGE_SIZE);
 106
 107   //
 108   // Cut the previous uplink if it exists and wasn't overwritten
 109   //
 110   if ((mPFPageUplink[mPFPageIndex] != NULL) && ((*mPFPageUplink[mPFPageIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK) == Address)) {
 111     *mPFPageUplink[mPFPageIndex] = 0;
 112   }
 113
 114   //
 115   // Link & Record the current uplink
 116   //
 117   *Uplink                     = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
 118   mPFPageUplink[mPFPageIndex] = Uplink;
 119
 120   mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;
 121 }
 122
 123 /**
 124   Update page table to map the memory correctly in order to make the instruction
 125   which caused page fault execute successfully. And it also save the original page
 126   table to be restored in single-step exception.
 127
 128   @param  PageTable           PageTable Address.
 129   @param  PFAddress           The memory address which caused page fault exception.
 130   @param  CpuIndex            The index of the processor.
 131   @param  ErrorCode           The Error code of exception.
 132   @param  IsValidPFAddress    The flag indicates if SMM profile data need be added.
 133
 134 **/
 135 VOID
 136 RestorePageTableAbove4G (
 137   UINT64   *PageTable,
 138   UINT64   PFAddress,
 139   UINTN    CpuIndex,
 140   UINTN    ErrorCode,
 141   BOOLEAN  *IsValidPFAddress
 142   )
 143 {
 144   UINTN     PTIndex;
 145   UINT64    Address;
 146   BOOLEAN   Nx;
 147   BOOLEAN   Existed;
 148   UINTN     Index;
 149   UINTN     PFIndex;
 150   IA32_CR4  Cr4;
 151   BOOLEAN   Enable5LevelPaging;
 152
 153   ASSERT ((PageTable != NULL) && (IsValidPFAddress != NULL));
 154
 155   Cr4.UintN          = AsmReadCr4 ();
 156   Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
 157
 158   //
 159   // If page fault address is 4GB above.
 160   //
 161
 162   //
 163   // Check if page fault address has existed in page table.
 164   // If it exists in page table but page fault is generated,
 165   // there are 2 possible reasons: 1. present flag is set to 0; 2. instruction fetch in protected memory range.
 166   //
 167   Existed   = FALSE;
 168   PageTable = (UINT64 *)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
 169   PTIndex   = 0;
 170   if (Enable5LevelPaging) {
 171     PTIndex = BitFieldRead64 (PFAddress, 48, 56);
 172   }
 173
 174   if ((!Enable5LevelPaging) || ((PageTable[PTIndex] & IA32_PG_P) != 0)) {
 175     // PML5E
 176     if (Enable5LevelPaging) {
 177       PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 178     }
 179
 180     PTIndex = BitFieldRead64 (PFAddress, 39, 47);
 181     if ((PageTable[PTIndex] & IA32_PG_P) != 0) {
 182       // PML4E
 183       PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 184       PTIndex   = BitFieldRead64 (PFAddress, 30, 38);
 185       if ((PageTable[PTIndex] & IA32_PG_P) != 0) {
 186         // PDPTE
 187         PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 188         PTIndex   = BitFieldRead64 (PFAddress, 21, 29);
 189         // PD
 190         if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {
 191           //
 192           // 2MB page
 193           //
 194           Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 195           if ((Address & ~((1ull << 21) - 1)) == ((PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)))) {
 196             Existed = TRUE;
 197           }
 198         } else {
 199           //
 200           // 4KB page
 201           //
 202           PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK);
 203           if (PageTable != 0) {
 204             //
 205             // When there is a valid entry to map to 4KB page, need not create a new entry to map 2MB.
 206             //
 207             PTIndex = BitFieldRead64 (PFAddress, 12, 20);
 208             Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 209             if ((Address & ~((1ull << 12) - 1)) == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {
 210               Existed = TRUE;
 211             }
 212           }
 213         }
 214       }
 215     }
 216   }
 217
 218   //
 219   // If page entry does not existed in page table at all, create a new entry.
 220   //
 221   if (!Existed) {
 222     if (IsAddressValid (PFAddress, &Nx)) {
 223       //
 224       // If page fault address above 4GB is in protected range but it causes a page fault exception,
 225       // Will create a page entry for this page fault address, make page table entry as present/rw and execution-disable.
 226       // this access is not saved into SMM profile data.
 227       //
 228       *IsValidPFAddress = TRUE;
 229     }
 230
 231     //
 232     // Create one entry in page table for page fault address.
 233     //
 234     SmiDefaultPFHandler ();
 235     //
 236     // Find the page table entry created just now.
 237     //
 238     PageTable = (UINT64 *)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
 239     PFAddress = AsmReadCr2 ();
 240     // PML5E
 241     if (Enable5LevelPaging) {
 242       PTIndex   = BitFieldRead64 (PFAddress, 48, 56);
 243       PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 244     }
 245
 246     // PML4E
 247     PTIndex   = BitFieldRead64 (PFAddress, 39, 47);
 248     PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 249     // PDPTE
 250     PTIndex   = BitFieldRead64 (PFAddress, 30, 38);
 251     PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 252     // PD
 253     PTIndex = BitFieldRead64 (PFAddress, 21, 29);
 254     Address = PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK;
 255     //
 256     // Check if 2MB-page entry need be changed to 4KB-page entry.
 257     //
 258     if (IsAddressSplit (Address)) {
 259       AcquirePage (&PageTable[PTIndex]);
 260
 261       // PTE
 262       PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 263       for (Index = 0; Index < 512; Index++) {
 264         PageTable[Index] = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
 265         if (!IsAddressValid (Address, &Nx)) {
 266           PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
 267         }
 268
 269         if (Nx && mXdSupported) {
 270           PageTable[Index] = PageTable[Index] | IA32_PG_NX;
 271         }
 272
 273         if (Address == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {
 274           PTIndex = Index;
 275         }
 276
 277         Address += SIZE_4KB;
 278       } // end for PT
 279     } else {
 280       //
 281       // Update 2MB page entry.
 282       //
 283       if (!IsAddressValid (Address, &Nx)) {
 284         //
 285         // Patch to remove present flag and rw flag.
 286         //
 287         PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
 288       }
 289
 290       //
 291       // Set XD bit to 1
 292       //
 293       if (Nx && mXdSupported) {
 294         PageTable[PTIndex] = PageTable[PTIndex] | IA32_PG_NX;
 295       }
 296     }
 297   }
 298
 299   //
 300   // Record old entries with non-present status
 301   // Old entries include the memory which instruction is at and the memory which instruction access.
 302   //
 303   //
 304   ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);
 305   if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {
 306     PFIndex                                = mPFEntryCount[CpuIndex];
 307     mLastPFEntryValue[CpuIndex][PFIndex]   = PageTable[PTIndex];
 308     mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];
 309     mPFEntryCount[CpuIndex]++;
 310   }
 311
 312   //
 313   // Add present flag or clear XD flag to make page fault handler succeed.
 314   //
 315   PageTable[PTIndex] |= (UINT64)(PAGE_ATTRIBUTE_BITS);
 316   if ((ErrorCode & IA32_PF_EC_ID) != 0) {
 317     //
 318     // If page fault is caused by instruction fetch, clear XD bit in the entry.
 319     //
 320     PageTable[PTIndex] &= ~IA32_PG_NX;
 321   }
 322
 323   return;
 324 }
 325
 326 /**
 327   Clear TF in FLAGS.
 328
 329   @param  SystemContext    A pointer to the processor context when
 330                            the interrupt occurred on the processor.
 331
 332 **/
 333 VOID
 334 ClearTrapFlag (
 335   IN OUT EFI_SYSTEM_CONTEXT  SystemContext
 336   )
 337 {
 338   SystemContext.SystemContextX64->Rflags &= (UINTN) ~BIT8;
 339 }