3 Copyright (c) 2017-2021, Intel Corporation. All rights reserved.<BR>
4 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @param[in] PchSpiBase PCH SPI PCI Base Address
14 @retval Return SPI BAR Address
22 return MmioRead32 (PchSpiBase
+ R_SPI_BASE
) & ~(B_SPI_BAR0_MASK
);
26 Release SPI MMIO BAR. Do nothing.
28 @param[in] PchSpiBase PCH SPI PCI Base Address
41 This function is to enable/disable BIOS Write Protect in SMM phase.
43 @param[in] EnableSmmSts Flag to Enable/disable Bios write protect
47 CpuSmmDisableBiosWriteProtect (
48 IN BOOLEAN EnableSmmSts
55 // Disable BIOS Write Protect in SMM phase.
57 Data32
= MmioRead32 ((UINTN
) (0xFED30880)) | (UINT32
) (BIT0
);
58 AsmWriteMsr32 (0x000001FE, Data32
);
61 // Enable BIOS Write Protect in SMM phase
63 Data32
= MmioRead32 ((UINTN
) (0xFED30880)) & (UINT32
) (~BIT0
);
64 AsmWriteMsr32 (0x000001FE, Data32
);
68 // Read FED30880h back to ensure the setting went through.
70 Data32
= MmioRead32 (0xFED30880);
75 This function is a hook for Spi to disable BIOS Write Protect.
77 @param[in] PchSpiBase PCH SPI PCI Base Address
78 @param[in] CpuSmmBwp Need to disable CPU SMM Bios write protection or not
80 @retval EFI_SUCCESS The protocol instance was properly initialized
81 @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
86 DisableBiosWriteProtect (
93 // Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
95 MmioOr8 (PchSpiBase
+ R_SPI_BCR
+ 1, (B_SPI_BCR_SYNC_SS
>> 8));
98 // Enable the access to the BIOS space for both read and write cycles
100 MmioOr8 (PchSpiBase
+ R_SPI_BCR
, B_SPI_BCR_BIOSWE
);
102 if (CpuSmmBwp
!= 0) {
103 CpuSmmDisableBiosWriteProtect (TRUE
);
110 This function is a hook for Spi to enable BIOS Write Protect.
112 @param[in] PchSpiBase PCH SPI PCI Base Address
113 @param[in] CpuSmmBwp Need to disable CPU SMM Bios write protection or not
118 EnableBiosWriteProtect (
125 // Disable the access to the BIOS space for write cycles
127 MmioAnd8 (PchSpiBase
+ R_SPI_BCR
, (UINT8
) (~B_SPI_BCR_BIOSWE
));
129 if (CpuSmmBwp
!= 0) {
130 CpuSmmDisableBiosWriteProtect (FALSE
);
135 This function disables SPI Prefetching and caching,
136 and returns previous BIOS Control Register value before disabling.
138 @param[in] PchSpiBase PCH SPI PCI Base Address
140 @retval Previous BIOS Control Register value
144 SaveAndDisableSpiPrefetchCache (
150 BiosCtlSave
= MmioRead8 (PchSpiBase
+ R_SPI_BCR
) & B_SPI_BCR_SRC
;
152 MmioAndThenOr32 (PchSpiBase
+ R_SPI_BCR
, \
153 (UINT32
) (~B_SPI_BCR_SRC
), \
154 (UINT32
) (V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS
<< B_SPI_BCR_SRC
));
160 This function updates BIOS Control Register with the given value.
162 @param[in] PchSpiBase PCH SPI PCI Base Address
163 @param[in] BiosCtlValue BIOS Control Register Value to be updated
167 SetSpiBiosControlRegister (
169 IN UINT8 BiosCtlValue
172 MmioAndThenOr8 (PchSpiBase
+ R_SPI_BCR
, (UINT8
) ~B_SPI_BCR_SRC
, BiosCtlValue
);