UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c

   1 /** @file
   2
   3   Copyright (c) 2017-2021, Intel Corporation. All rights reserved.<BR>
   4   SPDX-License-Identifier: BSD-2-Clause-Patent
   5
   6 **/
   7 #include "SpiCommon.h"
   8
   9 /**
  10   Acquire SPI MMIO BAR.
  11
  12   @param[in] PchSpiBase           PCH SPI PCI Base Address
  13
  14   @retval                         Return SPI BAR Address
  15
  16 **/
  17 UINT32
  18 AcquireSpiBar0 (
  19   IN  UINTN  PchSpiBase
  20   )
  21 {
  22   return MmioRead32 (PchSpiBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK);
  23 }
  24
  25 /**
  26   Release SPI MMIO BAR. Do nothing.
  27
  28   @param[in] PchSpiBase           PCH SPI PCI Base Address
  29
  30 **/
  31 VOID
  32 ReleaseSpiBar0 (
  33   IN  UINTN  PchSpiBase
  34   )
  35 {
  36 }
  37
  38 /**
  39   This function is to enable/disable BIOS Write Protect in SMM phase.
  40
  41   @param[in] EnableSmmSts        Flag to Enable/disable Bios write protect
  42
  43 **/
  44 VOID
  45 CpuSmmDisableBiosWriteProtect (
  46   IN  BOOLEAN  EnableSmmSts
  47   )
  48 {
  49   UINT32  Data32;
  50
  51   if (EnableSmmSts) {
  52     //
  53     // Disable BIOS Write Protect in SMM phase.
  54     //
  55     Data32 = MmioRead32 ((UINTN)(0xFED30880)) | (UINT32)(BIT0);
  56     AsmWriteMsr32 (0x000001FE, Data32);
  57   } else {
  58     //
  59     // Enable BIOS Write Protect in SMM phase
  60     //
  61     Data32 = MmioRead32 ((UINTN)(0xFED30880)) & (UINT32)(~BIT0);
  62     AsmWriteMsr32 (0x000001FE, Data32);
  63   }
  64
  65   //
  66   // Read FED30880h back to ensure the setting went through.
  67   //
  68   Data32 = MmioRead32 (0xFED30880);
  69 }
  70
  71 /**
  72   This function is a hook for Spi to disable BIOS Write Protect.
  73
  74   @param[in] PchSpiBase           PCH SPI PCI Base Address
  75   @param[in] CpuSmmBwp            Need to disable CPU SMM Bios write protection or not
  76
  77   @retval EFI_SUCCESS             The protocol instance was properly initialized
  78   @retval EFI_ACCESS_DENIED       The BIOS Region can only be updated in SMM phase
  79
  80 **/
  81 EFI_STATUS
  82 EFIAPI
  83 DisableBiosWriteProtect (
  84   IN  UINTN  PchSpiBase,
  85   IN  UINT8  CpuSmmBwp
  86   )
  87 {
  88   //
  89   // Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
  90   //
  91   MmioOr8 (PchSpiBase + R_SPI_BCR + 1, (B_SPI_BCR_SYNC_SS >> 8));
  92
  93   //
  94   // Enable the access to the BIOS space for both read and write cycles
  95   //
  96   MmioOr8 (PchSpiBase + R_SPI_BCR, B_SPI_BCR_BIOSWE);
  97
  98   if (CpuSmmBwp != 0) {
  99     CpuSmmDisableBiosWriteProtect (TRUE);
 100   }
 101
 102   return EFI_SUCCESS;
 103 }
 104
 105 /**
 106   This function is a hook for Spi to enable BIOS Write Protect.
 107
 108   @param[in] PchSpiBase           PCH SPI PCI Base Address
 109   @param[in] CpuSmmBwp            Need to disable CPU SMM Bios write protection or not
 110
 111 **/
 112 VOID
 113 EFIAPI
 114 EnableBiosWriteProtect (
 115   IN  UINTN  PchSpiBase,
 116   IN  UINT8  CpuSmmBwp
 117   )
 118 {
 119   //
 120   // Disable the access to the BIOS space for write cycles
 121   //
 122   MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8)(~B_SPI_BCR_BIOSWE));
 123
 124   if (CpuSmmBwp != 0) {
 125     CpuSmmDisableBiosWriteProtect (FALSE);
 126   }
 127 }
 128
 129 /**
 130   This function disables SPI Prefetching and caching,
 131   and returns previous BIOS Control Register value before disabling.
 132
 133   @param[in] PchSpiBase           PCH SPI PCI Base Address
 134
 135   @retval                         Previous BIOS Control Register value
 136
 137 **/
 138 UINT8
 139 SaveAndDisableSpiPrefetchCache (
 140   IN  UINTN  PchSpiBase
 141   )
 142 {
 143   UINT8  BiosCtlSave;
 144
 145   BiosCtlSave = MmioRead8 (PchSpiBase + R_SPI_BCR) & B_SPI_BCR_SRC;
 146
 147   MmioAndThenOr32 (
 148     PchSpiBase + R_SPI_BCR, \
 149     (UINT32)(~B_SPI_BCR_SRC), \
 150     (UINT32)(V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS <<  B_SPI_BCR_SRC)
 151     );
 152
 153   return BiosCtlSave;
 154 }
 155
 156 /**
 157   This function updates BIOS Control Register with the given value.
 158
 159   @param[in] PchSpiBase           PCH SPI PCI Base Address
 160   @param[in] BiosCtlValue         BIOS Control Register Value to be updated
 161
 162 **/
 163 VOID
 164 SetSpiBiosControlRegister (
 165   IN  UINTN  PchSpiBase,
 166   IN  UINT8  BiosCtlValue
 167   )
 168 {
 169   MmioAndThenOr8 (PchSpiBase + R_SPI_BCR, (UINT8) ~B_SPI_BCR_SRC, BiosCtlValue);
 170 }