3 Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
5 SPDX-License-Identifier: BSD-2-Clause-Patent
14 Abstract: The fixed ACPI description Table (FADT) Structure
19 #include "EDKIIGlueDxe.h"
23 #include <IndustryStandard/Acpi50.h>
24 #include "AcpiTablePlatform.h"
26 EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
28 EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
29 sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),
30 EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
31 0, // to make sum of entire table == 0
32 EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field
33 EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
34 EFI_ACPI_OEM_REVISION, // OEM revision number
35 EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
36 EFI_ACPI_CREATOR_REVISION // ASL compiler revision number
38 0, // Physical addesss of FACS
39 0, // Physical address of DSDT
40 INT_MODEL, // System Interrupt Model (ignored in 2k and later, must be 0 for 98)
41 PM_PROFILE, // Preferred PM Profile
42 SCI_INT_VECTOR, // System vector of SCI interrupt
43 SMI_CMD_IO_PORT, // Port address of SMI command port
44 ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
45 ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
46 S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
47 PSTATE_CNT, // PState control
48 PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk
49 PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk
50 PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk
51 PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk
52 PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk
53 PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk
54 GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk
55 GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk
56 PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
57 PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
58 PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk
59 PM_TM_LEN, // Byte Length of ports at pm_tm_blk
60 GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
61 GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
62 GPE1_BASE, // offset in gpe model where gpe1 events start
63 CST_CNT, // _CST support
64 P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
65 P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
66 FLUSH_SIZE, // Size of area read to flush caches
67 FLUSH_STRIDE, // Stride used in flushing caches
68 DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg
69 DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg
70 DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
71 MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
72 CENTURY, // index to century in RTC CMOS RAM
73 IAPC_BOOT_ARCH, // IA-PCI Boot Architecture Flag
77 EFI_ACPI_5_0_SYSTEM_IO,
83 0x0E, // Hardware reset value
88 // X_PM1a Event Register Block
90 EFI_ACPI_5_0_SYSTEM_IO,
97 // X_PM1b Event Register Block
99 EFI_ACPI_5_0_SYSTEM_IO,
102 EFI_ACPI_RESERVED_BYTE,
106 // X_PM1a Control Register Block
108 EFI_ACPI_5_0_SYSTEM_IO,
115 // X_PM1b Control Register Block
117 EFI_ACPI_5_0_SYSTEM_IO,
120 EFI_ACPI_RESERVED_BYTE,
124 // X_PM2 Control Register Block
126 EFI_ACPI_5_0_SYSTEM_IO,
133 // X_PM Timer Control Register Block
135 EFI_ACPI_5_0_SYSTEM_IO,
142 // X_General Purpose Event 0 Register Block
144 EFI_ACPI_5_0_SYSTEM_IO,
147 EFI_ACPI_RESERVED_BYTE,
151 // X_General Purpose Event 1 Register Block
153 EFI_ACPI_5_0_SYSTEM_IO,
156 EFI_ACPI_RESERVED_BYTE,
160 // Sleep Control Register Block
162 EFI_ACPI_5_0_SYSTEM_IO,
165 EFI_ACPI_RESERVED_BYTE,
169 // Sleep Status Register Block
171 EFI_ACPI_5_0_SYSTEM_IO,
174 EFI_ACPI_RESERVED_BYTE,
184 // Reference the table being generated to prevent the optimizer from
185 // removing the data structure from the executable