Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl

   1 /**************************************************************************;
   2 ;*                                                                        *;
   3 ;*                                                                        *;
   4 ;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
   5 ;*    Family of Customer Reference Boards.                                *;
   6 ;*                                                                        *;
   7 ;*                                                                        *;
   8 ;*    Copyright (c)  1999  - 2016, Intel Corporation. All rights reserved   *;
   9 ;
  10 ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11 ;
  12 ;*                                                                        *;
  13 ;*                                                                        *;
  14 ;**************************************************************************/
  15
  16
  17
  18 // Define a Global region of ACPI NVS Region that may be used for any
  19 // type of implementation.  The starting offset and size will be fixed
  20 // up by the System BIOS during POST.  Note that the Size must be a word
  21 // in size to be fixed up correctly.
  22
  23 OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
  24 Field(GNVS,AnyAcc,Lock,Preserve)
  25 {
  26   Offset(0),       // Miscellaneous Dynamic Registers:
  27   OSYS,   16,      //   (00) Operating System
  28       ,   8,       //   (02)
  29       ,   8,       //   (03)
  30       ,   8,       //   (04)
  31       ,   8,       //   (05)
  32       ,   8,       //   (06)
  33       ,   8,       //   (07)
  34       ,   8,       //   (08)
  35       ,   8,       //   (09)
  36       ,   8,       //   (10)
  37   P80D,   32,      //   (11) Port 80 Debug Port Value
  38   LIDS,   8,       //   (15) Lid State (Lid Open = 1)
  39       ,   8,       //   (16)
  40       ,   8,       //   (17)
  41   Offset(18),      // Thermal Policy Registers:
  42       ,   8,       //   (18)
  43       ,   8,       //   (19)
  44   ACTT,   8,       //   (20) Active Trip Point
  45   PSVT,   8,       //   (21) Passive Trip Point
  46   TC1V,   8,       //   (22) Passive Trip Point TC1 Value
  47   TC2V,   8,       //   (23) Passive Trip Point TC2 Value
  48   TSPV,   8,       //   (24) Passive Trip Point TSP Value
  49   CRTT,   8,       //   (25) Critical Trip Point
  50   DTSE,   8,       //   (26) Digital Thermal Sensor Enable
  51   DTS1,   8,       //   (27) Digital Thermal Sensor 1 Reading
  52   DTS2,   8,       //   (28) Digital Thermal Sensor 2 Reading
  53   DTSF,   8,       //   (29) DTS SMI Function Call
  54   Offset(30),      // Battery Support Registers:
  55       ,   8,       //   (30)
  56       ,   8,       //   (31)
  57       ,   8,       //   (32)
  58       ,   8,       //   (33)
  59       ,   8,       //   (34)
  60       ,   8,       //   (35)
  61       ,   8,       //   (36)
  62   Offset(40),      // CPU Identification Registers:
  63   APIC,   8,       //   (40) APIC Enabled by SBIOS (APIC Enabled = 1)
  64   MPEN,   8,       //   (41) Number of Logical Processors if MP Enabled != 0
  65       ,   8,       //   (42)
  66       ,   8,       //   (43)
  67       ,   8,       //   (44)
  68       ,   32,      //   (45)
  69   Offset(50),      // SIO CMOS Configuration Registers:
  70       ,   8,       //   (50)
  71       ,   8,       //   (51)
  72       ,   8,       //   (52)
  73       ,   8,       //   (53)
  74       ,   8,       //   (54)
  75       ,   8,       //   (55)
  76       ,   8,       //   (56)
  77       ,   8,       //   (57)
  78       ,   8,       //   (58)
  79   Offset(60),      // Internal Graphics Registers:
  80       ,   8,       //   (60)
  81       ,   8,       //   (61)
  82   CADL,   8,       //   (62) Current Attached Device List
  83       ,   8,       //   (63)
  84   CSTE,   16,      //   (64) Current Display State
  85   NSTE,   16,      //   (66) Next Display State
  86       ,   16,      //   (68)
  87   NDID,   8,       //   (70) Number of Valid Device IDs
  88   DID1,   32,      //   (71) Device ID 1
  89   DID2,   32,      //   (75) Device ID 2
  90   DID3,   32,      //   (79) Device ID 3
  91   DID4,   32,      //   (83) Device ID 4
  92   DID5,   32,      //   (87) Device ID 5
  93       ,   32,      //   (91)
  94       ,   8,       //   (95) Fifth byte of AKSV (mannufacturing mode)
  95   Offset(103),     // Backlight Control Registers:
  96       ,   8,       //   (103)
  97   BRTL,   8,       //   (104) Brightness Level Percentage
  98   Offset(105),     // Ambiant Light Sensor Registers:
  99       ,   8,       //   (105)
 100       ,   8,       //   (106)
 101   LLOW,   8,       //   (107) LUX Low Value
 102       ,   8,       //   (108)
 103   Offset(110),     // EMA Registers:
 104       ,   8,       //   (110)
 105       ,   16,      //   (111)
 106       ,   16,      //   (113)
 107   Offset(116),     // MEF Registers:
 108       ,   8,       //   (116) MEF Enable
 109   Offset(117),     // PCIe Dock:
 110       ,   8,       //   (117)
 111   Offset(120),     // TPM Registers:
 112       ,   8,       //   (120)
 113       ,   8,       //   (121)
 114       ,   8,       //   (122)
 115       ,   8,       //   (123)
 116       ,   32,      //   (124)
 117       ,   8,       //   (125)
 118       ,   8,       //   (129)
 119   Offset(130),     //
 120       ,   56,      //   (130)
 121       ,   56,      //   (137)
 122       ,   8,       //   (144)
 123       ,   56,      //   (145)
 124   Offset(170),     // IGD OpRegion/Software SCI base address
 125   ASLB,   32,      //   (170) IGD OpRegion base address
 126   Offset(174),     // IGD OpRegion/Software SCI shared data
 127   IBTT,   8,       //   (174) IGD Boot Display Device
 128   IPAT,   8,       //   (175) IGD Panel Type CMOs option
 129   ITVF,   8,       //   (176) IGD TV Format CMOS option
 130   ITVM,   8,       //   (177) IGD TV Minor Format CMOS option
 131   IPSC,   8,       //   (178) IGD Panel Scaling
 132   IBLC,   8,       //   (179) IGD BLC Configuration
 133   IBIA,   8,       //   (180) IGD BIA Configuration
 134   ISSC,   8,       //   (181) IGD SSC Configuration
 135   I409,   8,       //   (182) IGD 0409 Modified Settings Flag
 136   I509,   8,       //   (183) IGD 0509 Modified Settings Flag
 137   I609,   8,       //   (184) IGD 0609 Modified Settings Flag
 138   I709,   8,       //   (185) IGD 0709 Modified Settings Flag
 139   IDMM,   8,       //   (186) IGD DVMT Mode
 140   IDMS,   8,       //   (187) IGD DVMT Memory Size
 141   IF1E,   8,       //   (188) IGD Function 1 Enable
 142   HVCO,   8,       //   (189) HPLL VCO
 143   NXD1,   32,      //   (190) Next state DID1 for _DGS
 144   NXD2,   32,      //   (194) Next state DID2 for _DGS
 145   NXD3,   32,      //   (198) Next state DID3 for _DGS
 146   NXD4,   32,      //   (202) Next state DID4 for _DGS
 147   NXD5,   32,      //   (206) Next state DID5 for _DGS
 148   NXD6,   32,      //   (210) Next state DID6 for _DGS
 149   NXD7,   32,      //   (214) Next state DID7 for _DGS
 150   NXD8,   32,      //   (218) Next state DID8 for _DGS
 151   GSMI,   8,       //   (222) GMCH SMI/SCI mode (0=SCI)
 152   PAVP,   8,       //   (223) IGD PAVP data
 153   Offset(225),
 154   OSCC,   8,       //   (225) PCIE OSC Control
 155   NEXP,   8,       //   (226) Native PCIE Setup Value
 156   Offset(235), // Global Variables
 157   DSEN,   8,       //   (235) _DOS Display Support Flag.
 158   ECON,   8,       //   (236) Embedded Controller Availability Flag.
 159   GPIC,   8,       //   (237) Global IOAPIC/8259 Interrupt Mode Flag.
 160   CTYP,   8,       //   (238) Global Cooling Type Flag.
 161   L01C,   8,       //   (239) Global L01 Counter.
 162   VFN0,   8,       //   (240) Virtual Fan0 Status.
 163   VFN1,   8,       //   (241) Virtual Fan1 Status.
 164   Offset(256),
 165   NVGA,   32,  //   (256) NVIG opregion address
 166   NVHA,   32,  //   (260) NVHM opregion address
 167   AMDA,   32,  //   (264) AMDA opregion address
 168   DID6,   32,  //   (268) Device ID 6
 169   DID7,   32,  //   (272) Device ID 7
 170   DID8,   32,  //   (276) Device ID 8
 171   Offset(332),
 172   USEL,   8,    // (332) UART Selection
 173   PU1E,   8,    // (333) PCU UART 1 Enabled
 174   PU2E,   8,    // (334) PCU UART 2 Enabled
 175
 176   LPE0, 32,     // (335) LPE Bar0
 177   LPE1, 32,     // (339) LPE Bar1
 178   LPE2, 32,     // (343) LPE Bar2
 179
 180   Offset(347),
 181       ,   8,    // (347)
 182       ,   8,    // (348)
 183   PFLV,   8,    // (349) Platform Flavor
 184
 185   Offset(351),
 186   ICNF,   8,   //   (351) ISCT / AOAC Configuration
 187   XHCI,   8,   //   (352) xHCI controller mode
 188   PMEN,   8,   //   (353) PMIC enable/disable
 189
 190   LPEE,   8,   //   (354) LPE enable/disable
 191   ISPA,   32,  //   (355) ISP Base Addr
 192   ISPD,   8,    //  (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3
 193
 194   offset(360),  // ((4+8+6)*4+2)*4=296
 195   //
 196   // Lpss controllers
 197   //
 198   PCIB,     32,
 199   PCIT,     32,
 200   D10A,     32,  //DMA1
 201   D10L,     32,
 202   D11A,     32,
 203   D11L,     32,
 204   P10A,     32,  //  PWM1
 205   P10L,     32,
 206   P11A,     32,
 207   P11L,     32,
 208   P20A,     32,  //  PWM2
 209   P20L,     32,
 210   P21A,     32,
 211   P21L,     32,
 212   U10A,     32,  // UART1
 213   U10L,     32,
 214   U11A,     32,
 215   U11L,     32,
 216   U20A,     32,  // UART2
 217   U20L,     32,
 218   U21A,     32,
 219   U21L,     32,
 220   SP0A,     32,  // SPI
 221   SP0L,     32,
 222   SP1A,     32,
 223   SP1L,     32,
 224
 225   D20A,     32,  //DMA2
 226   D20L,     32,
 227   D21A,     32,
 228   D21L,     32,
 229   I10A,     32,  //  I2C1
 230   I10L,     32,
 231   I11A,     32,
 232   I11L,     32,
 233   I20A,     32,  //  I2C2
 234   I20L,     32,
 235   I21A,     32,
 236   I21L,     32,
 237   I30A,     32,  //  I2C3
 238   I30L,     32,
 239   I31A,     32,
 240   I31L,     32,
 241   I40A,     32,  //  I2C4
 242   I40L,     32,
 243   I41A,     32,
 244   I41L,     32,
 245   I50A,     32,  //  I2C5
 246   I50L,     32,
 247   I51A,     32,
 248   I51L,     32,
 249   I60A,     32,  //  I2C6
 250   I60L,     32,
 251   I61A,     32,
 252   I61L,     32,
 253   I70A,     32,  //  I2C7
 254   I70L,     32,
 255   I71A,     32,
 256   I71L,     32,
 257   //
 258   // Scc controllers
 259   //
 260   eM0A,     32,  //  EMMC
 261   eM0L,     32,
 262   eM1A,     32,
 263   eM1L,     32,
 264   SI0A,     32,  //  SDIO
 265   SI0L,     32,
 266   SI1A,     32,
 267   SI1L,     32,
 268   SD0A,     32,  //  SDCard
 269   SD0L,     32,
 270   SD1A,     32,
 271   SD1L,     32,
 272   MH0A,     32,  //
 273   MH0L,     32,
 274   MH1A,     32,
 275   MH1L,     32,
 276
 277   offset(656),
 278   SDRM,     8,
 279   offset(657),
 280   HLPS,     8,   //(657) Hide Devices
 281   offset(658),
 282   OSEL,     8,      //(658) OS Seletion - Windows/Android
 283
 284   offset(659),  // VLV1 DPTF
 285   SDP1,     8,      //(659) An enumerated value corresponding to SKU
 286   DPTE,     8,      //(660) DPTF Enable
 287   THM0,     8,      //(661) System Thermal 0
 288   THM1,     8,      //(662) System Thermal 1
 289   THM2,     8,      //(663) System Thermal 2
 290   THM3,     8,      //(664) System Thermal 3
 291   THM4,     8,      //(665) System Thermal 3
 292   CHGR,     8,      //(666) DPTF Changer Device
 293   DDSP,     8,      //(667) DPTF Display Device
 294   DSOC,     8,      //(668) DPTF SoC device
 295   DPSR,     8,      //(669) DPTF Processor device
 296   DPCT,     32,     //(670) DPTF Processor participant critical temperature
 297   DPPT,     32,     //(674) DPTF Processor participant passive temperature
 298   DGC0,     32,     //(678) DPTF Generic sensor0 participant critical temperature
 299   DGP0,     32,     //(682) DPTF Generic sensor0 participant passive temperature
 300   DGC1,     32,     //(686) DPTF Generic sensor1 participant critical temperature
 301   DGP1,     32,     //(690) DPTF Generic sensor1 participant passive temperature
 302   DGC2,     32,     //(694) DPTF Generic sensor2 participant critical temperature
 303   DGP2,     32,     //(698) DPTF Generic sensor2 participant passive temperature
 304   DGC3,     32,     //(702) DPTF Generic sensor3 participant critical temperature
 305   DGP3,     32,     //(706) DPTF Generic sensor3 participant passive temperature
 306   DGC4,     32,     //(710)DPTF Generic sensor3 participant critical temperature
 307   DGP4,     32,     //(714)DPTF Generic sensor3 participant passive temperature
 308   DLPM,     8,      //(718) DPTF Current low power mode setting
 309   DSC0,     32,     //(719) DPTF Critical threshold0 for SCU
 310   DSC1,     32,     //(723) DPTF Critical threshold1 for SCU
 311   DSC2,     32,     //(727) DPTF Critical threshold2 for SCU
 312   DSC3,     32,     //(731) DPTF Critical threshold3 for SCU
 313   DSC4,     32,     //(735) DPTF Critical threshold3 for SCU
 314   DDBG,     8,      //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled
 315   LPOE,     32,     //(740) DPTF LPO Enable
 316   LPPS,     32,     //(744) P-State start index
 317   LPST,     32,     //(748) Step size
 318   LPPC,     32,     //(752) Power control setting
 319   LPPF,     32,     //(756) Performance control setting
 320   DPME,     8,      //(760) DPTF DPPM enable/disable
 321   BCSL,     8,      //(761) Battery charging solution 0-CLV 1-ULPMC
 322   NFCS,     8,      //(762) NFCx Select 1: NFC1    2:NFC2
 323   PCIM,     8,      //(763) EMMC device 0-ACPI mode, 1-PCI mode
 324   TPMA,     32,     //(764)
 325   TPML,     32,     //(768)
 326   ITSA,      8,     //(772) I2C Touch Screen Address
 327   S0IX,     8,      //(773) S0ix status
 328   SDMD,     8,      //(774) SDIO Mode
 329   EMVR,     8,      //(775) eMMC controller version
 330   BMBD,     32,     //(776) BM Bound
 331   FSAS,     8,      //(780) FSA Status
 332   BDID,     8,      //(781) Board ID
 333   FBID,     8,      //(782) FAB ID
 334   OTGM,     8,      //(783) OTG mode
 335   STEP,     8,      //(784) Stepping ID
 336   WITT,     8,      //(785) Enable Test Device connected to I2C for WHCK test.
 337   SOCS,     8,      //(786) provide the SoC stepping infomation
 338   AMTE,     8,      //(787) Ambient Trip point change
 339   UTS,      8,      //(788) Enable Test Device connected to URT for WHCK test.
 340   SCPE,     8,      //(789) Allow higher performance on AC/USB - Enable/Disable
 341   Offset(792),
 342   EDPV,     8,      //(792) Check for eDP display device
 343   DIDX,     32,     //(793) Device ID for eDP device
 344   IOT,      8,      //(794) MinnowBoard Max JP1 is configured for MSFT IOT project.
 345   BATT,     8,      //(795) The Flag of RTC Battery Prensent.
 346   LPAD,     8,      //(796)
 347 }
 348