Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL

   1 /**************************************************************************;
   2 ;*                                                                        *;
   3 ;*                                                                        *;
   4 ;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
   5 ;*    Family of Customer Reference Boards.                                *;
   6 ;*                                                                        *;
   7 ;*                                                                        *;
   8 ;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
   9 ;
  10 ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11 ;
  12 ;*                                                                        *;
  13 ;*                                                                        *;
  14 ;**************************************************************************/
  15
  16
  17
  18 Scope (\_SB.PCI0)
  19 {
  20
  21   Device(PDRC)   // PCI Device Resource Consumption
  22   {
  23     Name(_HID,EISAID("PNP0C02"))
  24
  25     Name(_UID,1)
  26
  27     Name(BUF0,ResourceTemplate()
  28     {
  29       //
  30       // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h
  31       // Forced hard code at the moment.
  32       //
  33       //Memory32Fixed(ReadWrite,0,0,PCIX)       // PCIEX BAR
  34       Memory32Fixed(ReadWrite,0x0E0000000,0x010000000,PCIX)
  35
  36       //
  37       // SPI BAR. Check if the hard code meets the real configuration.
  38       // If not, dynamically update it like the _CRS method below.
  39       //
  40       Memory32Fixed(ReadWrite,0x0FED01000,0x01000,SPIB) // SPI BAR
  41
  42       //
  43       // PMC BAR. Check if the hard code meets the real configuration.
  44       // If not, dynamically update it like the _CRS method below.
  45       //
  46       Memory32Fixed(ReadWrite,0x0FED03000,0x01000,PMCB) // PMC BAR
  47
  48       //
  49       // SMB BAR. Check if the hard code meets the real configuration.
  50       // If not, dynamically update it like the _CRS method below.
  51       //
  52       Memory32Fixed(ReadWrite,0x0FED04000,0x01000,SMBB) // SMB BAR
  53
  54       //
  55       // IO BAR. Check if the hard code meets the real configuration.
  56       // If not, dynamically update it like the _CRS method below.
  57       //
  58       Memory32Fixed(ReadWrite,0x0FED0C000,0x04000,IOBR) // IO BAR
  59
  60       //
  61       // ILB BAR. Check if the hard code meets the real configuration.
  62       // If not, dynamically update it like the _CRS method below.
  63       //
  64       Memory32Fixed(ReadWrite,0x0FED08000,0x01000,ILBB) // ILB BAR
  65
  66       //
  67       // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h
  68       //
  69       Memory32Fixed(ReadWrite,0x0FED1C000,0x01000,RCRB) // RCRB BAR
  70
  71       //
  72       // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
  73       //
  74       Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH)
  75
  76       //
  77       // MPHY BAR. Check if the hard code meets the real configuration.
  78       // If not, dynamically update it like the _CRS method below.
  79       //
  80       Memory32Fixed(ReadWrite,0x0FEF00000,0x0100000,MPHB)       // MPHY BAR
  81     })
  82
  83     Method(_CRS,0,Serialized)
  84     {
  85
  86       Return(BUF0)
  87     }
  88
  89   }
  90 }