Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl

   1 /**************************************************************************;
   2 ;*                                                                        *;
   3 ;*                                                                        *;
   4 ;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
   5 ;*    Family of Customer Reference Boards.                                *;
   6 ;*                                                                        *;
   7 ;*                                                                        *;
   8 ;*    Copyright (c) 2012  - 2016, Intel Corporation. All rights reserved    *;
   9 ;
  10 ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11 ;
  12 ;*                                                                        *;
  13 ;*                                                                        *;
  14 ;**************************************************************************/
  15
  16
  17 Scope(\)
  18 {
  19   //
  20   // Define VLV ABASE I/O as an ACPI operating region. The base address
  21   // can be found in Device 31, Registers 40-43h.
  22   //
  23   OperationRegion(PMIO, SystemIo, \PMBS, 0x46)
  24   Field(PMIO, ByteAcc, NoLock, Preserve)
  25   {
  26     ,      8,
  27     PWBS,  1,       // Power Button Status
  28     Offset(0x20),
  29     ,      13,
  30     PMEB,  1,     // PME_B0_STS
  31     Offset(0x42),     // General Purpose Control
  32     ,      1,
  33     GPEC,  1
  34   }
  35   Field(PMIO, ByteAcc, NoLock, WriteAsZeros)
  36   {
  37     Offset(0x20),     // GPE0 Status
  38     ,      4,
  39     PSCI,  1,       // PUNIT SCI Status
  40     SCIS,  1        // GUNIT SCI Status
  41   }
  42
  43
  44
  45   //
  46   // Define a Memory Region that will allow access to the PMC
  47   // Register Block.  Note that in the Intel Reference Solution, the PMC
  48   // will get fixed up dynamically during POST.
  49   //
  50   OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register
  51   Field(PMCR,DWordAcc,Lock,Preserve)
  52   {
  53     Offset(0x00),   //  Function Disable Register
  54     L10D,  1,         //  (0) LPIO1 DMA Disable
  55     L11D,  1,         //  (1) LPIO1 PWM #1 Disable
  56     L12D,  1,         //  (2) LPIO1 PWM #2 Disable
  57     L13D,  1,         //  (3) LPIO1 HS-UART #1 Disable
  58     L14D,  1,         //  (4) LPIO1 HS-UART #2 Disable
  59     L15D,  1,         //  (5) LPIO1 SPI Disable
  60     ,          2,     //  (6:7) Reserved
  61     SD1D,  1,         //  (8) SCC SDIO #1 Disable
  62     SD2D,  1,         //  (9) SCC SDIO #2 Disable
  63     SD3D,  1,         //  (10) SCC SDIO #3 Disable
  64     HSID,  1,         //  (11)
  65     HDAD,  1,         //  (12) Azalia Disable
  66     LPED,  1,         //  (13) LPE Disable
  67     OTGD,  1,         //  (14) USB OTG Disable
  68     ,          1,     //  (15) USH Disable
  69     ,          1,     //  (16)
  70     ,          1,     //  (17)
  71     ,          1,     //  (18) USB Disable
  72     ,          1,     //  (19) SEC Disable
  73     RP1D,  1,         //  (20) Root Port 0 Disable
  74     RP2D,  1,         //  (21) Root Port 1 Disable
  75     RP3D,  1,         //  (22) Root Port 2 Disable
  76     RP4D,  1,         //  (23) Root Port 3 Disable
  77     L20D,  1,         //  (24) LPIO2 DMA Disable
  78     L21D,  1,         //  (25) LPIO2 I2C #1 Disable
  79     L22D,  1,         //  (26) LPIO2 I2C #2 Disable
  80     L23D,  1,         //  (27) LPIO2 I2C #3 Disable
  81     L24D,  1,         //  (28) LPIO2 I2C #4 Disable
  82     L25D,  1,         //  (29) LPIO2 I2C #5 Disable
  83     L26D,  1,         //  (30) LPIO2 I2C #6 Disable
  84     L27D,  1          //  (31) LPIO2 I2C #7 Disable
  85   }
  86
  87
  88   OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers
  89   Field(CLKC,DWordAcc,Lock,Preserve)
  90   {
  91     Offset(0x00),   //  PLT_CLK_CTL_0
  92     CKC0, 2,
  93     CKF0, 1,
  94     ,     29,
  95     Offset(0x04),   //  PLT_CLK_CTL_1
  96     CKC1, 2,
  97     CKF1, 1,
  98     ,     29,
  99     Offset(0x08),   //  PLT_CLK_CTL_2
 100     CKC2,  2,
 101     CKF2, 1,
 102     ,     29,
 103     Offset(0x0C),   //  PLT_CLK_CTL_3
 104     CKC3,  2,
 105     CKF3, 1,
 106     ,     29,
 107     Offset(0x10),   //  PLT_CLK_CTL_4
 108     CKC4,  2,
 109     CKF4, 1,
 110     ,     29,
 111     Offset(0x14),   //  PLT_CLK_CTL_5
 112     CKC5,  2,
 113     CKF5, 1,
 114     ,     29,
 115   }
 116 } //end Scope(\)
 117
 118 scope (\_SB)
 119 {
 120   Device(LPEA)
 121   {
 122     Name (_ADR, 0)
 123     Name (_HID, "80860F28")
 124     Name (_CID, "80860F28")
 125     //Name (_CLS, Package (3) {0x04, 0x01, 0x00})
 126     Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28")
 127     Name (_SUB, "80867270")
 128     Name (_UID, 1)
 129     Name (_DEP, Package() {\_SB.I2C2.RTEK})
 130     Name(_PR0,Package() {PLPE})
 131
 132     Method (_STA, 0x0, NotSerialized)
 133     {
 134       If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0)))
 135       {
 136         If(LEqual(LPAD, 1))
 137         {
 138           Return (0xF)
 139         }
 140       }
 141       Return (0x0)
 142     }
 143
 144     Method (_DIS, 0x0, NotSerialized)
 145     {
 146       //Add a dummy disable function
 147     }
 148
 149     Name (RBUF, ResourceTemplate ()
 150       {
 151         Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0)  // MMIO 1 - LPE MMIO
 152         Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1)  // MMIO 2 - Shadowed PCI Config Space
 153         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2)  // LPE Memory Bar Allocate during post
 154         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
 155         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25}
 156         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26}
 157         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27}
 158         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28}
 159         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
 160         GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} //  Audio jack interrupt
 161       }
 162     )
 163
 164     Method (_CRS, 0x0, NotSerialized)
 165     {
 166       CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)
 167       Store(LPE0, B0BA)
 168       CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
 169       Store(LPE1, B1BA)
 170       CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
 171       Store(LPE2, B2BA)
 172       Return (RBUF)
 173     }
 174
 175     OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
 176     Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
 177     {
 178       Offset (0x84),
 179       PSAT,   32
 180     }
 181
 182     PowerResource(PLPE, 0, 0)   // Power Resource for LPEA
 183     {
 184       Method (_STA)
 185       {
 186         Return (1)      // Power Resource is always available.
 187       }
 188
 189       Method (_ON)
 190       {
 191         And(PSAT, 0xfffffffC, PSAT)
 192         OR(PSAT, 0X00000000, PSAT)
 193       }
 194
 195       Method (_OFF)
 196       {
 197         OR(PSAT, 0x00000003, PSAT)
 198         OR(PSAT, 0X00000000, PSAT)
 199       }
 200     } // End PLPE
 201   } // End "Low Power Engine Audio"
 202
 203   Device(LPA2)
 204   {
 205     Name (_ADR, 0)
 206     Name (_HID, "LPE0F28")  // _HID: Hardware ID
 207     Name (_CID, "LPE0F28")  // _CID: Compatible ID
 208     Name (_DDN, "Intel(R) SST Audio - LPE0F28")  // _DDN: DOS Device Name
 209     Name (_SUB, "80867270")
 210     Name (_UID, 1)
 211     Name (_DEP, Package() {\_SB.I2C2.RTEK})
 212     Name(_PR0,Package() {PLPE})
 213
 214     Method (_STA, 0x0, NotSerialized)
 215     {
 216       If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1)))
 217       {
 218         If(LEqual(LPAD, 1))
 219         {
 220           Return (0xF)
 221         }
 222       }
 223       Return (0x0)
 224     }
 225
 226     Method (_DIS, 0x0, NotSerialized)
 227     {
 228       //Add a dummy disable function
 229     }
 230
 231     Name (RBUF, ResourceTemplate ()
 232       {
 233         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2)  // LPE Memory Bar Allocate during post
 234         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM)
 235         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX)
 236         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM)
 237         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM)
 238         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
 239         Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1)  // MMIO 2 - Shadowed PCI Config Space
 240       }
 241     )
 242
 243     Method (_CRS, 0x0, NotSerialized)
 244     {
 245       CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
 246       Add(LPE0, 0x140000, SHBA)
 247       CreateDwordField(^RBUF, ^MBOX._BAS, MBBA)
 248       Add(LPE0, 0x144000, MBBA)
 249       CreateDwordField(^RBUF, ^IRAM._BAS, IRBA)
 250       Add(LPE0, 0xC0000, IRBA)
 251       CreateDwordField(^RBUF, ^DRAM._BAS, DRBA)
 252       Add(LPE0, 0x100000, DRBA)
 253       CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
 254       Store(LPE1, B1BA)
 255       CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
 256       Store(LPE2, B2BA)
 257       Return (RBUF)
 258     }
 259
 260     OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
 261     Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
 262     {
 263       Offset (0x84),
 264       PSAT,   32
 265     }
 266
 267     PowerResource(PLPE, 0, 0)   // Power Resource for LPEA
 268     {
 269       Method (_STA)
 270       {
 271         Return (1)      // Power Resource is always available.
 272       }
 273
 274       Method (_ON)
 275       {
 276         And(PSAT, 0xfffffffC, PSAT)
 277         OR(PSAT, 0X00000000, PSAT)
 278       }
 279
 280       Method (_OFF)
 281       {
 282         OR(PSAT, 0x00000003, PSAT)
 283         OR(PSAT, 0X00000000, PSAT)
 284       }
 285     } // End PLPE
 286
 287     Device (ADMA)
 288     {
 289       Name (_ADR, Zero)  // _ADR: Address
 290       Name (_HID, "DMA0F28")  // _HID: Hardware ID
 291       Name (_CID, "DMA0F28")  // _CID: Compatible ID
 292       Name (_DDN, "Intel(R) Audio  DMA0 - DMA0F28")  // _DDN: DOS Device Name
 293       Name (_UID, One)  // _UID: Unique ID
 294       Name (RBUF, ResourceTemplate ()
 295       {
 296         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0)  // LPE BASE + LPE DMA0 offset
 297         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM)  // LPE BASE + LPE SHIM offset
 298         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
 299       })
 300
 301       Method (_CRS, 0, NotSerialized)   // _CRS: Current Resource Settings
 302       {
 303         CreateDwordField(^RBUF, ^DMA0._BAS, D0BA)
 304         Add(LPE0, 0x98000, D0BA)
 305         CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
 306         Add(LPE0, 0x140000, SHBA)
 307         Return (RBUF)
 308       }
 309     }
 310   } // End "Low Power Engine Audio" for Android
 311 }
 312
 313 scope (\_SB.PCI0)
 314 {
 315
 316   //
 317   // Serial ATA Host Controller - Device 19, Function 0
 318   //
 319
 320   Device(SATA)
 321   {
 322     Name(_ADR,0x00130000)
 323     //
 324     // SATA Methods pulled in via SSDT.
 325     //
 326
 327     OperationRegion(SATR, PCI_Config, 0x74,0x4)
 328     Field(SATR,WordAcc,NoLock,Preserve)
 329     {
 330       Offset(0x00), // 0x74, PMCR
 331       ,   8,
 332       PMEE,   1,    //PME_EN
 333       ,   6,
 334       PMES,   1     //PME_STS
 335     }
 336
 337     Method (_STA, 0x0, NotSerialized)
 338     {
 339       Return(0xf)
 340     }
 341
 342     Method(_DSW, 3)
 343     {
 344     } // End _DSW
 345   }
 346
 347   //
 348   // For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment
 349   //
 350   Device(EM41)
 351   {
 352     Name(_ADR,0x00100000)
 353     OperationRegion(SDIO, PCI_Config, 0x84,0x4)
 354     Field(SDIO,WordAcc,NoLock,Preserve)
 355     {
 356       Offset(0x00), // 0x84, PMCR
 357       ,   8,
 358       PMEE,   1,    //PME_EN
 359       ,   6,
 360       PMES,   1     //PME_STS
 361     }
 362
 363     Method (_STA, 0x0, NotSerialized)
 364     {
 365       If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0)))
 366       {
 367         Return(0xF)
 368       }
 369       Else
 370       {
 371         Return(0x0)
 372       }
 373     }
 374
 375     Method(_DSW, 3)
 376     {
 377     } // End _DSW
 378
 379     Device (CARD)
 380     {
 381       Name (_ADR, 0x00000008)
 382       Method(_RMV, 0x0, NotSerialized)
 383       {
 384         Return (0)
 385       } // End _DSW
 386     }
 387   }
 388
 389   //
 390   // For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment
 391   //
 392   Device(EM45)
 393   {
 394     Name(_ADR,0x00170000)
 395     OperationRegion(SDIO, PCI_Config, 0x84,0x4)
 396     Field(SDIO,WordAcc,NoLock,Preserve)
 397     {
 398       Offset(0x00), // 0x84, PMCR
 399       ,   8,
 400       PMEE,   1,    //PME_EN
 401       ,   6,
 402       PMES,   1     //PME_STS
 403     }
 404
 405     Method (_STA, 0x0, NotSerialized)
 406     {
 407       If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0)))
 408       {
 409         Return(0xF)
 410       }
 411       Else
 412       {
 413         Return(0x0)
 414       }
 415     }
 416
 417     Method(_DSW, 3)
 418     {
 419     } // End _DSW
 420
 421     Device (CARD)
 422     {
 423       Name (_ADR, 0x00000008)
 424       Method(_RMV, 0x0, NotSerialized)
 425       {
 426         Return (0)
 427       } // End _DSW
 428     }
 429   }
 430   //
 431   // For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment
 432   //
 433   Device(SD12)
 434   {
 435     Name(_ADR,0x00120000)
 436
 437     Method (_STA, 0x0, NotSerialized)
 438     {
 439       //
 440       // PCIM>> 0:ACPI mode           1:PCI mode
 441       //
 442       If (LEqual(PCIM, 0)) {
 443         Return (0x0)
 444       }
 445
 446       //
 447       // If device is disabled.
 448       //
 449       If (LEqual(SD3D, 1))
 450       {
 451         Return (0x0)
 452       }
 453
 454       Return (0xF)
 455     }
 456
 457     Device (CARD)
 458     {
 459       Name (_ADR, 0x00000008)
 460       Method(_RMV, 0x0, NotSerialized)
 461       {
 462         // SDRM = 0 non-removable;
 463         If (LEqual(SDRM, 0))
 464         {
 465           Return (0)
 466         }
 467
 468         Return (1)
 469       }
 470     }
 471   }
 472
 473   // xHCI Controller - Device 20, Function 0
 474   include("PchXhci.asl")
 475
 476   //
 477   // High Definition Audio Controller - Device 27, Function 0
 478   //
 479   Device(HDEF)
 480   {
 481     Name(_ADR, 0x001B0000)
 482     include("PchAudio.asl")
 483
 484     Method (_STA, 0x0, NotSerialized)
 485     {
 486       If (LEqual(HDAD, 0))
 487       {
 488         Return(0xf)
 489       }
 490       Return(0x0)
 491     }
 492
 493     Method(_DSW, 3)
 494     {
 495     } // End _DSW
 496   } // end "High Definition Audio Controller"
 497
 498
 499
 500   //
 501   // PCIE Root Port #1
 502   //
 503   Device(RP01)
 504   {
 505     Name(_ADR, 0x001C0000)
 506     include("PchPcie.asl")
 507     Name(_PRW, Package() {9, 4})
 508
 509     Method(_PRT,0)
 510     {
 511       If(PICM) { Return(AR04) }// APIC mode
 512       Return (PR04) // PIC Mode
 513     } // end _PRT
 514   } // end "PCIE Root Port #1"
 515
 516   //
 517   // PCIE Root Port #2
 518   //
 519   Device(RP02)
 520   {
 521     Name(_ADR, 0x001C0001)
 522     include("PchPcie.asl")
 523     Name(_PRW, Package() {9, 4})
 524
 525     Method(_PRT,0)
 526     {
 527       If(PICM) { Return(AR05) }// APIC mode
 528       Return (PR05) // PIC Mode
 529     } // end _PRT
 530
 531   } // end "PCIE Root Port #2"
 532
 533   //
 534   // PCIE Root Port #3
 535   //
 536   Device(RP03)
 537   {
 538     Name(_ADR, 0x001C0002)
 539     include("PchPcie.asl")
 540     Name(_PRW, Package() {9, 4})
 541     Method(_PRT,0)
 542     {
 543       If(PICM) { Return(AR06) }// APIC mode
 544       Return (PR06) // PIC Mode
 545     } // end _PRT
 546
 547   } // end "PCIE Root Port #3"
 548
 549   //
 550   // PCIE Root Port #4
 551   //
 552   Device(RP04)
 553   {
 554     Name(_ADR, 0x001C0003)
 555     include("PchPcie.asl")
 556     Name(_PRW, Package() {9, 4})
 557     Method(_PRT,0)
 558     {
 559       If(PICM) { Return(AR07) }// APIC mode
 560       Return (PR07) // PIC Mode
 561     } // end _PRT
 562
 563   } // end "PCIE Root Port #4"
 564
 565
 566   Scope(\_SB)
 567   {
 568     //
 569     // Dummy power resource for USB D3 cold support
 570     //
 571     PowerResource(USBC, 0, 0)
 572     {
 573       Method(_STA) { Return (0xF) }
 574       Method(_ON) {}
 575       Method(_OFF) {}
 576     }
 577   }
 578   //
 579   // EHCI Controller - Device 29, Function 0
 580   //
 581   Device(EHC1)
 582   {
 583     Name(_ADR, 0x001D0000)
 584     Name(_DEP, Package(0x1)
 585     {
 586       PEPD
 587     })
 588     include("PchEhci.asl")
 589     Name(_PRW, Package() {0x0D, 4})
 590
 591     OperationRegion(USBR, PCI_Config, 0x54,0x4)
 592     Field(USBR,WordAcc,NoLock,Preserve)
 593     {
 594       Offset(0x00), // 0x54, PMCR
 595       ,   8,
 596       PMEE,   1,    //PME_EN
 597       ,   6,
 598       PMES,   1     //PME_STS
 599     }
 600
 601     Method (_STA, 0x0, NotSerialized)
 602     {
 603       If(LEqual(XHCI, 0))      //XHCI is not present. It means EHCI is there
 604       {
 605         Return (0xF)
 606       } Else
 607       {
 608         Return (0x0)
 609       }
 610     }
 611
 612     Method (_RMV, 0, NotSerialized)
 613     {
 614       Return (0x0)
 615     }
 616     //
 617     // Create a dummy PR3 method to indicate to the PCI driver
 618     // that the device is capable of D3 cold
 619     //
 620     Method(_PR3, 0x0, NotSerialized)
 621     {
 622       return (Package() {\_SB.USBC})
 623     }
 624
 625   } // end "EHCI Controller"
 626
 627   //
 628   // SMBus Controller - Device 31, Function 3
 629   //
 630   Device(SBUS)
 631   {
 632     Name(_ADR,0x001F0003)
 633     Include("PchSmb.asl")
 634   }
 635
 636   Device(SEC0)
 637   {
 638     Name (_ADR, 0x001a0000)                     // Device 0x1a, Function 0
 639     Name(_DEP, Package(0x1)
 640     {
 641       PEPD
 642     })
 643
 644
 645     OperationRegion (PMEB, PCI_Config, 0x84, 0x04)  //PMECTRLSTATUS
 646     Field (PMEB, WordAcc, NoLock, Preserve)
 647     {
 648       ,   8,
 649       PMEE,   1,    //bit8 PMEENABLE
 650       ,   6,
 651       PMES,   1     //bit15 PMESTATUS
 652     }
 653
 654     // Arg0 -- integer that contains the device wake capability control (0-disable 1- enable)
 655     // Arg1 -- integer that contains target system state (0-4)
 656     // Arg2 -- integer that contains the target device state
 657     Method (_DSW, 3, NotSerialized)   // _DSW: Device Sleep Wake
 658     {
 659     }
 660
 661     Method (_CRS, 0, NotSerialized)
 662     {
 663       Name (RBUF, ResourceTemplate ()
 664       {
 665         Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000)
 666       })
 667
 668       If (LEqual(PAVP, 2))
 669       {
 670         Return (RBUF)
 671       }
 672       Return (ResourceTemplate() {})
 673     }
 674
 675     Method (_STA)
 676     {
 677       If (LNotEqual(PAVP, 0))
 678       {
 679         Return (0xF)
 680       }
 681       Return (0x0)
 682     }
 683   }   // Device(SEC0)
 684
 685 } // End scope (\_SB.PCI0)
 686