Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl

   1 /**************************************************************************;
   2 ;*                                                                        *;
   3 ;*                                                                        *;
   4 ;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
   5 ;*    Family of Customer Reference Boards.                                *;
   6 ;*                                                                        *;
   7 ;*                                                                        *;
   8 ;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;
   9 ;
  10 ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11 ;
  12 ;*                                                                        *;
  13 ;*                                                                        *;
  14 ;**************************************************************************/
  15
  16
  17 // Define various SMBus PCI Configuration Space Registers.
  18
  19 OperationRegion(SMBP,PCI_Config,0x40,0xC0)
  20 Field(SMBP,DWordAcc,NoLock,Preserve)
  21 {
  22   ,     2,
  23   I2CE, 1
  24 }
  25
  26 // SMBus Send Byte - This function will write a single byte of
  27 // data to a specific Slave Device per SMBus Send Byte Protocol.
  28 //      Arg0 = Address
  29 //      Arg1 = Data
  30 //      Return: Success = 1
  31 //              Failure = 0
  32
  33       Method(SSXB,2,Serialized)
  34 {
  35   OperationRegion(SMPB,PCI_Config,0x20,4)
  36   Field(SMPB,DWordAcc,NoLock,Preserve)
  37   {
  38     ,     5,
  39     SBAR, 11
  40   }
  41
  42   // Define various SMBus IO Mapped Registers.
  43
  44   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
  45   Field(SMBI,ByteAcc,NoLock,Preserve)
  46   {
  47     HSTS, 8,        // 0 - Host Status Register
  48     Offset(0x02),
  49     HCON, 8,        // 2 - Host Control
  50     HCOM, 8,        // 3 - Host Command
  51     TXSA, 8,        // 4 - Transmit Slave Address
  52     DAT0, 8,        // 5 - Host Data 0
  53     DAT1, 8,        // 6 - Host Data 1
  54     HBDR, 8,        // 7 - Host Block Data
  55     PECR, 8,        // 8 - Packer Error Check
  56     RXSA, 8,        // 9 - Receive Slave Address
  57     SDAT, 16,       // A - Slave Data
  58   }
  59
  60   // Step 1:  Confirm the ICHx SMBus is ready to perform
  61   // communication.
  62
  63   If(STRT())
  64   {
  65     Return(0)
  66   }
  67
  68   // Step 2:  Initiate a Send Byte.
  69
  70   Store(0,I2CE)                           // Ensure SMbus Mode.
  71   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
  72   Store(Arg0,TXSA)                        // Write Address in TXSA.
  73   Store(Arg1,HCOM)                        // Data in HCOM.
  74
  75   // Set the SMBus Host control register to 0x48.
  76   //   Bit 7:    =  0  = reserved
  77   //   Bit 6:    =  1  = start
  78   //   Bit 5:    =  0  = disregard, I2C related bit
  79   //   Bits 4:2: = 001 = Byte Protocol
  80   //   Bit 1:    =  0  = Normal Function
  81   //   Bit 0:    =  0  = Disable interrupt generation
  82
  83   Store(0x48,HCON)
  84
  85   // Step 3:  Exit the Method correctly.
  86
  87   If(COMP)
  88   {
  89     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
  90     Return(1)                       // Return Success.
  91   }
  92
  93   Return(0)
  94 }
  95
  96 // SMBus Receive Byte - This function will write a single byte
  97 // of data to a specific Slave Device per SMBus Receive Byte
  98 // Protocol.
  99 //      Arg0 = Address
 100 //      Return: Success = Byte-Size Value
 101 //              Failure = Word-Size Value = FFFFh.
 102
 103 Method(SRXB,1,Serialized)
 104 {
 105   OperationRegion(SMPB,PCI_Config,0x20,4)
 106   Field(SMPB,DWordAcc,NoLock,Preserve)
 107   {
 108     ,     5,
 109     SBAR, 11
 110   }
 111
 112   // Define various SMBus IO Mapped Registers.
 113
 114   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 115   Field(SMBI,ByteAcc,NoLock,Preserve)
 116   {
 117     HSTS, 8,        // 0 - Host Status Register
 118     Offset(0x02),
 119     HCON, 8,        // 2 - Host Control
 120     HCOM, 8,        // 3 - Host Command
 121     TXSA, 8,        // 4 - Transmit Slave Address
 122     DAT0, 8,        // 5 - Host Data 0
 123     DAT1, 8,        // 6 - Host Data 1
 124     HBDR, 8,        // 7 - Host Block Data
 125     PECR, 8,        // 8 - Packer Error Check
 126     RXSA, 8,        // 9 - Receive Slave Address
 127     SDAT, 16,       // A - Slave Data
 128   }
 129   // Step 1:  Confirm the ICHx SMBus is ready to perform
 130   // communication.
 131
 132   If(STRT())
 133   {
 134     Return(0xFFFF)
 135   }
 136
 137   // Step 2:  Initiate a Receive Byte.
 138
 139   Store(0,I2CE)                           // Ensure SMbus Mode.
 140   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 141   Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
 142
 143   // Set the SMBus Host control register to 0x48.
 144   //   Bit 7:    =  0  = reserved
 145   //   Bit 6:    =  1  = start
 146   //   Bit 5:    =  0  = disregard, I2C related bit
 147   //   Bits 4:2: = 001 = Byte Protocol
 148   //   Bit 1:    =  0  = Normal Function
 149   //   Bit 0:    =  0  = Disable interrupt generation
 150
 151   Store(0x44,HCON)
 152
 153   // Step 3:  Exit the Method correctly.
 154
 155   If(COMP)
 156   {
 157     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
 158     Return(DAT0)                    // Return Success.
 159   }
 160
 161   Return(0xFFFF)                          // Return Failure.
 162 }
 163
 164 // SMBus Write Byte - This function will write a single byte
 165 // of data to a specific Slave Device per SMBus Write Byte
 166 // Protocol.
 167 //      Arg0 = Address
 168 //      Arg1 = Command
 169 //      Arg2 = Data
 170 //      Return: Success = 1
 171 //              Failure = 0
 172
 173 Method(SWRB,3,Serialized)
 174 {
 175   OperationRegion(SMPB,PCI_Config,0x20,4)
 176   Field(SMPB,DWordAcc,NoLock,Preserve)
 177   {
 178     ,     5,
 179     SBAR, 11
 180   }
 181
 182   // Define various SMBus IO Mapped Registers.
 183
 184   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 185   Field(SMBI,ByteAcc,NoLock,Preserve)
 186   {
 187     HSTS, 8,        // 0 - Host Status Register
 188     Offset(0x02),
 189     HCON, 8,        // 2 - Host Control
 190     HCOM, 8,        // 3 - Host Command
 191     TXSA, 8,        // 4 - Transmit Slave Address
 192     DAT0, 8,        // 5 - Host Data 0
 193     DAT1, 8,        // 6 - Host Data 1
 194     HBDR, 8,        // 7 - Host Block Data
 195     PECR, 8,        // 8 - Packer Error Check
 196     RXSA, 8,        // 9 - Receive Slave Address
 197     SDAT, 16,       // A - Slave Data
 198   }
 199   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 200
 201   If(STRT())
 202   {
 203     Return(0)
 204   }
 205
 206   // Step 2:  Initiate a Write Byte.
 207
 208   Store(0,I2CE)                           // Ensure SMbus Mode.
 209   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 210   Store(Arg0,TXSA)                        // Write Address in TXSA.
 211   Store(Arg1,HCOM)                        // Command in HCOM.
 212   Store(Arg2,DAT0)                        // Data in DAT0.
 213
 214   // Set the SMBus Host control register to 0x48.
 215   //   Bit 7:    =  0  = reserved
 216   //   Bit 6:    =  1  = start
 217   //   Bit 5:    =  0  = disregard, I2C related bit
 218   //   Bits 4:2: = 010 = Byte Data Protocol
 219   //   Bit 1:    =  0  = Normal Function
 220   //   Bit 0:    =  0  = Disable interrupt generation
 221
 222   Store(0x48,HCON)
 223
 224   // Step 3:  Exit the Method correctly.
 225
 226   If(COMP)
 227   {
 228     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
 229     Return(1)                       // Return Success.
 230   }
 231
 232   Return(0)                               // Return Failure.
 233 }
 234
 235 // SMBus Read Byte - This function will read a single byte of data
 236 // from a specific slave device per SMBus Read Byte Protocol.
 237 //      Arg0 = Address
 238 //      Arg1 = Command
 239 //      Return: Success = Byte-Size Value
 240 //              Failure = Word-Size Value
 241
 242 Method(SRDB,2,Serialized)
 243 {
 244   OperationRegion(SMPB,PCI_Config,0x20,4)
 245   Field(SMPB,DWordAcc,NoLock,Preserve)
 246   {
 247     ,     5,
 248     SBAR, 11
 249   }
 250
 251   // Define various SMBus IO Mapped Registers.
 252
 253   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 254   Field(SMBI,ByteAcc,NoLock,Preserve)
 255   {
 256     HSTS, 8,        // 0 - Host Status Register
 257     Offset(0x02),
 258     HCON, 8,        // 2 - Host Control
 259     HCOM, 8,        // 3 - Host Command
 260     TXSA, 8,        // 4 - Transmit Slave Address
 261     DAT0, 8,        // 5 - Host Data 0
 262     DAT1, 8,        // 6 - Host Data 1
 263     HBDR, 8,        // 7 - Host Block Data
 264     PECR, 8,        // 8 - Packer Error Check
 265     RXSA, 8,        // 9 - Receive Slave Address
 266     SDAT, 16,       // A - Slave Data
 267   }
 268   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 269
 270   If(STRT())
 271   {
 272     Return(0xFFFF)
 273   }
 274
 275   // Step 2:  Initiate a Read Byte.
 276
 277   Store(0,I2CE)                           // Ensure SMbus Mode.
 278   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 279   Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
 280   Store(Arg1,HCOM)                        // Command in HCOM.
 281
 282   // Set the SMBus Host control register to 0x48.
 283   //   Bit 7:    =  0  = reserved
 284   //   Bit 6:    =  1  = start
 285   //   Bit 5:    =  0  = disregard, I2C related bit
 286   //   Bits 4:2: = 010 = Byte Data Protocol
 287   //   Bit 1:    =  0  = Normal Function
 288   //   Bit 0:    =  0  = Disable interrupt generation
 289
 290   Store(0x48,HCON)
 291
 292   // Step 3:  Exit the Method correctly.
 293
 294   If(COMP)
 295   {
 296     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
 297     Return(DAT0)                    // Return Success.
 298   }
 299
 300   Return(0xFFFF)                          // Return Failure.
 301 }
 302
 303 // SMBus Write Word - This function will write a single word
 304 // of data to a specific Slave Device per SMBus Write Word
 305 // Protocol.
 306 //      Arg0 = Address
 307 //      Arg1 = Command
 308 //      Arg2 = Data (16 bits in size)
 309 //      Return: Success = 1
 310 //              Failure = 0
 311
 312 Method(SWRW,3,Serialized)
 313 {
 314   OperationRegion(SMPB,PCI_Config,0x20,4)
 315   Field(SMPB,DWordAcc,NoLock,Preserve)
 316   {
 317     ,     5,
 318     SBAR, 11
 319   }
 320
 321   // Define various SMBus IO Mapped Registers.
 322
 323   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 324   Field(SMBI,ByteAcc,NoLock,Preserve)
 325   {
 326     HSTS, 8,        // 0 - Host Status Register
 327     Offset(0x02),
 328         HCON, 8,        // 2 - Host Control
 329         HCOM, 8,        // 3 - Host Command
 330         TXSA, 8,        // 4 - Transmit Slave Address
 331         DAT0, 8,        // 5 - Host Data 0
 332         DAT1, 8,        // 6 - Host Data 1
 333         HBDR, 8,        // 7 - Host Block Data
 334         PECR, 8,        // 8 - Packer Error Check
 335         RXSA, 8,        // 9 - Receive Slave Address
 336         SDAT, 16,       // A - Slave Data
 337   }
 338   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 339
 340   If(STRT())
 341   {
 342     Return(0)
 343   }
 344
 345   // Step 2:  Initiate a Write Word.
 346
 347   Store(0,I2CE)                           // Ensure SMbus Mode.
 348   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 349   Store(Arg0,TXSA)                        // Write Address in TXSA.
 350   Store(Arg1,HCOM)                        // Command in HCOM.
 351   And(Arg2,0xFF,DAT1)                     // Low byte Data in DAT1.
 352   And(ShiftRight(Arg2,8),0xFF,DAT0)       // High byte Data in DAT0.
 353
 354   // Set the SMBus Host control register to 0x4C.
 355   //   Bit 7:    =  0  = reserved
 356   //   Bit 6:    =  1  = start
 357   //   Bit 5:    =  0  = disregard, I2C related bit
 358   //   Bits 4:2: = 011 = Word Data Protocol
 359   //   Bit 1:    =  0  = Normal Function
 360   //   Bit 0:    =  0  = Disable interrupt generation
 361
 362   Store(0x4C,HCON)
 363
 364   // Step 3:  Exit the Method correctly.
 365
 366   If(COMP())
 367   {
 368     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others.
 369     Return(1)                       // Return Success.
 370   }
 371
 372   Return(0)                               // Return Failure.
 373 }
 374
 375 // SMBus Read Word - This function will read a single byte of data
 376 // from a specific slave device per SMBus Read Word Protocol.
 377 //      Arg0 = Address
 378 //      Arg1 = Command
 379 //      Return: Success = Word-Size Value
 380 //              Failure = Dword-Size Value
 381
 382 Method(SRDW,2,Serialized)
 383 {
 384   OperationRegion(SMPB,PCI_Config,0x20,4)
 385   Field(SMPB,DWordAcc,NoLock,Preserve)
 386   {
 387     ,     5,
 388     SBAR, 11
 389   }
 390
 391   // Define various SMBus IO Mapped Registers.
 392
 393   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 394   Field(SMBI,ByteAcc,NoLock,Preserve)
 395   {
 396     HSTS, 8,        // 0 - Host Status Register
 397         Offset(0x02),
 398         HCON, 8,        // 2 - Host Control
 399         HCOM, 8,        // 3 - Host Command
 400         TXSA, 8,        // 4 - Transmit Slave Address
 401         DAT0, 8,        // 5 - Host Data 0
 402         DAT1, 8,        // 6 - Host Data 1
 403         HBDR, 8,        // 7 - Host Block Data
 404         PECR, 8,        // 8 - Packer Error Check
 405         RXSA, 8,        // 9 - Receive Slave Address
 406         SDAT, 16,       // A - Slave Data
 407   }
 408   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 409
 410   If(STRT())
 411   {
 412     Return(0xFFFF)
 413   }
 414
 415   // Step 2:  Initiate a Read Word.
 416
 417   Store(0,I2CE)                           // Ensure SMbus Mode.
 418   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 419   Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
 420   Store(Arg1,HCOM)                        // Command in HCOM.
 421
 422   // Set the SMBus Host control register to 0x4C.
 423   //   Bit 7:    =  0  = reserved
 424   //   Bit 6:    =  1  = start
 425   //   Bit 5:    =  0  = disregard, I2C related bit
 426   //   Bits 4:2: = 011 = Word Data Protocol
 427   //   Bit 1:    =  0  = Normal Function
 428   //   Bit 0:    =  0  = Disable interrupt generation
 429
 430   Store(0x4C,HCON)
 431
 432   // Step 3:  Exit the Method correctly.
 433
 434   If(COMP())
 435   {
 436     Or(HSTS,0xFF,HSTS)                      // Clear INUSE_STS and others.
 437     Return(Or(ShiftLeft(DAT0,8),DAT1))      // Return Success.
 438   }
 439
 440   Return(0xFFFFFFFF)                      // Return Failure.
 441 }
 442
 443 // SMBus Block Write - This function will write an entire block of data
 444 // to a specific slave device per SMBus Block Write Protocol.
 445 //      Arg0 = Address
 446 //      Arg1 = Command
 447 //      Arg2 = Buffer of Data to Write
 448 //      Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write
 449 //      Return: Success = 1
 450 //              Failure = 0
 451
 452 Method(SBLW,4,Serialized)
 453 {
 454   OperationRegion(SMPB,PCI_Config,0x20,4)
 455   Field(SMPB,DWordAcc,NoLock,Preserve)
 456   {
 457     ,     5,
 458     SBAR, 11
 459   }
 460
 461   // Define various SMBus IO Mapped Registers.
 462
 463   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 464   Field(SMBI,ByteAcc,NoLock,Preserve)
 465   {
 466     HSTS, 8,        // 0 - Host Status Register
 467         Offset(0x02),
 468         HCON, 8,        // 2 - Host Control
 469         HCOM, 8,        // 3 - Host Command
 470         TXSA, 8,        // 4 - Transmit Slave Address
 471         DAT0, 8,        // 5 - Host Data 0
 472         DAT1, 8,        // 6 - Host Data 1
 473         HBDR, 8,        // 7 - Host Block Data
 474         PECR, 8,        // 8 - Packer Error Check
 475         RXSA, 8,        // 9 - Receive Slave Address
 476         SDAT, 16,       // A - Slave Data
 477   }
 478   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 479
 480   If(STRT())
 481   {
 482     Return(0)
 483   }
 484
 485   // Step 2:  Initiate a Block Write.
 486
 487   Store(Arg3,I2CE)                        // Select the proper protocol.
 488   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 489   Store(Arg0,TXSA)                        // Write Address in TXSA.
 490   Store(Arg1,HCOM)                        // Command in HCOM.
 491   Store(Sizeof(Arg2),DAT0)                // Count in DAT0.
 492   Store(0,Local1)                         // Init Pointer to Buffer.
 493   Store(DerefOf(Index(Arg2,0)),HBDR)      // First Byte in HBD Register.
 494
 495   // Set the SMBus Host control register to 0x48.
 496   //   Bit 7:    =  0  = reserved
 497   //   Bit 6:    =  1  = start
 498   //   Bit 5:    =  0  = disregard, I2C related bit
 499   //   Bits 4:2: = 101 = Block Protocol
 500   //   Bit 1:    =  0  = Normal Function
 501   //   Bit 0:    =  0  = Disable interrupt generation
 502
 503   Store(0x54,HCON)
 504
 505   // Step 3:  Send the entire Block of Data.
 506
 507   While(LGreater(Sizeof(Arg2),Local1))
 508   {
 509     // Wait up to 200ms for Host Status to get set.
 510
 511     Store(4000,Local0)              // 4000 * 50us = 200ms.
 512
 513     While(LAnd(LNot(And(HSTS,0x80)),Local0))
 514     {
 515       Decrement(Local0)       // Decrement Count.
 516       Stall(50)               // Delay = 50us.
 517     }
 518
 519     If(LNot(Local0))                // Timeout?
 520     {
 521       KILL()                  // Yes.  Kill Communication.
 522       Return(0)               // Return failure.
 523     }
 524
 525     Store(0x80,HSTS)                // Clear Host Status.
 526     Increment(Local1)               // Point to Next Byte.
 527
 528     // Place next byte in HBDR if last byte has not been sent.
 529
 530     If(LGreater(Sizeof(Arg2),Local1))
 531     {
 532       Store(DerefOf(Index(Arg2,Local1)),HBDR)
 533     }
 534   }
 535
 536   // Step 4:  Exit the Method correctly.
 537
 538   If(COMP())
 539   {
 540     Or(HSTS,0xFF,HSTS)              // Clear all status bits.
 541     Return(1)                       // Return Success.
 542   }
 543
 544   Return(0)                               // Return Failure.
 545 }
 546
 547 // SMBus Block Read - This function will read a block of data from
 548 // a specific slave device per SMBus Block Read Protocol.
 549 //      Arg0 = Address
 550 //      Arg1 = Command
 551 //      Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write
 552 //      Return: Success = Data Buffer (First Byte = length)
 553 //              Failure = 0
 554
 555 Method(SBLR,3,Serialized)
 556 {
 557   OperationRegion(SMPB,PCI_Config,0x20,4)
 558   Field(SMPB,DWordAcc,NoLock,Preserve)
 559   {
 560     ,     5,
 561     SBAR, 11
 562   }
 563
 564   // Define various SMBus IO Mapped Registers.
 565
 566   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 567   Field(SMBI,ByteAcc,NoLock,Preserve)
 568   {
 569     HSTS, 8,        // 0 - Host Status Register
 570         Offset(0x02),
 571         HCON, 8,        // 2 - Host Control
 572         HCOM, 8,        // 3 - Host Command
 573         TXSA, 8,        // 4 - Transmit Slave Address
 574         DAT0, 8,        // 5 - Host Data 0
 575         DAT1, 8,        // 6 - Host Data 1
 576         HBDR, 8,        // 7 - Host Block Data
 577         PECR, 8,        // 8 - Packer Error Check
 578         RXSA, 8,        // 9 - Receive Slave Address
 579         SDAT, 16,       // A - Slave Data
 580   }
 581   Name(TBUF, Buffer(256) {})
 582
 583   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 584
 585   If(STRT())
 586   {
 587     Return(0)
 588   }
 589
 590   // Step 2:  Initiate a Block Read.
 591
 592   Store(Arg2,I2CE)                        // Select the proper protocol.
 593   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 594   Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
 595   Store(Arg1,HCOM)                        // Command in HCOM.
 596
 597   // Set the SMBus Host control register to 0x48.
 598   //   Bit 7:    =  0  = reserved
 599   //   Bit 6:    =  1  = start
 600   //   Bit 5:    =  0  = disregard, I2C related bit
 601   //   Bits 4:2: = 101 = Block Protocol
 602   //   Bit 1:    =  0  = Normal Function
 603   //   Bit 0:    =  0  = Disable interrupt generation
 604
 605   Store(0x54,HCON)
 606
 607   // Step 3:  Wait up to 200ms to get the Data Count.
 608
 609   Store(4000,Local0)                      // 4000 * 50us = 200ms.
 610
 611   While(LAnd(LNot(And(HSTS,0x80)),Local0))
 612   {
 613     Decrement(Local0)               // Decrement Count.
 614     Stall(50)                       // Delay = 50us.
 615   }
 616
 617   If(LNot(Local0))                        // Timeout?
 618   {
 619     KILL()                          // Yes.  Kill Communication.
 620     Return(0)                       // Return failure.
 621   }
 622
 623   Store(DAT0,Index(TBUF,0))               // Get the Data Count.
 624   Store(0x80,HSTS)                        // Clear Host Status.
 625   Store(1,Local1)                         // Local1 = Buffer Pointer.
 626
 627   // Step 4:  Get the Block Data and store it.
 628
 629   While(LLess(Local1,DerefOf(Index(TBUF,0))))
 630   {
 631     // Wait up to 200ms for Host Status to get set.
 632
 633     Store(4000,Local0)              // 4000 * 50us = 200ms.
 634
 635     While(LAnd(LNot(And(HSTS,0x80)),Local0))
 636     {
 637       Decrement(Local0)       // Decrement Count.
 638       Stall(50)               // Delay = 50us.
 639     }
 640
 641     If(LNot(Local0))                // Timeout?
 642     {
 643       KILL()                  // Yes.  Kill Communication.
 644       Return(0)               // Return failure.
 645     }
 646
 647     Store(HBDR,Index(TBUF,Local1))  // Place into Buffer.
 648     Store(0x80,HSTS)                // Clear Host Status.
 649     Increment(Local1)
 650   }
 651
 652   // Step 5:  Exit the Method correctly.
 653
 654   If(COMP())
 655   {
 656     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others.
 657     Return(TBUF)                    // Return Success.
 658   }
 659
 660   Return(0)                               // Return Failure.
 661 }
 662
 663
 664 // SMBus Start Check
 665 //      Return: Success = 0
 666 //              Failure = 1
 667
 668 Method(STRT,0,Serialized)
 669 {
 670   OperationRegion(SMPB,PCI_Config,0x20,4)
 671   Field(SMPB,DWordAcc,NoLock,Preserve)
 672   {
 673     ,     5,
 674     SBAR, 11
 675   }
 676
 677   // Define various SMBus IO Mapped Registers.
 678
 679   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 680   Field(SMBI,ByteAcc,NoLock,Preserve)
 681   {
 682     HSTS, 8,        // 0 - Host Status Register
 683         Offset(0x02),
 684         HCON, 8,        // 2 - Host Control
 685         HCOM, 8,        // 3 - Host Command
 686         TXSA, 8,        // 4 - Transmit Slave Address
 687         DAT0, 8,        // 5 - Host Data 0
 688         DAT1, 8,        // 6 - Host Data 1
 689         HBDR, 8,        // 7 - Host Block Data
 690         PECR, 8,        // 8 - Packer Error Check
 691         RXSA, 8,        // 9 - Receive Slave Address
 692         SDAT, 16,       // A - Slave Data
 693   }
 694   // Wait up to 200ms to confirm the SMBus Semaphore has been
 695   // released (In Use Status = 0).  Note that the Sleep time may take
 696   // longer as the This function will yield the Processor such that it
 697   // may perform different tasks during the delay.
 698
 699   Store(200,Local0)                       // 200 * 1ms = 200ms.
 700
 701   While(Local0)
 702   {
 703     If(And(HSTS,0x40))              // In Use Set?
 704     {
 705       Decrement(Local0)       // Yes.  Decrement Count.
 706       Sleep(1)                // Delay = 1ms.
 707       If(LEqual(Local0,0))    // Count = 0?
 708       {
 709         Return(1)       // Return failure.
 710       }
 711     }
 712     Else
 713     {
 714       Store(0,Local0)         // In Use Clear.  Continue.
 715     }
 716   }
 717
 718   // In Use Status = 0 during last read, which will make subsequent
 719   // reads return In Use Status = 1 until software clears it.  All
 720   // software using ICHx SMBus should check this bit before initiating
 721   // any SMBus communication.
 722
 723   // Wait up to 200ms to confirm the Host Interface is
 724   // not processing a command.
 725
 726   Store(4000,Local0)                      // 4000 * 50us = 200ms.
 727
 728   While(Local0)
 729   {
 730     If(And(HSTS,0x01))              // Host Busy Set?
 731     {
 732       Decrement(Local0)       // Decrement Count.
 733       Stall(50)               // Delay = 50us.
 734       If(LEqual(Local0,0))    // Count = 0?
 735       {
 736         KILL()          // Yes.  Kill Communication.
 737       }
 738     }
 739     Else
 740     {
 741       Return(0)
 742     }
 743   }
 744
 745   Return(1)                               // Timeout.  Return failure.
 746 }
 747
 748 // SMBus Completion Check
 749 //      Return: Success = 1
 750 //              Failure = 0
 751
 752 Method(COMP,0,Serialized)
 753 {
 754   OperationRegion(SMPB,PCI_Config,0x20,4)
 755   Field(SMPB,DWordAcc,NoLock,Preserve)
 756   {
 757     ,     5,
 758     SBAR, 11
 759   }
 760
 761   // Define various SMBus IO Mapped Registers.
 762
 763   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 764   Field(SMBI,ByteAcc,NoLock,Preserve)
 765   {
 766     HSTS, 8,        // 0 - Host Status Register
 767         Offset(0x02),
 768         HCON, 8,        // 2 - Host Control
 769         HCOM, 8,        // 3 - Host Command
 770         TXSA, 8,        // 4 - Transmit Slave Address
 771         DAT0, 8,        // 5 - Host Data 0
 772         DAT1, 8,        // 6 - Host Data 1
 773         HBDR, 8,        // 7 - Host Block Data
 774         PECR, 8,        // 8 - Packer Error Check
 775         RXSA, 8,        // 9 - Receive Slave Address
 776         SDAT, 16,       // A - Slave Data
 777   }
 778   // Wait for up to 200ms for the Completion Command
 779   // Status to get set.
 780
 781   Store(4000,Local0)                      // 4000 * 50us = 200ms.
 782
 783   While(Local0)
 784   {
 785     If(And(HSTS,0x02))              // Completion Status Set?
 786     {
 787       Return(1)               // Yes.  We are done.
 788     }
 789     Else
 790     {
 791       Decrement(Local0)       // Decrement Count.
 792       Stall(50)               // Delay 50us.
 793       If(LEqual(Local0,0))    // Count = 0?
 794       {
 795         KILL()          // Yes.  Kill Communication.
 796       }
 797     }
 798   }
 799
 800   Return(0)                               // Timeout.  Return Failure.
 801 }
 802
 803 // SMBus Kill Command
 804
 805 Method(KILL,0,Serialized)
 806 {
 807   OperationRegion(SMPB,PCI_Config,0x20,4)
 808   Field(SMPB,DWordAcc,NoLock,Preserve)
 809   {
 810     ,     5,
 811     SBAR, 11
 812   }
 813
 814   // Define various SMBus IO Mapped Registers.
 815
 816   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 817   Field(SMBI,ByteAcc,NoLock,Preserve)
 818   {
 819     HSTS, 8,        // 0 - Host Status Register
 820         Offset(0x02),
 821         HCON, 8,        // 2 - Host Control
 822         HCOM, 8,        // 3 - Host Command
 823         TXSA, 8,        // 4 - Transmit Slave Address
 824         DAT0, 8,        // 5 - Host Data 0
 825         DAT1, 8,        // 6 - Host Data 1
 826         HBDR, 8,        // 7 - Host Block Data
 827         PECR, 8,        // 8 - Packer Error Check
 828         RXSA, 8,        // 9 - Receive Slave Address
 829         SDAT, 16,       // A - Slave Data
 830   }
 831   Or(HCON,0x02,HCON)                      // Yes.  Send Kill command.
 832   Or(HSTS,0xFF,HSTS)                      // Clear all status.
 833 }