Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl

   1 /**************************************************************************;
   2 ;*                                                                        *;
   3 ;*                                                                        *;
   4 ;*    Intel Corporation - ACPI Reference Code for the Sandy Bridge        *;
   5 ;*    Family of Customer Reference Boards.                                *;
   6 ;*                                                                        *;
   7 ;*                                                                        *;
   8 ;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
   9 ;
  10 ; This program and the accompanying materials are licensed and made available under
  11 ; the terms and conditions of the BSD License that accompanies this distribution.
  12 ; The full text of the license may be found at
  13 ; http://opensource.org/licenses/bsd-license.php.
  14 ;
  15 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17 ;
  18 ;*                                                                        *;
  19 ;*                                                                        *;
  20 ;**************************************************************************/
  21
  22 Scope(\_SB)
  23 {
  24
  25 //RTC
  26   Device(RTC)    // RTC
  27   {
  28     Name(_HID,EISAID("PNP0B00"))
  29
  30     Name(_CRS,ResourceTemplate()
  31     {
  32       IO(Decode16,0x70,0x70,0x01,0x08)
  33     })
  34   }
  35 //RTC
  36
  37   Device(HPET)   // High Performance Event Timer
  38   {
  39     Name (_HID, EisaId ("PNP0103"))
  40     Name (_UID, 0x00)
  41     Method (_STA, 0, NotSerialized)
  42     {
  43       Return (0x0F)
  44     }
  45
  46     Method (_CRS, 0, Serialized)
  47     {
  48       Name (RBUF, ResourceTemplate ()
  49       {
  50         Memory32Fixed (ReadWrite,
  51                        0xFED00000,         // Address Base
  52                        0x00000400,         // Address Length
  53                       )
  54         Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
  55         {
  56           0x00000008,   //0xB HPET-2
  57         }
  58       })
  59       Return (RBUF)
  60     }
  61   }
  62 //HPET
  63
  64   Name(PR00, Package()
  65   {
  66 // SD Host #0 - eMMC
  67     Package() {0x0010FFFF, 0, LNKA, 0 },
  68 // SD Host #1 - SDIO
  69     Package() {0x0011FFFF, 0, LNKB, 0 },
  70 // SD Host #2 - SD Card
  71     Package() {0x0012FFFF, 0, LNKC, 0 },
  72 // SATA Controller
  73     Package() {0x0013FFFF, 0, LNKD, 0 },
  74 // xHCI Host
  75     Package() {0x0014FFFF, 0, LNKE, 0 },
  76 // Low Power Audio Engine
  77     Package() {0x0015FFFF, 0, LNKF, 0 },
  78 // USB OTG
  79     Package() {0x0016FFFF, 0, LNKG, 0 },
  80 // MIPI-HSI/eMMC4.5
  81     Package() {0x0017FFFF, 0, LNKH, 0 },
  82 // LPSS2 DMA
  83 // LPSS2 I2C #4
  84     Package() {0x0018FFFF, 0, LNKB, 0 },
  85 // LPSS2 I2C #1
  86 // LPSS2 I2C #5
  87     Package() {0x0018FFFF, 2, LNKD, 0 },
  88 // LPSS2 I2C #2
  89 // LPSS2 I2C #6
  90     Package() {0x0018FFFF, 3, LNKC, 0 },
  91 // LPSS2 I2C #3
  92 // LPSS2 I2C #7
  93     Package() {0x0018FFFF, 1, LNKA, 0 },
  94 // SeC
  95     Package() {0x001AFFFF, 0, LNKF, 0 },
  96 //
  97 // High Definition Audio Controller
  98     Package() {0x001BFFFF, 0, LNKG, 0 },
  99 //
 100 // EHCI Controller
 101     Package() {0x001DFFFF, 0, LNKH, 0 },
 102 // LPSS DMA
 103     Package() {0x001EFFFF, 0, LNKD, 0 },
 104 // LPSS I2C #0
 105     Package() {0x001EFFFF, 3, LNKA, 0 },
 106 // LPSS I2C #1
 107     Package() {0x001EFFFF, 1, LNKB, 0 },
 108 // LPSS PCM
 109     Package() {0x001EFFFF, 2, LNKC, 0 },
 110 // LPSS I2S
 111 // LPSS HS-UART #0
 112 // LPSS HS-UART #1
 113 // LPSS SPI
 114 // LPC Bridge
 115 //
 116 // SMBus Controller
 117     Package() {0x001FFFFF, 1, LNKC, 0 },
 118 //
 119 // PCIE Root Port #1
 120     Package() {0x001CFFFF, 0, LNKA, 0 },
 121 // PCIE Root Port #2
 122     Package() {0x001CFFFF, 1, LNKB, 0 },
 123 // PCIE Root Port #3
 124     Package() {0x001CFFFF, 2, LNKC, 0 },
 125 // PCIE Root Port #4
 126     Package() {0x001CFFFF, 3, LNKD, 0 },
 127
 128 // Host Bridge
 129 // Mobile IGFX
 130     Package() {0x0002FFFF, 0, LNKA, 0 },
 131   })
 132
 133   Name(AR00, Package()
 134   {
 135 // SD Host #0 - eMMC
 136     Package() {0x0010FFFF, 0, 0, 16 },
 137 // SD Host #1 - SDIO
 138     Package() {0x0011FFFF, 0, 0, 17 },
 139 // SD Host #2 - SD Card
 140     Package() {0x0012FFFF, 0, 0, 18 },
 141 // SATA Controller
 142     Package() {0x0013FFFF, 0, 0, 19 },
 143 // xHCI Host
 144     Package() {0x0014FFFF, 0, 0, 20 },
 145 // Low Power Audio Engine
 146     Package() {0x0015FFFF, 0, 0, 21 },
 147 // USB OTG
 148     Package() {0x0016FFFF, 0, 0, 22 },
 149 //
 150 // MIPI-HSI
 151     Package() {0x0017FFFF, 0, 0, 23 },
 152 //
 153 // LPSS2 DMA
 154 // LPSS2 I2C #4
 155     Package() {0x0018FFFF, 0, 0, 17 },
 156 // LPSS2 I2C #1
 157 // LPSS2 I2C #5
 158     Package() {0x0018FFFF, 2, 0, 19 },
 159 // LPSS2 I2C #2
 160 // LPSS2 I2C #6
 161     Package() {0x0018FFFF, 3, 0, 18 },
 162 // LPSS2 I2C #3
 163 // LPSS2 I2C #7
 164     Package() {0x0018FFFF, 1, 0, 16 },
 165
 166 // SeC
 167     Package() {0x001AFFFF, 0, 0, 21 },
 168 //
 169 // High Definition Audio Controller
 170     Package() {0x001BFFFF, 0, 0, 22 },
 171 //
 172 // EHCI Controller
 173     Package() {0x001DFFFF, 0, 0, 23 },
 174 // LPSS DMA
 175     Package() {0x001EFFFF, 0, 0, 19 },
 176 // LPSS I2C #0
 177     Package() {0x001EFFFF, 3, 0, 16 },
 178 // LPSS I2C #1
 179     Package() {0x001EFFFF, 1, 0, 17 },
 180 // LPSS PCM
 181     Package() {0x001EFFFF, 2, 0, 18 },
 182 // LPSS I2S
 183 // LPSS HS-UART #0
 184 // LPSS HS-UART #1
 185 // LPSS SPI
 186 // LPC Bridge
 187 //
 188 // SMBus Controller
 189     Package() {0x001FFFFF, 1, 0, 18 },
 190 //
 191 // PCIE Root Port #1
 192     Package() {0x001CFFFF, 0, 0, 16 },
 193 // PCIE Root Port #2
 194     Package() {0x001CFFFF, 1, 0, 17 },
 195 // PCIE Root Port #3
 196     Package() {0x001CFFFF, 2, 0, 18 },
 197 // PCIE Root Port #4
 198     Package() {0x001CFFFF, 3, 0, 19 },
 199 // Host Bridge
 200 // Mobile IGFX
 201     Package() {0x0002FFFF, 0, 0, 16 },
 202   })
 203
 204   Name(PR04, Package()
 205   {
 206 // PCIE Port #1 Slot
 207     Package() {0x0000FFFF, 0, LNKA, 0 },
 208     Package() {0x0000FFFF, 1, LNKB, 0 },
 209     Package() {0x0000FFFF, 2, LNKC, 0 },
 210     Package() {0x0000FFFF, 3, LNKD, 0 },
 211   })
 212
 213   Name(AR04, Package()
 214   {
 215 // PCIE Port #1 Slot
 216     Package() {0x0000FFFF, 0, 0, 16 },
 217     Package() {0x0000FFFF, 1, 0, 17 },
 218     Package() {0x0000FFFF, 2, 0, 18 },
 219     Package() {0x0000FFFF, 3, 0, 19 },
 220   })
 221
 222   Name(PR05, Package()
 223   {
 224 // PCIE Port #2 Slot
 225     Package() {0x0000FFFF, 0, LNKB, 0 },
 226     Package() {0x0000FFFF, 1, LNKC, 0 },
 227     Package() {0x0000FFFF, 2, LNKD, 0 },
 228     Package() {0x0000FFFF, 3, LNKA, 0 },
 229   })
 230
 231   Name(AR05, Package()
 232   {
 233 // PCIE Port #2 Slot
 234     Package() {0x0000FFFF, 0, 0, 17 },
 235     Package() {0x0000FFFF, 1, 0, 18 },
 236     Package() {0x0000FFFF, 2, 0, 19 },
 237     Package() {0x0000FFFF, 3, 0, 16 },
 238   })
 239
 240   Name(PR06, Package()
 241   {
 242 // PCIE Port #3 Slot
 243     Package() {0x0000FFFF, 0, LNKC, 0 },
 244     Package() {0x0000FFFF, 1, LNKD, 0 },
 245     Package() {0x0000FFFF, 2, LNKA, 0 },
 246     Package() {0x0000FFFF, 3, LNKB, 0 },
 247   })
 248
 249   Name(AR06, Package()
 250   {
 251 // PCIE Port #3 Slot
 252     Package() {0x0000FFFF, 0, 0, 18 },
 253     Package() {0x0000FFFF, 1, 0, 19 },
 254     Package() {0x0000FFFF, 2, 0, 16 },
 255     Package() {0x0000FFFF, 3, 0, 17 },
 256   })
 257
 258   Name(PR07, Package()
 259   {
 260 // PCIE Port #4 Slot
 261     Package() {0x0000FFFF, 0, LNKD, 0 },
 262     Package() {0x0000FFFF, 1, LNKA, 0 },
 263     Package() {0x0000FFFF, 2, LNKB, 0 },
 264     Package() {0x0000FFFF, 3, LNKC, 0 },
 265   })
 266
 267   Name(AR07, Package()
 268   {
 269 // PCIE Port #4 Slot
 270     Package() {0x0000FFFF, 0, 0, 19 },
 271     Package() {0x0000FFFF, 1, 0, 16 },
 272     Package() {0x0000FFFF, 2, 0, 17 },
 273     Package() {0x0000FFFF, 3, 0, 18 },
 274   })
 275
 276   Name(PR01, Package()
 277   {
 278 // PCI slot 1
 279     Package() {0x0000FFFF, 0, LNKF, 0 },
 280     Package() {0x0000FFFF, 1, LNKG, 0 },
 281     Package() {0x0000FFFF, 2, LNKH, 0 },
 282     Package() {0x0000FFFF, 3, LNKE, 0 },
 283 // PCI slot 2
 284     Package() {0x0001FFFF, 0, LNKG, 0 },
 285     Package() {0x0001FFFF, 1, LNKF, 0 },
 286     Package() {0x0001FFFF, 2, LNKE, 0 },
 287     Package() {0x0001FFFF, 3, LNKH, 0 },
 288 // PCI slot 3
 289     Package() {0x0002FFFF, 0, LNKC, 0 },
 290     Package() {0x0002FFFF, 1, LNKD, 0 },
 291     Package() {0x0002FFFF, 2, LNKB, 0 },
 292     Package() {0x0002FFFF, 3, LNKA, 0 },
 293 // PCI slot 4
 294     Package() {0x0003FFFF, 0, LNKD, 0 },
 295     Package() {0x0003FFFF, 1, LNKC, 0 },
 296     Package() {0x0003FFFF, 2, LNKF, 0 },
 297     Package() {0x0003FFFF, 3, LNKG, 0 },
 298   })
 299
 300   Name(AR01, Package()
 301   {
 302 // PCI slot 1
 303     Package() {0x0000FFFF, 0, 0, 21 },
 304     Package() {0x0000FFFF, 1, 0, 22 },
 305     Package() {0x0000FFFF, 2, 0, 23 },
 306     Package() {0x0000FFFF, 3, 0, 20 },
 307 // PCI slot 2
 308     Package() {0x0001FFFF, 0, 0, 22 },
 309     Package() {0x0001FFFF, 1, 0, 21 },
 310     Package() {0x0001FFFF, 2, 0, 20 },
 311     Package() {0x0001FFFF, 3, 0, 23 },
 312 // PCI slot 3
 313     Package() {0x0002FFFF, 0, 0, 18 },
 314     Package() {0x0002FFFF, 1, 0, 19 },
 315     Package() {0x0002FFFF, 2, 0, 17 },
 316     Package() {0x0002FFFF, 3, 0, 16 },
 317 // PCI slot 4
 318     Package() {0x0003FFFF, 0, 0, 19 },
 319     Package() {0x0003FFFF, 1, 0, 18 },
 320     Package() {0x0003FFFF, 2, 0, 21 },
 321     Package() {0x0003FFFF, 3, 0, 22 },
 322   })
 323 //---------------------------------------------------------------------------
 324 // List of IRQ resource buffers compatible with _PRS return format.
 325 //---------------------------------------------------------------------------
 326 // Naming legend:
 327 // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.
 328 // Note. PRSy name is generated if IRQ Link name starts from "LNK".
 329 // HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
 330 //---------------------------------------------------------------------------
 331   Name(PRSA, ResourceTemplate()         // Link name: LNKA
 332   {
 333     IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
 334   })
 335   Alias(PRSA,PRSB)      // Link name: LNKB
 336   Alias(PRSA,PRSC)      // Link name: LNKC
 337   Alias(PRSA,PRSD)      // Link name: LNKD
 338   Alias(PRSA,PRSE)      // Link name: LNKE
 339   Alias(PRSA,PRSF)      // Link name: LNKF
 340   Alias(PRSA,PRSG)      // Link name: LNKG
 341   Alias(PRSA,PRSH)      // Link name: LNKH
 342 //---------------------------------------------------------------------------
 343 // Begin PCI tree object scope
 344 //---------------------------------------------------------------------------
 345
 346   Device(PCI0)   // PCI Bridge "Host Bridge"
 347   {
 348     Name(_HID, EISAID("PNP0A08"))       // Indicates PCI Express/PCI-X Mode2 host hierarchy
 349     Name(_CID, EISAID("PNP0A03"))       // To support legacy OS that doesn't understand the new HID
 350     Name(_ADR, 0x00000000)
 351     Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
 352     Method(_BBN, 0) { return(BN00()) }  // Bus number, optional for the Root PCI Bus
 353     Name(_UID, 0x0000)  // Unique Bus ID, optional
 354     Name(_DEP, Package(0x1)
 355     {
 356       PEPD
 357     })
 358
 359                             Method(_PRT,0)
 360     {
 361       If(PICM) {Return(AR00)} // APIC mode
 362       Return (PR00) // PIC Mode
 363     } // end _PRT
 364
 365     include("HOST_BUS.ASL")
 366     Device(LPCB)   // LPC Bridge
 367     {
 368       Name(_ADR, 0x001F0000)
 369       include("LpcB.asl")
 370     } // end "LPC Bridge"
 371
 372   } // end PCI0 Bridge "Host Bridge"
 373 } // end _SB scope