Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl

   1 /**************************************************************************;
   2 ;*                                                                        *;
   3 ;*                                                                        *;
   4 ;*    Intel Corporation - ACPI Reference Code for the Sandy Bridge        *;
   5 ;*    Family of Customer Reference Boards.                                *;
   6 ;*                                                                        *;
   7 ;*                                                                        *;
   8 ;*    Copyright (c) 2012  - 2015, Intel Corporation. All rights reserved    *;
   9 ;
  10 ; SPDX-License-Identifier: BSD-2-Clause-Patent
  11 ;
  12 ;*                                                                        *;
  13 ;*                                                                        *;
  14 ;**************************************************************************/
  15
  16 Scope(\_SB)
  17 {
  18 //RTC
  19   Device(RTC)    // RTC
  20   {
  21     Name(_HID,EISAID("PNP0B00"))
  22
  23     Name(_CRS,ResourceTemplate()
  24     {
  25       IO(Decode16,0x70,0x70,0x01,0x08)
  26     })
  27
  28     Method(_STA,0,Serialized) {
  29
  30       //
  31       // Report RTC Battery is Prensent or Not Present.
  32       //
  33       If (LEqual(BATT, 1)) {
  34         Return (0xF)
  35       }
  36       Return (0x0)
  37     }
  38   }
  39 //RTC
  40
  41   Device(HPET)   // High Performance Event Timer
  42   {
  43     Name (_HID, EisaId ("PNP0103"))
  44     Name (_UID, 0x00)
  45     Method (_STA, 0, NotSerialized)
  46     {
  47       Return (0x0F)
  48     }
  49
  50     Method (_CRS, 0, Serialized)
  51     {
  52       Name (RBUF, ResourceTemplate ()
  53       {
  54         Memory32Fixed (ReadWrite,
  55                        0xFED00000,         // Address Base
  56                        0x00000400,         // Address Length
  57                       )
  58         Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
  59         {
  60           0x00000008,   //0xB HPET-2
  61         }
  62       })
  63       Return (RBUF)
  64     }
  65   }
  66 //HPET
  67
  68   Name(PR00, Package()
  69   {
  70 // SD Host #0 - eMMC
  71     Package() {0x0010FFFF, 0, LNKA, 0 },
  72 // SD Host #1 - SDIO
  73     Package() {0x0011FFFF, 0, LNKB, 0 },
  74 // SD Host #2 - SD Card
  75     Package() {0x0012FFFF, 0, LNKC, 0 },
  76 // SATA Controller
  77     Package() {0x0013FFFF, 0, LNKD, 0 },
  78 // xHCI Host
  79     Package() {0x0014FFFF, 0, LNKE, 0 },
  80 // Low Power Audio Engine
  81     Package() {0x0015FFFF, 0, LNKF, 0 },
  82 // USB OTG
  83     Package() {0x0016FFFF, 0, LNKG, 0 },
  84 // MIPI-HSI/eMMC4.5
  85     Package() {0x0017FFFF, 0, LNKH, 0 },
  86 // LPSS2 DMA
  87 // LPSS2 I2C #4
  88     Package() {0x0018FFFF, 0, LNKB, 0 },
  89 // LPSS2 I2C #1
  90 // LPSS2 I2C #5
  91     Package() {0x0018FFFF, 2, LNKD, 0 },
  92 // LPSS2 I2C #2
  93 // LPSS2 I2C #6
  94     Package() {0x0018FFFF, 3, LNKC, 0 },
  95 // LPSS2 I2C #3
  96 // LPSS2 I2C #7
  97     Package() {0x0018FFFF, 1, LNKA, 0 },
  98 // SeC
  99     Package() {0x001AFFFF, 0, LNKF, 0 },
 100 //
 101 // High Definition Audio Controller
 102     Package() {0x001BFFFF, 0, LNKG, 0 },
 103 //
 104 // EHCI Controller
 105     Package() {0x001DFFFF, 0, LNKH, 0 },
 106 // LPSS DMA
 107     Package() {0x001EFFFF, 0, LNKD, 0 },
 108 // LPSS I2C #0
 109     Package() {0x001EFFFF, 3, LNKA, 0 },
 110 // LPSS I2C #1
 111     Package() {0x001EFFFF, 1, LNKB, 0 },
 112 // LPSS PCM
 113     Package() {0x001EFFFF, 2, LNKC, 0 },
 114 // LPSS I2S
 115 // LPSS HS-UART #0
 116 // LPSS HS-UART #1
 117 // LPSS SPI
 118 // LPC Bridge
 119 //
 120 // SMBus Controller
 121     Package() {0x001FFFFF, 1, LNKC, 0 },
 122 //
 123 // PCIE Root Port #1
 124     Package() {0x001CFFFF, 0, LNKA, 0 },
 125 // PCIE Root Port #2
 126     Package() {0x001CFFFF, 1, LNKB, 0 },
 127 // PCIE Root Port #3
 128     Package() {0x001CFFFF, 2, LNKC, 0 },
 129 // PCIE Root Port #4
 130     Package() {0x001CFFFF, 3, LNKD, 0 },
 131
 132 // Host Bridge
 133 // Mobile IGFX
 134     Package() {0x0002FFFF, 0, LNKA, 0 },
 135   })
 136
 137   Name(AR00, Package()
 138   {
 139 // SD Host #0 - eMMC
 140     Package() {0x0010FFFF, 0, 0, 16 },
 141 // SD Host #1 - SDIO
 142     Package() {0x0011FFFF, 0, 0, 17 },
 143 // SD Host #2 - SD Card
 144     Package() {0x0012FFFF, 0, 0, 18 },
 145 // SATA Controller
 146     Package() {0x0013FFFF, 0, 0, 19 },
 147 // xHCI Host
 148     Package() {0x0014FFFF, 0, 0, 20 },
 149 // Low Power Audio Engine
 150     Package() {0x0015FFFF, 0, 0, 21 },
 151 // USB OTG
 152     Package() {0x0016FFFF, 0, 0, 22 },
 153 //
 154 // MIPI-HSI
 155     Package() {0x0017FFFF, 0, 0, 23 },
 156 //
 157 // LPSS2 DMA
 158 // LPSS2 I2C #4
 159     Package() {0x0018FFFF, 0, 0, 17 },
 160 // LPSS2 I2C #1
 161 // LPSS2 I2C #5
 162     Package() {0x0018FFFF, 2, 0, 19 },
 163 // LPSS2 I2C #2
 164 // LPSS2 I2C #6
 165     Package() {0x0018FFFF, 3, 0, 18 },
 166 // LPSS2 I2C #3
 167 // LPSS2 I2C #7
 168     Package() {0x0018FFFF, 1, 0, 16 },
 169
 170 // SeC
 171     Package() {0x001AFFFF, 0, 0, 21 },
 172 //
 173 // High Definition Audio Controller
 174     Package() {0x001BFFFF, 0, 0, 22 },
 175 //
 176 // EHCI Controller
 177     Package() {0x001DFFFF, 0, 0, 23 },
 178 // LPSS DMA
 179     Package() {0x001EFFFF, 0, 0, 19 },
 180 // LPSS I2C #0
 181     Package() {0x001EFFFF, 3, 0, 16 },
 182 // LPSS I2C #1
 183     Package() {0x001EFFFF, 1, 0, 17 },
 184 // LPSS PCM
 185     Package() {0x001EFFFF, 2, 0, 18 },
 186 // LPSS I2S
 187 // LPSS HS-UART #0
 188 // LPSS HS-UART #1
 189 // LPSS SPI
 190 // LPC Bridge
 191 //
 192 // SMBus Controller
 193     Package() {0x001FFFFF, 1, 0, 18 },
 194 //
 195 // PCIE Root Port #1
 196     Package() {0x001CFFFF, 0, 0, 16 },
 197 // PCIE Root Port #2
 198     Package() {0x001CFFFF, 1, 0, 17 },
 199 // PCIE Root Port #3
 200     Package() {0x001CFFFF, 2, 0, 18 },
 201 // PCIE Root Port #4
 202     Package() {0x001CFFFF, 3, 0, 19 },
 203 // Host Bridge
 204 // Mobile IGFX
 205     Package() {0x0002FFFF, 0, 0, 16 },
 206   })
 207
 208   Name(PR04, Package()
 209   {
 210 // PCIE Port #1 Slot
 211     Package() {0x0000FFFF, 0, LNKA, 0 },
 212     Package() {0x0000FFFF, 1, LNKB, 0 },
 213     Package() {0x0000FFFF, 2, LNKC, 0 },
 214     Package() {0x0000FFFF, 3, LNKD, 0 },
 215   })
 216
 217   Name(AR04, Package()
 218   {
 219 // PCIE Port #1 Slot
 220     Package() {0x0000FFFF, 0, 0, 16 },
 221     Package() {0x0000FFFF, 1, 0, 17 },
 222     Package() {0x0000FFFF, 2, 0, 18 },
 223     Package() {0x0000FFFF, 3, 0, 19 },
 224   })
 225
 226   Name(PR05, Package()
 227   {
 228 // PCIE Port #2 Slot
 229     Package() {0x0000FFFF, 0, LNKB, 0 },
 230     Package() {0x0000FFFF, 1, LNKC, 0 },
 231     Package() {0x0000FFFF, 2, LNKD, 0 },
 232     Package() {0x0000FFFF, 3, LNKA, 0 },
 233   })
 234
 235   Name(AR05, Package()
 236   {
 237 // PCIE Port #2 Slot
 238     Package() {0x0000FFFF, 0, 0, 17 },
 239     Package() {0x0000FFFF, 1, 0, 18 },
 240     Package() {0x0000FFFF, 2, 0, 19 },
 241     Package() {0x0000FFFF, 3, 0, 16 },
 242   })
 243
 244   Name(PR06, Package()
 245   {
 246 // PCIE Port #3 Slot
 247     Package() {0x0000FFFF, 0, LNKC, 0 },
 248     Package() {0x0000FFFF, 1, LNKD, 0 },
 249     Package() {0x0000FFFF, 2, LNKA, 0 },
 250     Package() {0x0000FFFF, 3, LNKB, 0 },
 251   })
 252
 253   Name(AR06, Package()
 254   {
 255 // PCIE Port #3 Slot
 256     Package() {0x0000FFFF, 0, 0, 18 },
 257     Package() {0x0000FFFF, 1, 0, 19 },
 258     Package() {0x0000FFFF, 2, 0, 16 },
 259     Package() {0x0000FFFF, 3, 0, 17 },
 260   })
 261
 262   Name(PR07, Package()
 263   {
 264 // PCIE Port #4 Slot
 265     Package() {0x0000FFFF, 0, LNKD, 0 },
 266     Package() {0x0000FFFF, 1, LNKA, 0 },
 267     Package() {0x0000FFFF, 2, LNKB, 0 },
 268     Package() {0x0000FFFF, 3, LNKC, 0 },
 269   })
 270
 271   Name(AR07, Package()
 272   {
 273 // PCIE Port #4 Slot
 274     Package() {0x0000FFFF, 0, 0, 19 },
 275     Package() {0x0000FFFF, 1, 0, 16 },
 276     Package() {0x0000FFFF, 2, 0, 17 },
 277     Package() {0x0000FFFF, 3, 0, 18 },
 278   })
 279
 280   Name(PR01, Package()
 281   {
 282 // PCI slot 1
 283     Package() {0x0000FFFF, 0, LNKF, 0 },
 284     Package() {0x0000FFFF, 1, LNKG, 0 },
 285     Package() {0x0000FFFF, 2, LNKH, 0 },
 286     Package() {0x0000FFFF, 3, LNKE, 0 },
 287 // PCI slot 2
 288     Package() {0x0001FFFF, 0, LNKG, 0 },
 289     Package() {0x0001FFFF, 1, LNKF, 0 },
 290     Package() {0x0001FFFF, 2, LNKE, 0 },
 291     Package() {0x0001FFFF, 3, LNKH, 0 },
 292 // PCI slot 3
 293     Package() {0x0002FFFF, 0, LNKC, 0 },
 294     Package() {0x0002FFFF, 1, LNKD, 0 },
 295     Package() {0x0002FFFF, 2, LNKB, 0 },
 296     Package() {0x0002FFFF, 3, LNKA, 0 },
 297 // PCI slot 4
 298     Package() {0x0003FFFF, 0, LNKD, 0 },
 299     Package() {0x0003FFFF, 1, LNKC, 0 },
 300     Package() {0x0003FFFF, 2, LNKF, 0 },
 301     Package() {0x0003FFFF, 3, LNKG, 0 },
 302   })
 303
 304   Name(AR01, Package()
 305   {
 306 // PCI slot 1
 307     Package() {0x0000FFFF, 0, 0, 21 },
 308     Package() {0x0000FFFF, 1, 0, 22 },
 309     Package() {0x0000FFFF, 2, 0, 23 },
 310     Package() {0x0000FFFF, 3, 0, 20 },
 311 // PCI slot 2
 312     Package() {0x0001FFFF, 0, 0, 22 },
 313     Package() {0x0001FFFF, 1, 0, 21 },
 314     Package() {0x0001FFFF, 2, 0, 20 },
 315     Package() {0x0001FFFF, 3, 0, 23 },
 316 // PCI slot 3
 317     Package() {0x0002FFFF, 0, 0, 18 },
 318     Package() {0x0002FFFF, 1, 0, 19 },
 319     Package() {0x0002FFFF, 2, 0, 17 },
 320     Package() {0x0002FFFF, 3, 0, 16 },
 321 // PCI slot 4
 322     Package() {0x0003FFFF, 0, 0, 19 },
 323     Package() {0x0003FFFF, 1, 0, 18 },
 324     Package() {0x0003FFFF, 2, 0, 21 },
 325     Package() {0x0003FFFF, 3, 0, 22 },
 326   })
 327 //---------------------------------------------------------------------------
 328 // List of IRQ resource buffers compatible with _PRS return format.
 329 //---------------------------------------------------------------------------
 330 // Naming legend:
 331 // RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.
 332 // Note. PRSy name is generated if IRQ Link name starts from "LNK".
 333 // HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.
 334 //---------------------------------------------------------------------------
 335   Name(PRSA, ResourceTemplate()         // Link name: LNKA
 336   {
 337     IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}
 338   })
 339   Alias(PRSA,PRSB)      // Link name: LNKB
 340   Alias(PRSA,PRSC)      // Link name: LNKC
 341   Alias(PRSA,PRSD)      // Link name: LNKD
 342   Alias(PRSA,PRSE)      // Link name: LNKE
 343   Alias(PRSA,PRSF)      // Link name: LNKF
 344   Alias(PRSA,PRSG)      // Link name: LNKG
 345   Alias(PRSA,PRSH)      // Link name: LNKH
 346 //---------------------------------------------------------------------------
 347 // Begin PCI tree object scope
 348 //---------------------------------------------------------------------------
 349
 350   Device(PCI0)   // PCI Bridge "Host Bridge"
 351   {
 352     Name(_HID, EISAID("PNP0A08"))       // Indicates PCI Express/PCI-X Mode2 host hierarchy
 353     Name(_CID, EISAID("PNP0A03"))       // To support legacy OS that doesn't understand the new HID
 354     Name(_ADR, 0x00000000)
 355     Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
 356     Method(_BBN, 0) { return(BN00()) }  // Bus number, optional for the Root PCI Bus
 357     Name(_UID, 0x0000)  // Unique Bus ID, optional
 358     Name(_DEP, Package(0x1)
 359     {
 360       PEPD
 361     })
 362
 363                             Method(_PRT,0)
 364     {
 365       If(PICM) {Return(AR00)} // APIC mode
 366       Return (PR00) // PIC Mode
 367     } // end _PRT
 368
 369     include("HOST_BUS.ASL")
 370     Device(LPCB)   // LPC Bridge
 371     {
 372       Name(_ADR, 0x001F0000)
 373       include("LpcB.asl")
 374     } // end "LPC Bridge"
 375
 376   } // end PCI0 Bridge "Host Bridge"
 377 } // end _SB scope