Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RhProxy.asl

   1 /** @file
   2   SSDT for RhProxy Driver.
   3
   4 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 DefinitionBlock ("RHPX.aml", "SSDT", 1, "MSFT", "RHPROXY", 1)
  10 {
  11     Scope (\_SB)
  12     {
  13         //
  14         // Test peripheral device node for MinnowBoardMax
  15         //
  16         Device(RHPX)
  17         {
  18             Name(_HID, "MSFT8000")
  19             Name(_CID, "MSFT8000")
  20             Name(_UID, 1)
  21
  22             Name(_CRS, ResourceTemplate()
  23             {
  24                 // Index 0
  25                 SPISerialBus(            // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI
  26                     1,                     // Device selection
  27                     PolarityLow,           // Device selection polarity
  28                     FourWireMode,          // wiremode
  29                     8,                     // databit len
  30                     ControllerInitiated,   // slave mode
  31                     8000000,               // Connection speed
  32                     ClockPolarityLow,      // Clock polarity
  33                     ClockPhaseSecond,      // clock phase
  34                     "\\_SB.SPI1",          // ResourceSource: SPI bus controller name
  35                     0,                     // ResourceSourceIndex
  36                     ResourceConsumer,      // Resource usage
  37                     JSPI,                  // DescriptorName: creates name for offset of resource descriptor
  38                     )                      // Vendor Data
  39
  40                 // Index 1
  41                 I2CSerialBus(            // Pin 13, 15 of JP1, for SIO_I2C5 (signal)
  42                     0xFF,                  // SlaveAddress: bus address (TBD)
  43                     ,                      // SlaveMode: default to ControllerInitiated
  44                     400000,                // ConnectionSpeed: in Hz
  45                     ,                      // Addressing Mode: default to 7 bit
  46                     "\\_SB.I2C6",          // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))
  47                     ,
  48                     ,
  49                     JI2C,                  // Descriptor Name: creates name for offset of resource descriptor
  50                     )                      // VendorData
  51
  52                 // Index 2
  53                 UARTSerialBus(           // Pin 17, 19 of JP1, for SIO_UART2
  54                     115200,                // InitialBaudRate: in bits ber second
  55                     ,                      // BitsPerByte: default to 8 bits
  56                     ,                      // StopBits: Defaults to one bit
  57                     0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled
  58                     ,                      // IsBigEndian: default to LittleEndian
  59                     ,                      // Parity: Defaults to no parity
  60                     ,                      // FlowControl: Defaults to no flow control
  61                     32,                    // ReceiveBufferSize
  62                     32,                    // TransmitBufferSize
  63                     "\\_SB.URT2",          // ResourceSource: UART bus controller name
  64                     ,
  65                     ,
  66                     UAR2,                  // DescriptorName: creates name for offset of resource descriptor
  67                     )
  68
  69                 // Index 3
  70                 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0}  // Pin 21 of JP1 (GPIO_S5[00])
  71                 // Index 4
  72                 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0}
  73
  74                 // Index 5
  75                 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1}  // Pin 23 of JP1 (GPIO_S5[01])
  76                 // Index 6
  77                 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}
  78
  79                 // Index 7
  80                 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2}  // Pin 25 of JP1 (GPIO_S5[02])
  81                 // Index 8
  82                 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2}
  83
  84                 // Index 9
  85                 UARTSerialBus(           // Pin 6, 8, 10, 12 of JP1, for SIO_UART1
  86                     115200,                // InitialBaudRate: in bits ber second
  87                     ,                      // BitsPerByte: default to 8 bits
  88                     ,                      // StopBits: Defaults to one bit
  89                     0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled
  90                     ,                      // IsBigEndian: default to LittleEndian
  91                     ,                      // Parity: Defaults to no parity
  92                     FlowControlHardware,   // FlowControl: Defaults to no flow control
  93                     32,                    // ReceiveBufferSize
  94                     32,                    // TransmitBufferSize
  95                     "\\_SB.URT1",          // ResourceSource: UART bus controller name
  96                     ,
  97                     ,
  98                     UAR1,              // DescriptorName: creates name for offset of resource descriptor
  99                     )
 100
 101                 // Index 10
 102                 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62}  // Pin 14 of JP1 (GPIO_SC[62])
 103                 // Index 11
 104                 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62}
 105
 106                 // Index 12
 107                 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63}  // Pin 16 of JP1 (GPIO_SC[63])
 108                 // Index 13
 109                 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63}
 110
 111                 // Index 14
 112                 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65}  // Pin 18 of JP1 (GPIO_SC[65])
 113                 // Index 15
 114                 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65}
 115
 116                 // Index 16
 117                 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64}  // Pin 20 of JP1 (GPIO_SC[64])
 118                 // Index 17
 119                 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64}
 120
 121                 // Index 18
 122                 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94}  // Pin 22 of JP1 (GPIO_SC[94])
 123                 // Index 19
 124                 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94}
 125
 126                 // Index 20
 127                 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95}  // Pin 24 of JP1 (GPIO_SC[95])
 128                 // Index 21
 129                 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95}
 130
 131                 // Index 22
 132                 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54}  // Pin 26 of JP1 (GPIO_SC[54])
 133                 // Index 23
 134                 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}
 135             })
 136
 137             Name(_DSD, Package()
 138             {
 139                 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
 140                 Package()
 141                 {
 142                     // SPI Mapping
 143                     Package(2) { "bus-SPI-SPI0", Package() { 0 }},
 144
 145                     // TODO: Intel will need to provide the right value for SPI0 properties
 146                     Package(2) { "SPI0-MinClockInHz", 100000 },
 147                     Package(2) { "SPI0-MaxClockInHz", 15000000 },
 148                     // SupportedDataBitLengths takes a list of support data bit length
 149                     // Example : Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8, 7, 16 }},
 150                     Package(2) { "SPI0-SupportedDataBitLengths", Package() { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }},
 151                     // I2C Mapping
 152                     Package(2) { "bus-I2C-I2C5", Package() { 1 }},
 153                     // UART Mapping
 154                     Package(2) { "bus-UART-UART2", Package() { 2 }},
 155                     Package(2) { "bus-UART-UART1", Package() { 9 }},
 156                 }
 157             })
 158         }
 159     }
 160 }