4 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
6 SPDX-License-Identifier: BSD-2-Clause-Patent
15 Interface definition details between ValleyView MRC and platform drivers during PEI phase.
19 #ifndef _VLV_POLICY_PPI_H_
20 #define _VLV_POLICY_PPI_H_
23 // MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}
25 #define VLV_POLICY_PPI_GUID \
27 0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \
31 // Extern the GUID for protocol users.
33 extern EFI_GUID gVlvPolicyPpiGuid
;
36 // PPI revision number
37 // Any backwards compatible changes to this PPI will result in an update in the revision number
38 // Major changes will require publication of a new PPI
40 #define MRC_PLATFORM_POLICY_PPI_REVISION 1
46 #define S3_TIMING_DATA_LEN 9
47 #define S3_READ_TRAINING_DATA_LEN 16
48 #define S3_WRITE_TRAINING_DATA_LEN 12
50 #ifndef S3_RESTORE_DATA_LEN
51 #define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)
52 #endif // S3_RESTORE_DATA_LEN
55 // MRC Platform Data Structure
58 UINT8 SpdAddressTable
[MAX_SOCKETS
];
59 UINT8 TSonDimmSmbusAddress
[MAX_SOCKETS
];
63 UINT32 WdbBaseAddress
; // Write Data Buffer area (WC caching mode)
76 UINT8 IgdDvmt50PreAlloc
;
86 } MEMORY_CONFIGURATION
;
90 // MRC Platform Policiy PPI
92 typedef struct _VLV_POLICY_PPI
{
94 VLV_PLATFORM_DATA PlatformData
;
95 GT_CONFIGURATION GtConfig
;
96 MEMORY_CONFIGURATION MemConfig
;
97 VOID
*S3DataPtr
; // was called MRC_PARAMS_SAVE_RESTORE
98 UINT8 ISPEn
; //ISP (IUNIT) Device Enabled
99 UINT8 ISPPciDevConfig
; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS
104 #endif // _VLV_POLICY_PPI_H_