Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h

   1 /**
   2   Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
   3   SPDX-License-Identifier: BSD-2-Clause-Patent
   4
   5 **/
   6 /*++
   7
   8 Module Name:
   9
  10   PpmPlatformPolicy.h
  11
  12 Abstract:
  13
  14   Interface definition details between PPM and platform drivers during DXE phase.
  15
  16 --*/
  17 #ifndef _PPM_PLATFORM_POLICY_H_
  18 #define _PPM_PLATFORM_POLICY_H_
  19
  20 //
  21 //  PPM policy provided by platform for DXE phase {DDABFEAC-EF63-452c-8F39-ED7FAED8265E}
  22 //
  23 #define PPM_PLATFORM_POLICY_PROTOCOL_GUID \
  24   {0xddabfeac, 0xef63, 0x452c, 0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}
  25
  26 //
  27 // Extern the GUID for protocol users.
  28 //
  29 extern EFI_GUID gPpmPlatformPolicyProtocolGuid;
  30
  31 //
  32 // Forward reference for ANSI C compatibility
  33 //
  34 typedef struct _PPM_PLATFORM_POLICY_PROTOCOL PPM_PLATFORM_POLICY_PROTOCOL;
  35
  36 //
  37 // Protocol revision number
  38 // Any backwards compatible changes to this protocol will result in an update in the revision number
  39 // Major changes will require publication of a new protocol
  40 //
  41 // Revision 1: Original version
  42 // Revision 2: Added T-states field to the PPM_FUNCTION_ENABLES structure, Renamed unused fields - CxPopUpEnable, CxPopDownEnable, FastC4ExitEnable
  43 // Revision 3: Extended VidCpuid to 32 bits for extended CPUID support (Penryn)
  44 // Revision 4: Added support for extended C6 residency enabling
  45 //
  46 #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION     1
  47 #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_2   2
  48 #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_3   3
  49 #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4   4
  50
  51 //
  52 // Define maximum number of custom VID states supported
  53 //
  54 #ifndef MAX_CUSTOM_VID_TABLE_STATES
  55 #define MAX_CUSTOM_VID_TABLE_STATES               6
  56 #endif
  57 //
  58 // Custom VID table
  59 //
  60 typedef struct {
  61   UINT8   VidNumber;
  62   UINT32  VidCpuid;
  63   UINT16  VidMaxRatio;
  64   UINT16  VidMaxVid;
  65   UINT16  StateRatio[MAX_CUSTOM_VID_TABLE_STATES];
  66   UINT16  StateVid[MAX_CUSTOM_VID_TABLE_STATES];
  67 } PPM_CUSTOM_VID_TABLE;
  68
  69 //
  70 // PPM functional enables
  71 //
  72 typedef struct {
  73   UINT8   EnableGv                   :1; // 0: Disabled; 1: Enabled
  74   UINT8   EnableCx                   :1;
  75   UINT8   EnableCxe                  :1;
  76   UINT8   EnableC4                   :1;
  77   UINT8   EnableC6                   :1;
  78   UINT8   EnableC7                   :1;
  79   UINT8   EnableTm                   :1;
  80   UINT8   Reserve00                  :1;
  81   UINT8   Reserve01                  :1;
  82   UINT8   EnableTurboMode            :1;
  83   UINT8   PowerLimit2                :1;
  84   UINT8   EnableProcHot              :1;
  85   UINT8   Reserve02                  :1;
  86   UINT8   EnableCMP                  :1;
  87   UINT8   TStatesEnable              :1;
  88   UINT8   Reserve03                  :1;
  89   UINT8   Reserve04                  ;
  90
  91 } PPM_FUNCTION_ENABLES;
  92
  93
  94 //
  95 // PPM Turbo settings
  96 //
  97 typedef struct _PPM_TURBO_SETTINGS {
  98   UINT16  PowerLimit1;
  99   UINT32  PowerLimit1Time;
 100   UINT16  PowerLimit2;
 101   UINT8   TurboPowerLimitLock;
 102 } PPM_TURBO_SETTINGS;
 103
 104 //
 105 // Platform Policy
 106 //
 107 struct _PPM_PLATFORM_POLICY_PROTOCOL {
 108   UINT8                                 Revision;
 109   PPM_FUNCTION_ENABLES                  FunctionEnables;
 110   PPM_CUSTOM_VID_TABLE                  CustomVidTable;
 111   PPM_TURBO_SETTINGS                    TurboSettings;
 112
 113   UINT8                                 Reserve00;
 114   UINT8                                 Reserve01;
 115   UINT8                                 Reserve02;
 116   UINT8                                 Reserve03;
 117   UINT8                                 Reserve04;
 118   UINT8                                 Reserve05;
 119   UINT8                                 Reserve06;
 120
 121   UINT8                                 S3RestoreMsrSwSmiNumber;
 122   UINT8                                 Reserve07;
 123   UINT32                                Reserve08;
 124   UINT8                                 Reserve09;
 125   //
 126   // Primary and Secondary Plane Current Limits
 127   //
 128   UINT16                                Reserve10;
 129   UINT8                                 Reserve11;
 130 };
 131
 132 #endif