1 /*-----------------------------------------------------------------------------
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5 Intel Silvermont Processor Power Management BIOS Reference Code
7 Copyright (c) 2006 - 2014, Intel Corporation
9 SPDX-License-Identifier: BSD-2-Clause-Patent
14 Revision: Refer to Readme
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21 This Processor Power Management BIOS Source Code is furnished under license
22 and may only be used or copied in accordance with the terms of the license.
23 The information in this document is furnished for informational use only, is
24 subject to change without notice, and should not be construed as a commitment
25 by Intel Corporation. Intel Corporation assumes no responsibility or liability
26 for any errors or inaccuracies that may appear in this document or any
27 software that may be provided in association with this document.
29 Except as permitted by such license, no part of this document may be
30 reproduced, stored in a retrieval system, or transmitted in any form or by
31 any means without the express written consent of Intel Corporation.
33 WARNING: You are authorized and licensed to install and use this BIOS code
34 ONLY on an IST PC. This utility may damage any system that does not
35 meet these requirements.
37 An IST PC is a computer which
38 (1) Is capable of seamlessly and automatically transitioning among
39 multiple performance states (potentially operating at different
40 efficiency ratings) based upon power source changes, END user
41 preference, processor performance demand, and thermal conditions; and
42 (2) Includes an Intel Pentium II processors, Intel Pentium III
43 processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
44 Processor-M, Intel Pentium M Processor, or any other future Intel
45 processors that incorporates the capability to transition between
46 different performance states by altering some, or any combination of,
47 the following processor attributes: core voltage, core frequency, bus
48 frequency, number of processor cores available, or any other attribute
49 that changes the efficiency (instructions/unit time-power) at which the
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56 (1) <TODO> - IF the trap range and port definitions do not match those
57 specified by this reference code, this file must be modified IAW the
58 individual implmentation.
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61 ------------------------------------------------------------------------------*/
73 External(\_PR.CPU1, DeviceObj)
74 External(\_PR.CPU2, DeviceObj)
75 External(\_PR.CPU3, DeviceObj)
76 External(\_PR.CPU0._CST)
83 // Return P0's _CST object.
85 Return(\_PR.CPU0._CST)
94 // Return P0's _CST object.
96 Return(\_PR.CPU0._CST)
105 // Return P0's _CST object.
107 Return(\_PR.CPU0._CST)
110 } // End of Definition Block