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[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / CPU / PowerManagement / AcpiTables / Ssdt / ApTst.asl
1 /*-----------------------------------------------------------------------------
2 -------------------------------------------------------------------------------
3
4
5 Intel Platform Processor Power Management BIOS Reference Code
6
7 Copyright (c) 2007 - 2014, Intel Corporation
8
9 This program and the accompanying materials are licensed and made available under
10 the terms and conditions of the BSD License that accompanies this distribution.
11 The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php.
13
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17
18 Filename: APTST.ASL
19
20 Revision: Refer to Readme
21
22 Date: Refer to Readme
23
24 --------------------------------------------------------------------------------
25 -------------------------------------------------------------------------------
26
27 This Processor Power Management BIOS Source Code is furnished under license
28 and may only be used or copied in accordance with the terms of the license.
29 The information in this document is furnished for informational use only, is
30 subject to change without notice, and should not be construed as a commitment
31 by Intel Corporation. Intel Corporation assumes no responsibility or liability
32 for any errors or inaccuracies that may appear in this document or any
33 software that may be provided in association with this document.
34
35 Except as permitted by such license, no part of this document may be
36 reproduced, stored in a retrieval system, or transmitted in any form or by
37 any means without the express written consent of Intel Corporation.
38
39 WARNING: You are authorized and licensed to install and use this BIOS code
40 ONLY on an IST PC. This utility may damage any system that does not
41 meet these requirements.
42
43 An IST PC is a computer which
44 (1) Is capable of seamlessly and automatically transitioning among
45 multiple performance states (potentially operating at different
46 efficiency ratings) based upon power source changes, END user
47 preference, processor performance demand, and thermal conditions; and
48 (2) Includes an Intel Pentium II processors, Intel Pentium III
49 processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
50 Processor-M, Intel Pentium M Processor, or any other future Intel
51 processors that incorporates the capability to transition between
52 different performance states by altering some, or any combination of,
53 the following processor attributes: core voltage, core frequency, bus
54 frequency, number of processor cores available, or any other attribute
55 that changes the efficiency (instructions/unit time-power) at which the
56 processor operates.
57
58 -------------------------------------------------------------------------------
59 -------------------------------------------------------------------------------
60
61 NOTES:
62 (1) <TODO> - IF the trap range and port definitions do not match those
63 specified by this reference code, this file must be modified IAW the
64 individual implmentation.
65
66 --------------------------------------------------------------------------------
67 ------------------------------------------------------------------------------*/
68
69
70 DefinitionBlock(
71 "APTST.aml",
72 "SSDT",
73 0x01,
74 "PmRef",
75 "ApTst",
76 0x3000
77 )
78 {
79 External(\_PR.CPU1, DeviceObj)
80 External(\_PR.CPU2, DeviceObj)
81 External(\_PR.CPU3, DeviceObj)
82 External(\_PR.CPU0._PTC)
83 External(\_PR.CPU0._TSS)
84 External(PDC0)
85 External(CFGD)
86 External(MPEN)
87
88 Scope(\_PR.CPU1)
89 {
90 Name(_TPC, 0) // All T-States are available
91
92 //
93 // T-State Control/Status interface
94 //
95 Method(_PTC, 0)
96 {
97 Return(\_PR.CPU0._PTC)
98 }
99
100 Method(_TSS, 0)
101 {
102 Return(\_PR.CPU0._TSS)
103 }
104
105 //
106 // T-State Dependency
107 //
108 Method(_TSD, 0)
109 {
110 //
111 // IF four cores are supported/enabled && !(direct access to MSR)
112 // Report 4 processors and SW_ANY as the coordination
113 // IF two cores are supported/enabled && !(direct access to MSR)
114 // Report 2 processors and SW_ANY as the coordination type
115 // ELSE
116 // Report 1 processor and SW_ALL as the coordination type (domain 1)
117 //
118 // CFGD[23] = Four cores enabled
119 // CFGD[24] = Two or more cores enabled
120 // PDCx[2] = OSPM is capable of direct access to On
121 // Demand throttling MSR
122 //
123
124 If(LNot(And(PDC0,4)))
125 {
126 Return(Package(){ // SW_ANY
127 Package(){
128 5, // # entries.
129 0, // Revision.
130 0, // Domain #.
131 0xFD, // Coord Type- SW_ANY
132 MPEN // # processors.
133 }
134 })
135 }
136 Return(Package(){ // SW_ALL
137 Package(){
138 5, // # entries.
139 0, // Revision.
140 1, // Domain #.
141 0xFC, // Coord Type- SW_ALL
142 1 // # processors.
143 }
144 })
145 }
146 } // End of CPU1
147
148 Scope(\_PR.CPU2)
149 {
150 Name(_TPC, 0) // All T-States are available
151
152 //
153 // T-State Control/Status interface
154 //
155 Method(_PTC, 0)
156 {
157 Return(\_PR.CPU0._PTC)
158 }
159
160 Method(_TSS, 0)
161 {
162 Return(\_PR.CPU0._TSS)
163 }
164
165 //
166 // T-State Dependency
167 //
168 Method(_TSD, 0)
169 {
170 //
171 // IF four cores are supported/enabled && !(direct access to MSR)
172 // Report 4 processors and SW_ANY as the coordination
173 // IF two cores are supported/enabled && !(direct access to MSR)
174 // Report 2 processors and SW_ANY as the coordination type
175 // ELSE
176 // Report 1 processor and SW_ALL as the coordination type (domain 1)
177 //
178 // CFGD[23] = Four cores enabled
179 // CFGD[24] = Two or more cores enabled
180 // PDCx[2] = OSPM is capable of direct access to On
181 // Demand throttling MSR
182 //
183
184 If(LNot(And(PDC0,4)))
185 {
186 Return(Package(){ // SW_ANY
187 Package(){
188 5, // # entries.
189 0, // Revision.
190 0, // Domain #.
191 0xFD, // Coord Type- SW_ANY
192 MPEN // # processors.
193 }
194 })
195 }
196 Return(Package(){ // SW_ALL
197 Package(){
198 5, // # entries.
199 0, // Revision.
200 1, // Domain #.
201 0xFC, // Coord Type- SW_ALL
202 1 // # processors.
203 }
204 })
205 }
206 } // End of CPU2
207
208 Scope(\_PR.CPU3)
209 {
210 Name(_TPC, 0) // All T-States are available
211
212 //
213 // T-State Control/Status interface
214 //
215 Method(_PTC, 0)
216 {
217 Return(\_PR.CPU0._PTC)
218 }
219
220 Method(_TSS, 0)
221 {
222 Return(\_PR.CPU0._TSS)
223 }
224
225 //
226 // T-State Dependency
227 //
228 Method(_TSD, 0)
229 {
230 //
231 // IF four cores are supported/enabled && !(direct access to MSR)
232 // Report 4 processors and SW_ANY as the coordination
233 // IF two cores are supported/enabled && !(direct access to MSR)
234 // Report 2 processors and SW_ANY as the coordination type
235 // ELSE
236 // Report 1 processor and SW_ALL as the coordination type (domain 1)
237 //
238 // CFGD[23] = Four cores enabled
239 // CFGD[24] = Two or more cores enabled
240 // PDCx[2] = OSPM is capable of direct access to On
241 // Demand throttling MSR
242 //
243
244 If(LNot(And(PDC0,4)))
245 {
246 Return(Package(){ // SW_ANY
247 Package(){
248 5, // # entries.
249 0, // Revision.
250 0, // Domain #.
251 0xFD, // Coord Type- SW_ANY
252 MPEN // # processors.
253 }
254 })
255 }
256 Return(Package(){ // SW_ALL
257 Package(){
258 5, // # entries.
259 0, // Revision.
260 1, // Domain #.
261 0xFC, // Coord Type- SW_ALL
262 1 // # processors.
263 }
264 })
265 }
266 } // End of CPU3
267 } // End of Definition Block
268
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