Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl

   1 /*-----------------------------------------------------------------------------
   2 -------------------------------------------------------------------------------
   3
   4
   5  Intel Platform Processor Power Management BIOS Reference Code
   6
   7  Copyright (c) 2007  - 2014, Intel Corporation
   8
   9   SPDX-License-Identifier: BSD-2-Clause-Patent
  10
  11
  12  Filename:      APTST.ASL
  13
  14  Revision:      Refer to Readme
  15
  16  Date:          Refer to Readme
  17
  18 --------------------------------------------------------------------------------
  19 -------------------------------------------------------------------------------
  20
  21  This Processor Power Management BIOS Source Code is furnished under license
  22  and may only be used or copied in accordance with the terms of the license.
  23  The information in this document is furnished for informational use only, is
  24  subject to change without notice, and should not be construed as a commitment
  25  by Intel Corporation. Intel Corporation assumes no responsibility or liability
  26  for any errors or inaccuracies that may appear in this document or any
  27  software that may be provided in association with this document.
  28
  29  Except as permitted by such license, no part of this document may be
  30  reproduced, stored in a retrieval system, or transmitted in any form or by
  31  any means without the express written consent of Intel Corporation.
  32
  33  WARNING: You are authorized and licensed to install and use this BIOS code
  34  ONLY on an IST PC. This utility may damage any system that does not
  35  meet these requirements.
  36
  37         An IST PC is a computer which
  38         (1) Is capable of seamlessly and automatically transitioning among
  39         multiple performance states (potentially operating at different
  40         efficiency ratings) based upon power source changes, END user
  41         preference, processor performance demand, and thermal conditions; and
  42         (2) Includes an Intel Pentium II processors, Intel Pentium III
  43         processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  44         Processor-M, Intel Pentium M Processor, or any other future Intel
  45         processors that incorporates the capability to transition between
  46         different performance states by altering some, or any combination of,
  47         the following processor attributes: core voltage, core frequency, bus
  48         frequency, number of processor cores available, or any other attribute
  49         that changes the efficiency (instructions/unit time-power) at which the
  50         processor operates.
  51
  52 -------------------------------------------------------------------------------
  53 -------------------------------------------------------------------------------
  54
  55 NOTES:
  56         (1) <TODO> - IF the trap range and port definitions do not match those
  57         specified by this reference code, this file must be modified IAW the
  58         individual implmentation.
  59
  60 --------------------------------------------------------------------------------
  61 ------------------------------------------------------------------------------*/
  62
  63
  64 DefinitionBlock(
  65         "APTST.aml",
  66         "SSDT",
  67         0x01,
  68         "PmRef",
  69         "ApTst",
  70         0x3000
  71         )
  72 {
  73         External(\_PR.CPU1, DeviceObj)
  74         External(\_PR.CPU2, DeviceObj)
  75         External(\_PR.CPU3, DeviceObj)
  76         External(\_PR.CPU0._PTC)
  77         External(\_PR.CPU0._TSS)
  78         External(PDC0)
  79         External(CFGD)
  80         External(MPEN)
  81
  82         Scope(\_PR.CPU1)
  83         {
  84                 Name(_TPC, 0)   // All T-States are available
  85
  86                 //
  87                 // T-State Control/Status interface
  88                 //
  89                 Method(_PTC, 0)
  90                 {
  91                         Return(\_PR.CPU0._PTC)
  92                 }
  93
  94                 Method(_TSS, 0)
  95                 {
  96                         Return(\_PR.CPU0._TSS)
  97                 }
  98
  99                 //
 100                 // T-State Dependency
 101                 //
 102                 Method(_TSD, 0)
 103                 {
 104                         //
 105                         // IF four cores are supported/enabled && !(direct access to MSR)
 106                         //    Report 4 processors and SW_ANY as the coordination
 107                         // IF two cores are supported/enabled && !(direct access to MSR)
 108                         //    Report 2 processors and SW_ANY as the coordination type
 109                         //  ELSE
 110                         //    Report 1 processor and SW_ALL as the coordination type (domain 1)
 111                         //
 112                         //  CFGD[23] = Four cores enabled
 113                         //  CFGD[24] = Two or more cores enabled
 114                         //  PDCx[2] = OSPM is capable of direct access to On
 115                         //              Demand throttling MSR
 116                         //
 117
 118                 If(LNot(And(PDC0,4)))
 119                 {
 120                                 Return(Package(){       // SW_ANY
 121                                         Package(){
 122                                                 5,                // # entries.
 123                                                 0,                // Revision.
 124                                                 0,                // Domain #.
 125                                                 0xFD,           // Coord Type- SW_ANY
 126                                                 MPEN          // # processors.
 127                                         }
 128                                 })
 129                 }
 130                 Return(Package(){               // SW_ALL
 131                         Package(){
 132                                 5,                        // # entries.
 133                                 0,                        // Revision.
 134                                 1,                        // Domain #.
 135                                 0xFC,                   // Coord Type- SW_ALL
 136                                 1               // # processors.
 137                         }
 138                 })
 139                 }
 140         }  // End of CPU1
 141
 142         Scope(\_PR.CPU2)
 143         {
 144                 Name(_TPC, 0)   // All T-States are available
 145
 146                 //
 147                 // T-State Control/Status interface
 148                 //
 149                 Method(_PTC, 0)
 150                 {
 151                         Return(\_PR.CPU0._PTC)
 152                 }
 153
 154                 Method(_TSS, 0)
 155                 {
 156                         Return(\_PR.CPU0._TSS)
 157                 }
 158
 159                 //
 160                 // T-State Dependency
 161                 //
 162                 Method(_TSD, 0)
 163                 {
 164                         //
 165                         // IF four cores are supported/enabled && !(direct access to MSR)
 166                         //    Report 4 processors and SW_ANY as the coordination
 167                         // IF two cores are supported/enabled && !(direct access to MSR)
 168                         //    Report 2 processors and SW_ANY as the coordination type
 169                         //  ELSE
 170                         //    Report 1 processor and SW_ALL as the coordination type (domain 1)
 171                         //
 172                         //  CFGD[23] = Four cores enabled
 173                         //  CFGD[24] = Two or more cores enabled
 174                         //  PDCx[2] = OSPM is capable of direct access to On
 175                         //              Demand throttling MSR
 176                         //
 177
 178                 If(LNot(And(PDC0,4)))
 179                 {
 180                                 Return(Package(){       // SW_ANY
 181                                         Package(){
 182                                                 5,                // # entries.
 183                                                 0,                // Revision.
 184                                                 0,                // Domain #.
 185                                                 0xFD,           // Coord Type- SW_ANY
 186                                                 MPEN          // # processors.
 187                                         }
 188                                 })
 189                 }
 190                 Return(Package(){               // SW_ALL
 191                         Package(){
 192                                 5,                        // # entries.
 193                                 0,                        // Revision.
 194                                 1,                        // Domain #.
 195                                 0xFC,                   // Coord Type- SW_ALL
 196                                 1                // # processors.
 197                         }
 198                 })
 199                 }
 200         }  // End of CPU2
 201
 202         Scope(\_PR.CPU3)
 203         {
 204                 Name(_TPC, 0)   // All T-States are available
 205
 206                 //
 207                 // T-State Control/Status interface
 208                 //
 209                 Method(_PTC, 0)
 210                 {
 211                         Return(\_PR.CPU0._PTC)
 212                 }
 213
 214                 Method(_TSS, 0)
 215                 {
 216                         Return(\_PR.CPU0._TSS)
 217                 }
 218
 219                 //
 220                 // T-State Dependency
 221                 //
 222                 Method(_TSD, 0)
 223                 {
 224                         //
 225                         // IF four cores are supported/enabled && !(direct access to MSR)
 226                         //    Report 4 processors and SW_ANY as the coordination
 227                         // IF two cores are supported/enabled && !(direct access to MSR)
 228                         //    Report 2 processors and SW_ANY as the coordination type
 229                         //  ELSE
 230                         //    Report 1 processor and SW_ALL as the coordination type (domain 1)
 231                         //
 232                         //  CFGD[23] = Four cores enabled
 233                         //  CFGD[24] = Two or more cores enabled
 234                         //  PDCx[2] = OSPM is capable of direct access to On
 235                         //              Demand throttling MSR
 236                         //
 237
 238                 If(LNot(And(PDC0,4)))
 239                 {
 240                                 Return(Package(){       // SW_ANY
 241                                         Package(){
 242                                                 5,                // # entries.
 243                                                 0,                // Revision.
 244                                                 0,                // Domain #.
 245                                                 0xFD,           // Coord Type- SW_ANY
 246                                                 MPEN          // # processors.
 247                                         }
 248                                 })
 249                 }
 250                 Return(Package(){               // SW_ALL
 251                         Package(){
 252                                 5,                        // # entries.
 253                                 0,                        // Revision.
 254                                 1,                        // Domain #.
 255                                 0xFC,                   // Coord Type- SW_ALL
 256                                 1                // # processors.
 257                         }
 258                 })
 259                 }
 260         }  // End of CPU3
 261 } // End of Definition Block
 262