Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl

   1 /*-----------------------------------------------------------------------------
   2 -------------------------------------------------------------------------------
   3
   4
   5  Intel Silvermont Processor Power Management BIOS Reference Code
   6
   7  Copyright (c) 2006 - 2014, Intel Corporation
   8
   9   SPDX-License-Identifier: BSD-2-Clause-Patent
  10
  11
  12  Filename:    CPU0IST.ASL
  13
  14  Revision:    Refer to Readme
  15
  16  Date:        Refer to Readme
  17
  18 --------------------------------------------------------------------------------
  19 -------------------------------------------------------------------------------
  20
  21  This Processor Power Management BIOS Source Code is furnished under license
  22  and may only be used or copied in accordance with the terms of the license.
  23  The information in this document is furnished for informational use only, is
  24  subject to change without notice, and should not be construed as a commitment
  25  by Intel Corporation. Intel Corporation assumes no responsibility or liability
  26  for any errors or inaccuracies that may appear in this document or any
  27  software that may be provided in association with this document.
  28
  29  Except as permitted by such license, no part of this document may be
  30  reproduced, stored in a retrieval system, or transmitted in any form or by
  31  any means without the express written consent of Intel Corporation.
  32
  33  WARNING: You are authorized and licensed to install and use this BIOS code
  34  ONLY on an IST PC. This utility may damage any system that does not
  35  meet these requirements.
  36
  37     An IST PC is a computer which
  38     (1) Is capable of seamlessly and automatically transitioning among
  39     multiple performance states (potentially operating at different
  40     efficiency ratings) based upon power source changes, END user
  41     preference, processor performance demand, and thermal conditions; and
  42     (2) Includes an Intel Pentium II processors, Intel Pentium III
  43     processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  44     Processor-M, Intel Pentium M Processor, or any other future Intel
  45     processors that incorporates the capability to transition between
  46     different performance states by altering some, or any combination of,
  47     the following processor attributes: core voltage, core frequency, bus
  48     frequency, number of processor cores available, or any other attribute
  49     that changes the efficiency (instructions/unit time-power) at which the
  50     processor operates.
  51
  52 -------------------------------------------------------------------------------
  53 -------------------------------------------------------------------------------
  54
  55 NOTES:
  56     (1) <TODO> - IF the trap range and port definitions do not match those
  57     specified by this reference code, this file must be modified IAW the
  58     individual implmentation.
  59
  60 --------------------------------------------------------------------------------
  61 ------------------------------------------------------------------------------*/
  62
  63
  64 DefinitionBlock (
  65     "CPU0IST.aml",
  66     "SSDT",
  67     0x01,
  68     "PmRef",
  69     "Cpu0Ist",
  70     0x3000
  71     )
  72 {
  73     External (\_PR.CPU0, DeviceObj)
  74     External (PDC0)
  75     External (CFGD)
  76
  77     Scope(\_PR.CPU0)
  78     {
  79         //OperationRegion (DEB0, SystemIO, 0x80, 1)    //DBG
  80         //Field (DEB0, ByteAcc,NoLock,Preserve)        //DBG
  81         //{ DBG8, 8,}                                  //DBG
  82
  83         Name(_PPC, 0)        // Initialize as All States Available.
  84
  85         // NOTE:  For CMP systems; this table is not loaded unless
  86         //      the required driver support is present.
  87         //      So, we do not check for those cases here.
  88         //
  89         //   CFGD[0] = GV3 Capable/Enabled
  90         //   PDCx[0]  = OS Capable of Hardware P-State control
  91         //
  92         Method(_PCT,0)
  93         {
  94             If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))
  95             {
  96                 //Store(0xA0,DBG8) //DBG
  97                 Return(Package()    // Native Mode
  98                 {
  99                     ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
 100                     ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
 101                 })
 102             }
 103             // @NOTE: IO Trap is not supported. Therefore should not expose any IO interface for _PCT
 104             // For all other cases, report control through the
 105             // SMI interface.  (The port used for SMM control is fixed up
 106             // by the initialization code.)
 107             //
 108             Return(Package()        // SMM Mode
 109             {
 110                ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
 111                ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
 112             })
 113         }
 114
 115
 116         // NOTE:  For CMP systems; this table is not loaded if MP
 117         //      driver support is not present or P-State are disabled.
 118         //
 119         Method(_PSS,0)
 120         {
 121             //
 122             // Report NSPP if:
 123             //   (1) GV3 capable (Not checked, see above.)
 124             //   (2) Driver support direct hardware control
 125             //   (3) MP driver support present (Not checked, see above.)
 126             // else;
 127             //   Report SPSS
 128             //
 129             //   PDCx[0]  = OS Capable of Hardware P-State control
 130             //
 131             If(And(PDC0,0x0001)){
 132                 //Store(0xB0,DBG8) //DBG
 133                 Return(NPSS)
 134             }
 135             //Store(0xBF,DBG8) //DBG
 136             // Otherwise, report SMM mode
 137             //
 138             Return(SPSS)
 139
 140         }
 141
 142         Name(SPSS,Package()
 143         {
 144             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 145             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 146             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 147             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 148             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 149             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 150             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 151             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 152             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 153             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 154             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 155             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 156             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 157             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 158             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 159             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
 160         })
 161
 162         Name(NPSS,Package()
 163         {
 164             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 165             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 166             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 167             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 168             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 169             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 170             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 171             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 172             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 173             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 174             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 175             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 176             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 177             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 178             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 179             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
 180         })
 181
 182         // The _PSD object provides information to the OSPM related
 183         // to P-State coordination between processors in a multi-processor
 184         // configurations.
 185         //
 186         Method(_PSD,0)
 187         {
 188             //
 189             // IF CMP is supported/enabled
 190             //   IF quad core processor
 191             //     IF PDC[11]
 192             //         Report 4 processors and HW_ALL as the coordination type
 193             //     ELSE
 194             //         Report 4 processors and SW_ALL as the coordination type
 195             //   ELSE
 196             //     IF PDC[11]
 197             //         Report 2 processors and HW_ALL as the coordination type
 198             //     ELSE
 199             //         Report 2 processors and SW_ALL as the coordination type
 200             // ELSE
 201             //    Report 1 processor and SW_ALL as the coordination type
 202             //    (Domain 0)
 203             //
 204             //   CFGD[24] = Two or more cores enabled
 205             //   CFGD[23] = Four cores enabled
 206             //   PDCx[11] = Hardware coordination with hardware feedback
 207             //
 208
 209             If(And(CFGD,0x1000000))    // CMP Enabled.
 210             {
 211               If(And(CFGD,0x800000))    // 2 or 4 process.
 212                 {
 213                   If(And(PDC0,0x0800))
 214                   {
 215                       Return(Package(){    // HW_ALL
 216                         Package(){
 217                             5,              // # entries.
 218                             0,              // Revision.
 219                             0,              // Domain #.
 220                             0xFE,           // Coord Type- HW_ALL.
 221                             4               // # processors.
 222                         }
 223                       })
 224                   } // If(And(PDC0,0x0800))
 225                    Return(Package(){        // SW_ALL
 226                      Package(){
 227                         5,                  // # entries.
 228                         0,                  // Revision.
 229                         0,                  // Domain #.
 230                         0xFC,               // Coord Type- SW_ALL.
 231                         4                   // # processors.
 232                      }
 233                     })
 234                 } else {
 235                   Return(Package(){        // HW_ALL
 236                       Package(){
 237                           5,                  // # entries.
 238                           0,                  // Revision.
 239                           0,                  // Domain #.
 240                           0xFE,               // Coord Type- HW_ALL.
 241                           2                   // # processors.
 242                       }
 243                   })
 244                 }
 245             }    // If(And(CFGD,0x1000000))    // CMP Enabled.
 246
 247             Return(Package(){              // SW_ALL
 248                 Package(){
 249                     5,                        // # entries.
 250                     0,                        // Revision.
 251                     0,                        // Domain #.
 252                     0xFC,                     // Coord Type- SW_ALL.
 253                     1                         // # processors.
 254                 }
 255             })
 256         } // Method(_PSD,0)
 257     } // Scope(\_PR.CPU0)
 258 } // End of Definition Block
 259
 260