1 /*-----------------------------------------------------------------------------
2 -------------------------------------------------------------------------------
5 Intel Silvermont Processor Power Management BIOS Reference Code
7 Copyright (c) 2006 - 2014, Intel Corporation
9 SPDX-License-Identifier: BSD-2-Clause-Patent
14 Revision: Refer to Readme
18 --------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
21 This Processor Power Management BIOS Source Code is furnished under license
22 and may only be used or copied in accordance with the terms of the license.
23 The information in this document is furnished for informational use only, is
24 subject to change without notice, and should not be construed as a commitment
25 by Intel Corporation. Intel Corporation assumes no responsibility or liability
26 for any errors or inaccuracies that may appear in this document or any
27 software that may be provided in association with this document.
29 Except as permitted by such license, no part of this document may be
30 reproduced, stored in a retrieval system, or transmitted in any form or by
31 any means without the express written consent of Intel Corporation.
33 WARNING: You are authorized and licensed to install and use this BIOS code
34 ONLY on an IST PC. This utility may damage any system that does not
35 meet these requirements.
37 An IST PC is a computer which
38 (1) Is capable of seamlessly and automatically transitioning among
39 multiple performance states (potentially operating at different
40 efficiency ratings) based upon power source changes, END user
41 preference, processor performance demand, and thermal conditions; and
42 (2) Includes an Intel Pentium II processors, Intel Pentium III
43 processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
44 Processor-M, Intel Pentium M Processor, or any other future Intel
45 processors that incorporates the capability to transition between
46 different performance states by altering some, or any combination of,
47 the following processor attributes: core voltage, core frequency, bus
48 frequency, number of processor cores available, or any other attribute
49 that changes the efficiency (instructions/unit time-power) at which the
52 -------------------------------------------------------------------------------
53 -------------------------------------------------------------------------------
56 (1) <TODO> - IF the trap range and port definitions do not match those
57 specified by this reference code, this file must be modified IAW the
58 individual implmentation.
60 --------------------------------------------------------------------------------
61 ------------------------------------------------------------------------------*/
73 External (\_PR.CPU0, DeviceObj)
79 //OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG
80 //Field (DEB0, ByteAcc,NoLock,Preserve) //DBG
83 Name(_PPC, 0) // Initialize as All States Available.
85 // NOTE: For CMP systems; this table is not loaded unless
86 // the required driver support is present.
87 // So, we do not check for those cases here.
89 // CFGD[0] = GV3 Capable/Enabled
90 // PDCx[0] = OS Capable of Hardware P-State control
94 If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))
96 //Store(0xA0,DBG8) //DBG
97 Return(Package() // Native Mode
99 ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
100 ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
103 // @NOTE: IO Trap is not supported. Therefore should not expose any IO interface for _PCT
104 // For all other cases, report control through the
105 // SMI interface. (The port used for SMM control is fixed up
106 // by the initialization code.)
108 Return(Package() // SMM Mode
110 ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
111 ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
116 // NOTE: For CMP systems; this table is not loaded if MP
117 // driver support is not present or P-State are disabled.
123 // (1) GV3 capable (Not checked, see above.)
124 // (2) Driver support direct hardware control
125 // (3) MP driver support present (Not checked, see above.)
129 // PDCx[0] = OS Capable of Hardware P-State control
131 If(And(PDC0,0x0001)){
132 //Store(0xB0,DBG8) //DBG
135 //Store(0xBF,DBG8) //DBG
136 // Otherwise, report SMM mode
144 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
145 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
146 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
147 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
148 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
149 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
150 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
151 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
152 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
153 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
154 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
155 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
156 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
157 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
158 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
159 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
164 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
165 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
166 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
167 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
168 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
169 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
170 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
171 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
172 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
173 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
174 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
175 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
176 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
177 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
178 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
179 Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
182 // The _PSD object provides information to the OSPM related
183 // to P-State coordination between processors in a multi-processor
189 // IF CMP is supported/enabled
190 // IF quad core processor
192 // Report 4 processors and HW_ALL as the coordination type
194 // Report 4 processors and SW_ALL as the coordination type
197 // Report 2 processors and HW_ALL as the coordination type
199 // Report 2 processors and SW_ALL as the coordination type
201 // Report 1 processor and SW_ALL as the coordination type
204 // CFGD[24] = Two or more cores enabled
205 // CFGD[23] = Four cores enabled
206 // PDCx[11] = Hardware coordination with hardware feedback
209 If(And(CFGD,0x1000000)) // CMP Enabled.
211 If(And(CFGD,0x800000)) // 2 or 4 process.
215 Return(Package(){ // HW_ALL
220 0xFE, // Coord Type- HW_ALL.
224 } // If(And(PDC0,0x0800))
225 Return(Package(){ // SW_ALL
230 0xFC, // Coord Type- SW_ALL.
235 Return(Package(){ // HW_ALL
240 0xFE, // Coord Type- HW_ALL.
245 } // If(And(CFGD,0x1000000)) // CMP Enabled.
247 Return(Package(){ // SW_ALL
252 0xFC, // Coord Type- SW_ALL.
257 } // Scope(\_PR.CPU0)
258 } // End of Definition Block