Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl

   1 /*-----------------------------------------------------------------------------
   2 -------------------------------------------------------------------------------
   3
   4
   5  Intel Silvermont Processor Power Management BIOS Reference Code
   6
   7  Copyright (c) 2006 - 2014, Intel Corporation
   8
   9   SPDX-License-Identifier: BSD-2-Clause-Patent
  10
  11
  12  Filename:      CPU0TST.ASL
  13
  14  Revision:      Refer to Readme
  15
  16  Date:          Refer to Readme
  17
  18 --------------------------------------------------------------------------------
  19 -------------------------------------------------------------------------------
  20
  21  This Processor Power Management BIOS Source Code is furnished under license
  22  and may only be used or copied in accordance with the terms of the license.
  23  The information in this document is furnished for informational use only, is
  24  subject to change without notice, and should not be construed as a commitment
  25  by Intel Corporation. Intel Corporation assumes no responsibility or liability
  26  for any errors or inaccuracies that may appear in this document or any
  27  software that may be provided in association with this document.
  28
  29  Except as permitted by such license, no part of this document may be
  30  reproduced, stored in a retrieval system, or transmitted in any form or by
  31  any means without the express written consent of Intel Corporation.
  32
  33  WARNING: You are authorized and licensed to install and use this BIOS code
  34  ONLY on an IST PC. This utility may damage any system that does not
  35  meet these requirements.
  36
  37         An IST PC is a computer which
  38         (1) Is capable of seamlessly and automatically transitioning among
  39         multiple performance states (potentially operating at different
  40         efficiency ratings) based upon power source changes, end user
  41         preference, processor performance demand, and thermal conditions; and
  42         (2) Includes an Intel Pentium II processors, Intel Pentium III
  43         processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  44         Processor-M, Intel Pentium M Processor, or any other future Intel
  45         processors that incorporates the capability to transition between
  46         different performance states by altering some, or any combination of,
  47         the following processor attributes: core voltage, core frequency, bus
  48         frequency, number of processor cores available, or any other attribute
  49         that changes the efficiency (instructions/unit time-power) at which the
  50         processor operates.
  51
  52 -------------------------------------------------------------------------------
  53 -------------------------------------------------------------------------------
  54
  55 NOTES:
  56         (1) <TODO> - IF the trap range and port definitions do not match those
  57         specified by this reference code, this file must be modified IAW the
  58         individual implmentation.
  59
  60 --------------------------------------------------------------------------------
  61 ------------------------------------------------------------------------------*/
  62
  63 DefinitionBlock(
  64         "CPU0TST.aml",
  65         "SSDT",
  66         0x01,
  67         "PmRef",
  68         "Cpu0Tst",
  69         0x3000
  70         )
  71 {
  72         External(\_PR.CPU0, DeviceObj)
  73         External(PDC0)
  74         External(CFGD)
  75         External(_PSS)
  76
  77         Scope(\_PR.CPU0)
  78         {
  79                 Name(_TPC, 0)   // All T-States are available
  80
  81                 //
  82                 // T-State Control/Status interface
  83                 //
  84                 Method(_PTC, 0)
  85                 {
  86                         //
  87                         // IF OSPM is capable of direct access to MSR
  88                         //    Report MSR interface
  89                         // ELSE
  90                         //    Report I/O interface
  91                         //
  92                         //  PDCx[2] = OSPM is capable of direct access to On
  93                         //              Demand throttling MSR
  94                         //
  95                         If(And(PDC0, 0x0004)) {
  96                                 Return(Package() {
  97                                         ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
  98                                         ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
  99                                 })
 100                         }
 101
 102                 }
 103
 104                 // _TSS package for I/O port based T-State control
 105                 // "Power" fields are replaced with real values by the first
 106                 // call of _TSS method.
 107                 //
 108                 Name(TSSI, Package() {
 109                                 Package(){100, 1000, 0, 0x00, 0},
 110                                 Package(){ 88,  875, 0, 0x0F, 0},
 111                                 Package(){ 75,  750, 0, 0x0E, 0},
 112                                 Package(){ 63,  625, 0, 0x0D, 0},
 113                                 Package(){ 50,  500, 0, 0x0C, 0},
 114                                 Package(){ 38,  375, 0, 0x0B, 0},
 115                                 Package(){ 25,  250, 0, 0x0A, 0},
 116                                 Package(){ 13,  125, 0, 0x09, 0}
 117                 })
 118
 119                 // _TSS package for MSR based T-State control
 120                 // "Power" fields are replaced with real values by the first
 121                 // call of _TSS method.
 122                 //
 123                 Name(TSSM, Package() {
 124                                 Package(){100, 1000, 0, 0x00, 0},
 125                                 Package(){ 88,  875, 0, 0x1E, 0},
 126                                 Package(){ 75,  750, 0, 0x1C, 0},
 127                                 Package(){ 63,  625, 0, 0x1A, 0},
 128                                 Package(){ 50,  500, 0, 0x18, 0},
 129                                 Package(){ 38,  375, 0, 0x16, 0},
 130                                 Package(){ 25,  250, 0, 0x14, 0},
 131                                 Package(){ 13,  125, 0, 0x12, 0}
 132                 })
 133
 134                 Name(TSSF, 0)   // Flag for TSSI/TSSM initialization
 135
 136                 Method(_TSS, 0)
 137                 {
 138                         // Update "Power" fields of TSSI/TSSM with the LFM
 139                         // power data IF _PSS is available
 140                         //
 141                         IF (LAnd(LNot(TSSF),CondRefOf(_PSS)))
 142                         {
 143                                 Store(_PSS, Local0)
 144                                 Store(SizeOf(Local0), Local1)   // _PSS size
 145                                 Decrement(Local1)               // Index of LFM
 146                                 Store(DerefOf(Index(DerefOf(Index(Local0,Local1)),1)), Local2)  // LFM Power
 147
 148                                 Store(0, Local3)
 149                                 While(LLess(Local3, SizeOf(TSSI)))
 150                                 {
 151                                         Store(Divide(Multiply(Local2, Subtract(8, Local3)), 8),
 152                                               Local4)           // Power for this TSSI/TSSM entry
 153                                         Store(Local4,Index(DerefOf(Index(TSSI,Local3)),1))
 154                                         Store(Local4,Index(DerefOf(Index(TSSM,Local3)),1))
 155                                         Increment(Local3)
 156                                 }
 157                                 Store(Ones, TSSF)               // TSSI/TSSM are updated
 158                         }
 159                         //
 160                         // IF OSPM is capable of direct access to MSR
 161                         //    Report TSSM
 162                         // ELSE
 163                         //    Report TSSI
 164                         //
 165                         If(And(PDC0, 0x0004))
 166                         {
 167                                 Return(TSSM)
 168                         }
 169                         Return(TSSI)
 170                 }
 171
 172               Method(_TDL, 0)
 173               {
 174                 Store ("Cpu0: _TDL Called", Debug)
 175                 Name ( LFMI, 0)
 176                 Store (SizeOf(TSSM), LFMI)
 177                 Decrement(LFMI)    // Index of LFM entry in TSSM
 178                 Return(LFMI)
 179               }
 180
 181                 //
 182                 // T-State Dependency
 183                 //
 184                 Method(_TSD, 0)
 185                 {
 186                         //
 187       // IF four cores are supported/enabled && !(direct access to MSR)
 188                         //    Report 4 processors and SW_ANY as the coordination type
 189       // ELSE IF two cores are supported/enabled && !(direct access to MSR)
 190                         //    Report 2 processors and SW_ANY as the coordination type
 191                         // ELSE
 192                         //   Report 1 processor and SW_ALL as the coordination type
 193                         //
 194                         //  CFGD[23] = Four cores enabled
 195                         //  CFGD[24] = Two or more cores enabled
 196                         //  PDCx[2] = OSPM is capable of direct access to On
 197                         //              Demand throttling MSR
 198                         //
 199                         If(LAnd(And(CFGD,0x0800000),LNot(And(PDC0,4))))
 200                         {
 201                                 Return(Package(){       // SW_ANY
 202                                         Package(){
 203                                                 5,                // # entries.
 204                                                 0,                // Revision.
 205                                                 0,                // Domain #.
 206                                                 0xFD,           // Coord Type- SW_ANY
 207                                                 4                   // # processors.
 208                                         }
 209                                 })
 210                         }
 211                         If(LAnd(And(CFGD,0x1000000),LNot(And(PDC0,4))))
 212                         {
 213                                 Return(Package(){       // SW_ANY
 214                                         Package(){
 215                                                 5,                // # entries.
 216                                                 0,                // Revision.
 217                                                 0,                // Domain #.
 218                                                 0xFD,           // Coord Type- SW_ANY
 219                                                 2                   // # processors.
 220                                         }
 221                                 })
 222                         }
 223                         Return(Package(){               // SW_ALL
 224                                 Package(){
 225                                         5,                        // # entries.
 226                                         0,                        // Revision.
 227                                         0,                        // Domain #.
 228                                         0xFC,                   // Coord Type- SW_ALL
 229                                         1                           // # processors.
 230                                 }
 231                         })
 232                 }
 233         }
 234 } // End of Definition Block
 235