1 /*-----------------------------------------------------------------------------
4 Intel Silvermont Processor Power Management BIOS Reference Code
6 Copyright (c) 2006 - 2014, Intel Corporation
8 This program and the accompanying materials are licensed and made available under
9 the terms and conditions of the BSD License that accompanies this distribution.
10 The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php.
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 Revision: Refer to Readme
22 -------------------------------------------------------------------------------
24 This Processor Power Management BIOS Source Code is furnished under license
25 and may only be used or copied in accordance with the terms of the license.
26 The information in this document is furnished for informational use only, is
27 subject to change without notice, and should not be construed as a commitment
28 by Intel Corporation. Intel Corporation assumes no responsibility or liability
29 for any errors or inaccuracies that may appear in this document or any
30 software that may be provided in association with this document.
32 Except as permitted by such license, no part of this document may be
33 reproduced, stored in a retrieval system, or transmitted in any form or by
34 any means without the express written consent of Intel Corporation.
36 WARNING: You are authorized and licensed to install and use this BIOS code
37 ONLY on an IST PC. This utility may damage any system that does not
38 meet these requirements.
40 An IST PC is a computer which
41 (1) Is capable of seamlessly and automatically transitioning among
42 multiple performance states (potentially operating at different
43 efficiency ratings) based upon power source changes, END user
44 preference, processor performance demand, and thermal conditions; and
45 (2) Includes an Intel Pentium II processors, Intel Pentium III
46 processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
47 Processor-M, Intel Pentium M Processor, or any other future Intel
48 processors that incorporates the capability to transition between
49 different performance states by altering some, or any combination of,
50 the following processor attributes: core voltage, core frequency, bus
51 frequency, number of processor cores available, or any other attribute
52 that changes the efficiency (instructions/unit time-power) at which the
54 -------------------------------------------------------------------------------
57 (1) <TODO> - Except for the SSDT package, the objects in this ASL code
58 may be moved to the DSDT. It is kept separate in this reference package
59 for ease of distribution only.
60 ------------------------------------------------------------------------------*/
71 External(\_PR.CPU0, DeviceObj)
72 External(\_PR.CPU1, DeviceObj)
73 External(\_PR.CPU2, DeviceObj)
74 External(\_PR.CPU3, DeviceObj)
80 // Package of pointers to SSDT's
82 // First column is SSDT name, used for debug only.
83 // (First column must be EXACTLY eight characters.)
84 // Second column is physical address.
85 // Third column is table length.
87 // IF modifying this file, see warnings listed in ppminit.asm.
91 "CPU0IST ", 0x80000000, 0x80000000,
92 "APIST ", 0x80000000, 0x80000000,
93 "CPU0CST ", 0x80000000, 0x80000000,
94 "APCST ", 0x80000000, 0x80000000
98 // Note: See PpmBiosInit in PPMINIT.ASM for a definition of
99 // the PpmFlags mirrored in CFGD.
101 Name(CFGD, 0x80000000)
103 Name(\PDC0,0x80000000) // CPU0 _PDC Flags.
104 Name(\PDC1,0x80000000) // CPU1 _PDC Flags.
105 Name(\PDC2,0x80000000) // CPU2 _PDC Flags.
106 Name(\PDC3,0x80000000) // CPU3 _PDC Flags.
107 Name(\SDTL,0x00) // Loaded SSDT Flags.
113 // Define handles for opregions (used by load.)
115 Name(HI0,0) // Handle to CPU0IST
116 Name(HC0,0) // Handle to CPU0CST
121 // Check and extract the _PDC information.
123 Store(CPDC(Arg0), Local0)
125 // Save the capability information and load tables as needed.
137 // Check and extract the _OSC information.
139 Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0)
141 // Save the capability information and load tables as needed.
151 // Implement a generic Method to check _PDC information which may be called
152 // by any of the processor scopes. (The use of _PDC is deprecated in ACPI 3.
153 // in favor of _OSC. However, for backwards compatibility, _PDC may be
154 // implemented using _OSC as follows:)
158 CreateDwordField (Arg0, 0, REVS)
159 CreateDwordField (Arg0, 4, SIZE)
162 // Local0 = Number of bytes for Arg0
164 Store (SizeOf (Arg0), Local0)
167 // Local1 = Number of Capabilities bytes in Arg0
169 Store (Subtract (Local0, 8), Local1)
172 // TEMP = Temporary field holding Capability DWORDs
174 CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)
177 // Create the Status (STAT) buffer with the first DWORD = 0
178 // This is required as per ACPI 3.0 Spec which says the
179 // first DWORD is used to return errors defined by _OSC.
181 Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})
184 // Concatenate the _PDC capabilities bytes to the STS0 Buffer
185 // and store them in a local variable for calling OSC
187 Concatenate (STS0, TEMP, Local2)
189 Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2))
193 // Implement a generic Method to check _OSC information which may be called
194 // by any of the processor scopes.
199 // Point to Status DWORD in the Arg3 buffer (STATUS)
201 CreateDWordField(Arg3, 0, STS0)
203 // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)
205 CreateDwordField(Arg3, 4, CAP0)
208 // _OSC needs to validate the UUID and Revision.
210 // IF Unrecognized UUID
211 // Return Unrecognized UUID _OSC Failure
212 // IF Unsupported Revision
213 // Return Unsupported Revision _OSC Failure
215 // STS0[0] = Reserved
216 // STS0[1] = _OSC Failure
217 // STS0[2] = Unrecognized UUID
218 // STS0[3] = Unsupported Revision
219 // STS0[4] = Capabilities masked
221 // Note: The comparison method used is necessary due to
222 // limitations of certain OSes which cannot perform direct
223 // buffer comparisons.
225 // Create a set of "Input" UUID fields.
227 CreateDwordField(Arg0, 0x0, IID0)
228 CreateDwordField(Arg0, 0x4, IID1)
229 CreateDwordField(Arg0, 0x8, IID2)
230 CreateDwordField(Arg0, 0xC, IID3)
232 // Create a set of "Expected" UUID fields.
234 Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953"))
235 CreateDwordField(UID0, 0x0, EID0)
236 CreateDwordField(UID0, 0x4, EID1)
237 CreateDwordField(UID0, 0x8, EID2)
238 CreateDwordField(UID0, 0xC, EID3)
240 // Verify the input UUID matches the expected UUID.
242 If(LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3)))))
245 // Return Unrecognized UUID _OSC Failure
251 If(LNot(LEqual(Arg1,1)))
254 // Return Unsupported Revision _OSC Failure
264 // Get the capability information and load appropriate tables as needed.
269 // Point to Status DWORD in the Arg0 buffer (STATUS)
270 CreateDWordField(Arg0, 0, STS0)
272 // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
273 CreateDwordField(Arg0, 4, CAP0)
276 // If the UUID was unrecognized or the _OSC revision was unsupported,
277 // return without updating capabilities.
279 If(LOr(LEqual(STS0,0x6),LEqual(STS0,0xA)))
285 // Check if this is a query (BIT0 of Status = 1).
286 // If so, mask off the bits we support and return.
290 And(CAP0, 0xBFF, CAP0)
295 // Store result of PDC. (We clear out the MSB, which was just
296 // used as a placeholder for the compiler; and then "OR" the
297 // value in case we get multiple calls, each of which only
298 // reports partial support.)
300 Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0)
303 // Check IF the IST SSDTs should be loaded.
305 // CFGD[0] = GV3 Capable/Enabled
310 // Load the IST SSDTs if:
311 // (1) CMP capable and enabled.
312 // (2) Driver supports P-States in MP configurations
313 // (3) Driver supports direct HW P-State control
314 // (4) SSDT is not already loaded
316 // CFGD[24] = Two or more cores enabled
317 // PDCx[3] = OS supports C1 and P-states in MP systems
318 // PDCx[0] = OS supports direct access of the perf MSR
319 // SDTL[0] = CPU0 IST SSDT Loaded
321 If(LAnd(LAnd(And(CFGD,0x01000000),LEqual(And(PDC0, 0x0009), 0x0009)),LNot(And(SDTL,0x01))))
324 // Flag the IST SSDT as loaded for CPU0
328 OperationRegion(IST0,SystemMemory,DeRefOf(Index(SSDT,1)),DeRefOf(Index(SSDT,2)))
329 Load(IST0, HI0) // Dynamically load the CPU0IST SSDT
334 // Check IF the CST SSDTs should be loaded.
336 // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
341 // Load the CST SSDTs if:
342 // (1) CMP capable/enabled
343 // (2) Driver supports multi-processor configurations
344 // (3) CPU0 CST ISDT is not already loaded
346 // CFGD[24] = Two or more cores enabled
347 // PDCx[3] = OS supports C1 and P-states in MP systems
348 // PDCx[4] = OS supports ind. C2/C3 in MP systems
349 // SDTL[1] = CPU0 CST SSDT Loaded
351 If(LAnd(LAnd(And(CFGD,0x01000000),And(PDC0,0x0018)),LNot(And(SDTL,0x02))))
354 // Flag the CST SSDT as loaded for CPU0
358 OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8)))
359 Load(CST0, HC0) // Dynamically load the CPU0CST SSDT
371 // Define handles for opregions (used by load.)
373 Name(HI1,0) // Handle to APIST
374 Name(HC1,0) // Handle to APCST
379 // Refer to \_PR.CPU0._PDC for description.
381 Store(\_PR.CPU0.CPDC(Arg0), Local0)
389 // Refer to \_PR.CPU0._OSC for description.
391 Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
397 // Get the capability information and load appropriate tables as needed.
402 // Point to Status DWORD in the Arg0 buffer (STATUS)
404 CreateDWordField(Arg0, 0, STS1)
406 // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
408 CreateDwordField(Arg0, 4, CAP1)
410 // If the UUID was unrecognized or the _OSC revision was unsupported,
411 // return without updating capabilities.
413 If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
419 // Check if this is a query (BIT0 of Status = 1).
420 // If so, mask off the bits we support and return.
424 And(CAP1, 0xBFF, CAP1)
429 // Store result of PDC. (We clear out the MSB, which was just
430 // used as a placeholder for the compiler; and then "OR" the
431 // value in case we get multiple calls, each of which only
432 // reports partial support.)
434 Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
437 // Attempt to dynamically load the IST SSDTs if:
438 // (1) Driver supports P-States in MP configurations
439 // (2) Driver supports direct HW P-State control
441 // PDCx[3] = OS supports C1 and P-states in MP systems
442 // PDCx[0] = OS supports direct access of the perf MSR
444 If(LEqual(And(PDC0, 0x0009), 0x0009))
450 // Load the CST SSDTs if:
451 // (1) Driver supports multi-processor configurations
453 // PDCx[3] = OS supports C1 and P-states in MP systems
454 // PDCx[4] = OS supports ind. C2/C3 in MP systems
465 // Dynamically load the CST SSDTs if:
466 // (1) C-States are enabled
467 // (2) SSDT is not already loaded
469 // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
470 // SDTL[5] = AP CST SSDT Loaded
474 If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
477 // Flag the CST SSDT as loaded for the AP's
481 // Dynamically load the APCST SSDT
483 OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
489 // Dynamically load the IST SSDTs if:
490 // (1) If GV3 capable and enabled
491 // (2) SSDT is not already loaded
493 // CFGD[0] = GV3 Capable/Enabled
494 // SDTL[4] = AP IST SSDT Loaded
498 If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
501 // Flag the IST SSDT as loaded for CPU0
505 OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
506 Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
514 // Define handles for opregions (used by load.)
516 Name(HI1,0) // Handle to APIST
517 Name(HC1,0) // Handle to APCST
522 // Refer to \_PR.CPU0._PDC for description.
524 Store(\_PR.CPU0.CPDC(Arg0), Local0)
532 // Refer to \_PR.CPU0._OSC for description.
534 Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
540 // Get the capability information and load appropriate tables as needed.
545 // Point to Status DWORD in the Arg0 buffer (STATUS)
547 CreateDWordField(Arg0, 0, STS1)
549 // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
551 CreateDwordField(Arg0, 4, CAP1)
553 // If the UUID was unrecognized or the _OSC revision was unsupported,
554 // return without updating capabilities.
556 If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
562 // Check if this is a query (BIT0 of Status = 1).
563 // If so, mask off the bits we support and return.
567 And(CAP1, 0xBFF, CAP1)
572 // Store result of PDC. (We clear out the MSB, which was just
573 // used as a placeholder for the compiler; and then "OR" the
574 // value in case we get multiple calls, each of which only
575 // reports partial support.)
577 Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
580 // Attempt to dynamically load the IST SSDTs if:
581 // (1) Driver supports P-States in MP configurations
582 // (2) Driver supports direct HW P-State control
584 // PDCx[3] = OS supports C1 and P-states in MP systems
585 // PDCx[0] = OS supports direct access of the perf MSR
587 If(LEqual(And(PDC0, 0x0009), 0x0009))
593 // Load the CST SSDTs if:
594 // (1) Driver supports multi-processor configurations
596 // PDCx[3] = OS supports C1 and P-states in MP systems
597 // PDCx[4] = OS supports ind. C2/C3 in MP systems
608 // Dynamically load the CST SSDTs if:
609 // (1) C-States are enabled
610 // (2) SSDT is not already loaded
612 // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
613 // SDTL[5] = AP CST SSDT Loaded
617 If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
620 // Flag the CST SSDT as loaded for the AP's
624 // Dynamically load the APCST SSDT
626 OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
632 // Dynamically load the IST SSDTs if:
633 // (1) If GV3 capable and enabled
634 // (2) SSDT is not already loaded
636 // CFGD[0] = GV3 Capable/Enabled
637 // SDTL[4] = AP IST SSDT Loaded
641 If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
644 // Flag the IST SSDT as loaded for CPU0
648 OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
649 Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
657 // Define handles for opregions (used by load.)
659 Name(HI1,0) // Handle to APIST
660 Name(HC1,0) // Handle to APCST
665 // Refer to \_PR.CPU0._PDC for description.
667 Store(\_PR.CPU0.CPDC(Arg0), Local0)
675 // Refer to \_PR.CPU0._OSC for description.
677 Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
683 // Get the capability information and load appropriate tables as needed.
688 // Point to Status DWORD in the Arg0 buffer (STATUS)
690 CreateDWordField(Arg0, 0, STS1)
692 // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
694 CreateDwordField(Arg0, 4, CAP1)
696 // If the UUID was unrecognized or the _OSC revision was unsupported,
697 // return without updating capabilities.
699 If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
705 // Check if this is a query (BIT0 of Status = 1).
706 // If so, mask off the bits we support and return.
710 And(CAP1, 0xBFF, CAP1)
715 // Store result of PDC. (We clear out the MSB, which was just
716 // used as a placeholder for the compiler; and then "OR" the
717 // value in case we get multiple calls, each of which only
718 // reports partial support.)
720 Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
723 // Attempt to dynamically load the IST SSDTs if:
724 // (1) Driver supports P-States in MP configurations
725 // (2) Driver supports direct HW P-State control
727 // PDCx[3] = OS supports C1 and P-states in MP systems
728 // PDCx[0] = OS supports direct access of the perf MSR
730 If(LEqual(And(PDC0, 0x0009), 0x0009))
736 // Load the CST SSDTs if:
737 // (1) Driver supports multi-processor configurations
739 // PDCx[3] = OS supports C1 and P-states in MP systems
740 // PDCx[4] = OS supports ind. C2/C3 in MP systems
751 // Dynamically load the CST SSDTs if:
752 // (1) C-States are enabled
753 // (2) SSDT is not already loaded
755 // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
756 // SDTL[5] = AP CST SSDT Loaded
760 If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
763 // Flag the CST SSDT as loaded for the AP's
767 // Dynamically load the APCST SSDT
769 OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
775 // Dynamically load the IST SSDTs if:
776 // (1) If GV3 capable and enabled
777 // (2) SSDT is not already loaded
779 // CFGD[0] = GV3 Capable/Enabled
780 // SDTL[4] = AP IST SSDT Loaded
784 If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
787 // Flag the IST SSDT as loaded for CPU0
791 OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
792 Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
796 } // End of Definition Block