1 /*-----------------------------------------------------------------------------
4 Intel Silvermont Processor Power Management BIOS Reference Code
6 Copyright (c) 2006 - 2014, Intel Corporation
8 SPDX-License-Identifier: BSD-2-Clause-Patent
13 Revision: Refer to Readme
16 -------------------------------------------------------------------------------
18 This Processor Power Management BIOS Source Code is furnished under license
19 and may only be used or copied in accordance with the terms of the license.
20 The information in this document is furnished for informational use only, is
21 subject to change without notice, and should not be construed as a commitment
22 by Intel Corporation. Intel Corporation assumes no responsibility or liability
23 for any errors or inaccuracies that may appear in this document or any
24 software that may be provided in association with this document.
26 Except as permitted by such license, no part of this document may be
27 reproduced, stored in a retrieval system, or transmitted in any form or by
28 any means without the express written consent of Intel Corporation.
30 WARNING: You are authorized and licensed to install and use this BIOS code
31 ONLY on an IST PC. This utility may damage any system that does not
32 meet these requirements.
34 An IST PC is a computer which
35 (1) Is capable of seamlessly and automatically transitioning among
36 multiple performance states (potentially operating at different
37 efficiency ratings) based upon power source changes, END user
38 preference, processor performance demand, and thermal conditions; and
39 (2) Includes an Intel Pentium II processors, Intel Pentium III
40 processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
41 Processor-M, Intel Pentium M Processor, or any other future Intel
42 processors that incorporates the capability to transition between
43 different performance states by altering some, or any combination of,
44 the following processor attributes: core voltage, core frequency, bus
45 frequency, number of processor cores available, or any other attribute
46 that changes the efficiency (instructions/unit time-power) at which the
48 -------------------------------------------------------------------------------
51 (1) <TODO> - Except for the SSDT package, the objects in this ASL code
52 may be moved to the DSDT. It is kept separate in this reference package
53 for ease of distribution only.
54 ------------------------------------------------------------------------------*/
65 External(\_PR.CPU0, DeviceObj)
66 External(\_PR.CPU1, DeviceObj)
67 External(\_PR.CPU2, DeviceObj)
68 External(\_PR.CPU3, DeviceObj)
74 // Package of pointers to SSDT's
76 // First column is SSDT name, used for debug only.
77 // (First column must be EXACTLY eight characters.)
78 // Second column is physical address.
79 // Third column is table length.
81 // IF modifying this file, see warnings listed in ppminit.asm.
85 "CPU0IST ", 0x80000000, 0x80000000,
86 "APIST ", 0x80000000, 0x80000000,
87 "CPU0CST ", 0x80000000, 0x80000000,
88 "APCST ", 0x80000000, 0x80000000
92 // Note: See PpmBiosInit in PPMINIT.ASM for a definition of
93 // the PpmFlags mirrored in CFGD.
95 Name(CFGD, 0x80000000)
97 Name(\PDC0,0x80000000) // CPU0 _PDC Flags.
98 Name(\PDC1,0x80000000) // CPU1 _PDC Flags.
99 Name(\PDC2,0x80000000) // CPU2 _PDC Flags.
100 Name(\PDC3,0x80000000) // CPU3 _PDC Flags.
101 Name(\SDTL,0x00) // Loaded SSDT Flags.
107 // Define handles for opregions (used by load.)
109 Name(HI0,0) // Handle to CPU0IST
110 Name(HC0,0) // Handle to CPU0CST
115 // Check and extract the _PDC information.
117 Store(CPDC(Arg0), Local0)
119 // Save the capability information and load tables as needed.
131 // Check and extract the _OSC information.
133 Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0)
135 // Save the capability information and load tables as needed.
145 // Implement a generic Method to check _PDC information which may be called
146 // by any of the processor scopes. (The use of _PDC is deprecated in ACPI 3.
147 // in favor of _OSC. However, for backwards compatibility, _PDC may be
148 // implemented using _OSC as follows:)
152 CreateDwordField (Arg0, 0, REVS)
153 CreateDwordField (Arg0, 4, SIZE)
156 // Local0 = Number of bytes for Arg0
158 Store (SizeOf (Arg0), Local0)
161 // Local1 = Number of Capabilities bytes in Arg0
163 Store (Subtract (Local0, 8), Local1)
166 // TEMP = Temporary field holding Capability DWORDs
168 CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)
171 // Create the Status (STAT) buffer with the first DWORD = 0
172 // This is required as per ACPI 3.0 Spec which says the
173 // first DWORD is used to return errors defined by _OSC.
175 Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})
178 // Concatenate the _PDC capabilities bytes to the STS0 Buffer
179 // and store them in a local variable for calling OSC
181 Concatenate (STS0, TEMP, Local2)
183 Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2))
187 // Implement a generic Method to check _OSC information which may be called
188 // by any of the processor scopes.
193 // Point to Status DWORD in the Arg3 buffer (STATUS)
195 CreateDWordField(Arg3, 0, STS0)
197 // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)
199 CreateDwordField(Arg3, 4, CAP0)
202 // _OSC needs to validate the UUID and Revision.
204 // IF Unrecognized UUID
205 // Return Unrecognized UUID _OSC Failure
206 // IF Unsupported Revision
207 // Return Unsupported Revision _OSC Failure
209 // STS0[0] = Reserved
210 // STS0[1] = _OSC Failure
211 // STS0[2] = Unrecognized UUID
212 // STS0[3] = Unsupported Revision
213 // STS0[4] = Capabilities masked
215 // Note: The comparison method used is necessary due to
216 // limitations of certain OSes which cannot perform direct
217 // buffer comparisons.
219 // Create a set of "Input" UUID fields.
221 CreateDwordField(Arg0, 0x0, IID0)
222 CreateDwordField(Arg0, 0x4, IID1)
223 CreateDwordField(Arg0, 0x8, IID2)
224 CreateDwordField(Arg0, 0xC, IID3)
226 // Create a set of "Expected" UUID fields.
228 Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953"))
229 CreateDwordField(UID0, 0x0, EID0)
230 CreateDwordField(UID0, 0x4, EID1)
231 CreateDwordField(UID0, 0x8, EID2)
232 CreateDwordField(UID0, 0xC, EID3)
234 // Verify the input UUID matches the expected UUID.
236 If(LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3)))))
239 // Return Unrecognized UUID _OSC Failure
245 If(LNot(LEqual(Arg1,1)))
248 // Return Unsupported Revision _OSC Failure
258 // Get the capability information and load appropriate tables as needed.
263 // Point to Status DWORD in the Arg0 buffer (STATUS)
264 CreateDWordField(Arg0, 0, STS0)
266 // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
267 CreateDwordField(Arg0, 4, CAP0)
270 // If the UUID was unrecognized or the _OSC revision was unsupported,
271 // return without updating capabilities.
273 If(LOr(LEqual(STS0,0x6),LEqual(STS0,0xA)))
279 // Check if this is a query (BIT0 of Status = 1).
280 // If so, mask off the bits we support and return.
284 And(CAP0, 0xBFF, CAP0)
289 // Store result of PDC. (We clear out the MSB, which was just
290 // used as a placeholder for the compiler; and then "OR" the
291 // value in case we get multiple calls, each of which only
292 // reports partial support.)
294 Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0)
297 // Check IF the IST SSDTs should be loaded.
299 // CFGD[0] = GV3 Capable/Enabled
304 // Load the IST SSDTs if:
305 // (1) CMP capable and enabled.
306 // (2) Driver supports P-States in MP configurations
307 // (3) Driver supports direct HW P-State control
308 // (4) SSDT is not already loaded
310 // CFGD[24] = Two or more cores enabled
311 // PDCx[3] = OS supports C1 and P-states in MP systems
312 // PDCx[0] = OS supports direct access of the perf MSR
313 // SDTL[0] = CPU0 IST SSDT Loaded
315 If(LAnd(LAnd(And(CFGD,0x01000000),LEqual(And(PDC0, 0x0009), 0x0009)),LNot(And(SDTL,0x01))))
318 // Flag the IST SSDT as loaded for CPU0
322 OperationRegion(IST0,SystemMemory,DeRefOf(Index(SSDT,1)),DeRefOf(Index(SSDT,2)))
323 Load(IST0, HI0) // Dynamically load the CPU0IST SSDT
328 // Check IF the CST SSDTs should be loaded.
330 // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
335 // Load the CST SSDTs if:
336 // (1) CMP capable/enabled
337 // (2) Driver supports multi-processor configurations
338 // (3) CPU0 CST ISDT is not already loaded
340 // CFGD[24] = Two or more cores enabled
341 // PDCx[3] = OS supports C1 and P-states in MP systems
342 // PDCx[4] = OS supports ind. C2/C3 in MP systems
343 // SDTL[1] = CPU0 CST SSDT Loaded
345 If(LAnd(LAnd(And(CFGD,0x01000000),And(PDC0,0x0018)),LNot(And(SDTL,0x02))))
348 // Flag the CST SSDT as loaded for CPU0
352 OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8)))
353 Load(CST0, HC0) // Dynamically load the CPU0CST SSDT
365 // Define handles for opregions (used by load.)
367 Name(HI1,0) // Handle to APIST
368 Name(HC1,0) // Handle to APCST
373 // Refer to \_PR.CPU0._PDC for description.
375 Store(\_PR.CPU0.CPDC(Arg0), Local0)
383 // Refer to \_PR.CPU0._OSC for description.
385 Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
391 // Get the capability information and load appropriate tables as needed.
396 // Point to Status DWORD in the Arg0 buffer (STATUS)
398 CreateDWordField(Arg0, 0, STS1)
400 // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
402 CreateDwordField(Arg0, 4, CAP1)
404 // If the UUID was unrecognized or the _OSC revision was unsupported,
405 // return without updating capabilities.
407 If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
413 // Check if this is a query (BIT0 of Status = 1).
414 // If so, mask off the bits we support and return.
418 And(CAP1, 0xBFF, CAP1)
423 // Store result of PDC. (We clear out the MSB, which was just
424 // used as a placeholder for the compiler; and then "OR" the
425 // value in case we get multiple calls, each of which only
426 // reports partial support.)
428 Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
431 // Attempt to dynamically load the IST SSDTs if:
432 // (1) Driver supports P-States in MP configurations
433 // (2) Driver supports direct HW P-State control
435 // PDCx[3] = OS supports C1 and P-states in MP systems
436 // PDCx[0] = OS supports direct access of the perf MSR
438 If(LEqual(And(PDC0, 0x0009), 0x0009))
444 // Load the CST SSDTs if:
445 // (1) Driver supports multi-processor configurations
447 // PDCx[3] = OS supports C1 and P-states in MP systems
448 // PDCx[4] = OS supports ind. C2/C3 in MP systems
459 // Dynamically load the CST SSDTs if:
460 // (1) C-States are enabled
461 // (2) SSDT is not already loaded
463 // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
464 // SDTL[5] = AP CST SSDT Loaded
468 If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
471 // Flag the CST SSDT as loaded for the AP's
475 // Dynamically load the APCST SSDT
477 OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
483 // Dynamically load the IST SSDTs if:
484 // (1) If GV3 capable and enabled
485 // (2) SSDT is not already loaded
487 // CFGD[0] = GV3 Capable/Enabled
488 // SDTL[4] = AP IST SSDT Loaded
492 If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
495 // Flag the IST SSDT as loaded for CPU0
499 OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
500 Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
508 // Define handles for opregions (used by load.)
510 Name(HI1,0) // Handle to APIST
511 Name(HC1,0) // Handle to APCST
516 // Refer to \_PR.CPU0._PDC for description.
518 Store(\_PR.CPU0.CPDC(Arg0), Local0)
526 // Refer to \_PR.CPU0._OSC for description.
528 Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
534 // Get the capability information and load appropriate tables as needed.
539 // Point to Status DWORD in the Arg0 buffer (STATUS)
541 CreateDWordField(Arg0, 0, STS1)
543 // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
545 CreateDwordField(Arg0, 4, CAP1)
547 // If the UUID was unrecognized or the _OSC revision was unsupported,
548 // return without updating capabilities.
550 If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
556 // Check if this is a query (BIT0 of Status = 1).
557 // If so, mask off the bits we support and return.
561 And(CAP1, 0xBFF, CAP1)
566 // Store result of PDC. (We clear out the MSB, which was just
567 // used as a placeholder for the compiler; and then "OR" the
568 // value in case we get multiple calls, each of which only
569 // reports partial support.)
571 Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
574 // Attempt to dynamically load the IST SSDTs if:
575 // (1) Driver supports P-States in MP configurations
576 // (2) Driver supports direct HW P-State control
578 // PDCx[3] = OS supports C1 and P-states in MP systems
579 // PDCx[0] = OS supports direct access of the perf MSR
581 If(LEqual(And(PDC0, 0x0009), 0x0009))
587 // Load the CST SSDTs if:
588 // (1) Driver supports multi-processor configurations
590 // PDCx[3] = OS supports C1 and P-states in MP systems
591 // PDCx[4] = OS supports ind. C2/C3 in MP systems
602 // Dynamically load the CST SSDTs if:
603 // (1) C-States are enabled
604 // (2) SSDT is not already loaded
606 // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
607 // SDTL[5] = AP CST SSDT Loaded
611 If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
614 // Flag the CST SSDT as loaded for the AP's
618 // Dynamically load the APCST SSDT
620 OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
626 // Dynamically load the IST SSDTs if:
627 // (1) If GV3 capable and enabled
628 // (2) SSDT is not already loaded
630 // CFGD[0] = GV3 Capable/Enabled
631 // SDTL[4] = AP IST SSDT Loaded
635 If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
638 // Flag the IST SSDT as loaded for CPU0
642 OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
643 Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
651 // Define handles for opregions (used by load.)
653 Name(HI1,0) // Handle to APIST
654 Name(HC1,0) // Handle to APCST
659 // Refer to \_PR.CPU0._PDC for description.
661 Store(\_PR.CPU0.CPDC(Arg0), Local0)
669 // Refer to \_PR.CPU0._OSC for description.
671 Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
677 // Get the capability information and load appropriate tables as needed.
682 // Point to Status DWORD in the Arg0 buffer (STATUS)
684 CreateDWordField(Arg0, 0, STS1)
686 // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
688 CreateDwordField(Arg0, 4, CAP1)
690 // If the UUID was unrecognized or the _OSC revision was unsupported,
691 // return without updating capabilities.
693 If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
699 // Check if this is a query (BIT0 of Status = 1).
700 // If so, mask off the bits we support and return.
704 And(CAP1, 0xBFF, CAP1)
709 // Store result of PDC. (We clear out the MSB, which was just
710 // used as a placeholder for the compiler; and then "OR" the
711 // value in case we get multiple calls, each of which only
712 // reports partial support.)
714 Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
717 // Attempt to dynamically load the IST SSDTs if:
718 // (1) Driver supports P-States in MP configurations
719 // (2) Driver supports direct HW P-State control
721 // PDCx[3] = OS supports C1 and P-states in MP systems
722 // PDCx[0] = OS supports direct access of the perf MSR
724 If(LEqual(And(PDC0, 0x0009), 0x0009))
730 // Load the CST SSDTs if:
731 // (1) Driver supports multi-processor configurations
733 // PDCx[3] = OS supports C1 and P-states in MP systems
734 // PDCx[4] = OS supports ind. C2/C3 in MP systems
745 // Dynamically load the CST SSDTs if:
746 // (1) C-States are enabled
747 // (2) SSDT is not already loaded
749 // CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
750 // SDTL[5] = AP CST SSDT Loaded
754 If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
757 // Flag the CST SSDT as loaded for the AP's
761 // Dynamically load the APCST SSDT
763 OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
769 // Dynamically load the IST SSDTs if:
770 // (1) If GV3 capable and enabled
771 // (2) SSDT is not already loaded
773 // CFGD[0] = GV3 Capable/Enabled
774 // SDTL[4] = AP IST SSDT Loaded
778 If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
781 // Flag the IST SSDT as loaded for CPU0
785 OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
786 Load(IST1, HI1) // Dynamically load the CPU1IST SSDT
790 } // End of Definition Block