Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h

   1 /*++
   2
   3 Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9 Module Name:
  10
  11   PlatformMemoryRange.h
  12
  13 Abstract:
  14
  15   Platform Memory Range PPI as defined in EFI 2.0
  16
  17   PPI for reserving special purpose memory ranges.
  18
  19 --*/
  20 //
  21 //
  22 #ifndef _PEI_PLATFORM_MEMORY_RANGE_H_
  23 #define _PEI_PLATFORM_MEMORY_RANGE_H_
  24
  25 #define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \
  26   { \
  27     0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \
  28   }
  29
  30 typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI  PEI_PLATFORM_MEMORY_RANGE_PPI ;
  31
  32 #define PEI_MEMORY_RANGE_OPTION_ROM UINT32
  33
  34 #define PEI_MR_OPTION_ROM_ALL       0xFFFFFFFF
  35 #define PEI_MR_OPTION_ROM_NONE      0x00000000
  36 #define PEI_MR_OPTION_ROM_C0000_16K 0x00000001
  37 #define PEI_MR_OPTION_ROM_C4000_16K 0x00000002
  38 #define PEI_MR_OPTION_ROM_C8000_16K 0x00000004
  39 #define PEI_MR_OPTION_ROM_CC000_16K 0x00000008
  40 #define PEI_MR_OPTION_ROM_D0000_16K 0x00000010
  41 #define PEI_MR_OPTION_ROM_D4000_16K 0x00000020
  42 #define PEI_MR_OPTION_ROM_D8000_16K 0x00000040
  43 #define PEI_MR_OPTION_ROM_DC000_16K 0x00000080
  44 #define PEI_MR_OPTION_ROM_E0000_16K 0x00000100
  45 #define PEI_MR_OPTION_ROM_E4000_16K 0x00000200
  46 #define PEI_MR_OPTION_ROM_E8000_16K 0x00000400
  47 #define PEI_MR_OPTION_ROM_EC000_16K 0x00000800
  48 #define PEI_MR_OPTION_ROM_F0000_16K 0x00001000
  49 #define PEI_MR_OPTION_ROM_F4000_16K 0x00002000
  50 #define PEI_MR_OPTION_ROM_F8000_16K 0x00004000
  51 #define PEI_MR_OPTION_ROM_FC000_16K 0x00008000
  52
  53 //
  54 // SMRAM Memory Range
  55 //
  56 #define PEI_MEMORY_RANGE_SMRAM      UINT32
  57 #define PEI_MR_SMRAM_ALL            0xFFFFFFFF
  58 #define PEI_MR_SMRAM_NONE           0x00000000
  59 #define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
  60 #define PEI_MR_SMRAM_SEGTYPE_MASK   0x00FF0000
  61 #define PEI_MR_SMRAM_ABSEG_MASK     0x00010000
  62 #define PEI_MR_SMRAM_HSEG_MASK      0x00020000
  63 #define PEI_MR_SMRAM_TSEG_MASK      0x00040000
  64 //
  65 // If adding additional entries, SMRAM Size
  66 // is a multiple of 128KB.
  67 //
  68 #define PEI_MR_SMRAM_SIZE_MASK          0x0000FFFF
  69 #define PEI_MR_SMRAM_SIZE_128K_MASK     0x00000001
  70 #define PEI_MR_SMRAM_SIZE_256K_MASK     0x00000002
  71 #define PEI_MR_SMRAM_SIZE_512K_MASK     0x00000004
  72 #define PEI_MR_SMRAM_SIZE_1024K_MASK    0x00000008
  73 #define PEI_MR_SMRAM_SIZE_2048K_MASK    0x00000010
  74 #define PEI_MR_SMRAM_SIZE_4096K_MASK    0x00000020
  75 #define PEI_MR_SMRAM_SIZE_8192K_MASK    0x00000040
  76
  77 #define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001
  78 #define PEI_MR_SMRAM_HSEG_128K_CACHE    0x80020001
  79 #define PEI_MR_SMRAM_HSEG_128K_NOCACHE  0x00020001
  80 #define PEI_MR_SMRAM_TSEG_128K_CACHE    0x80040001
  81 #define PEI_MR_SMRAM_TSEG_128K_NOCACHE  0x00040001
  82 #define PEI_MR_SMRAM_TSEG_256K_CACHE    0x80040002
  83 #define PEI_MR_SMRAM_TSEG_256K_NOCACHE  0x00040002
  84 #define PEI_MR_SMRAM_TSEG_512K_CACHE    0x80040004
  85 #define PEI_MR_SMRAM_TSEG_512K_NOCACHE  0x00040004
  86 #define PEI_MR_SMRAM_TSEG_1024K_CACHE   0x80040008
  87 #define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008
  88
  89 //
  90 // Graphics Memory Range
  91 //
  92 #define PEI_MEMORY_RANGE_GRAPHICS_MEMORY  UINT32
  93 #define PEI_MR_GRAPHICS_MEMORY_ALL        0xFFFFFFFF
  94 #define PEI_MR_GRAPHICS_MEMORY_NONE       0x00000000
  95 #define PEI_MR_GRAPHICS_MEMORY_CACHEABLE  0x80000000
  96 //
  97 // If adding additional entries, Graphics Memory Size
  98 // is a multiple of 512KB.
  99 //
 100 #define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK    0x0000FFFF
 101 #define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001
 102 #define PEI_MR_GRAPHICS_MEMORY_512K_CACHE   0x80000001
 103 #define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE   0x00000002
 104 #define PEI_MR_GRAPHICS_MEMORY_1M_CACHE     0x80000002
 105 #define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE   0x00000008
 106 #define PEI_MR_GRAPHICS_MEMORY_4M_CACHE     0x80000008
 107 #define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE   0x00000010
 108 #define PEI_MR_GRAPHICS_MEMORY_8M_CACHE     0x80000010
 109 #define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE  0x00000020
 110 #define PEI_MR_GRAPHICS_MEMORY_16M_CACHE    0x80000020
 111 #define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE  0x00000040
 112 #define PEI_MR_GRAPHICS_MEMORY_32M_CACHE    0x80000040
 113 #define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE  0x00000060
 114 #define PEI_MR_GRAPHICS_MEMORY_48M_CACHE    0x80000060
 115 #define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE  0x00000080
 116 #define PEI_MR_GRAPHICS_MEMORY_64M_CACHE    0x80000080
 117 #define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100
 118 #define PEI_MR_GRAPHICS_MEMORY_128M_CACHE   0x80000100
 119 #define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200
 120 #define PEI_MR_GRAPHICS_MEMORY_256M_CACHE   0x80000200
 121 //
 122 // Pci Memory Hole
 123 //
 124 #define PEI_MEMORY_RANGE_PCI_MEMORY       UINT32
 125 #define PEI_MR_PCI_MEMORY_SIZE_512M_MASK  0x00000001
 126
 127 typedef
 128 EFI_STATUS
 129 (EFIAPI *PEI_CHOOSE_RANGES) (
 130   IN      EFI_PEI_SERVICES                      **PeiServices,
 131   IN PEI_PLATFORM_MEMORY_RANGE_PPI              * This,
 132   IN OUT  PEI_MEMORY_RANGE_OPTION_ROM           * OptionRomMask,
 133   IN OUT  PEI_MEMORY_RANGE_SMRAM                * SmramMask,
 134   IN OUT  PEI_MEMORY_RANGE_GRAPHICS_MEMORY      * GraphicsMemoryMask,
 135   IN OUT  PEI_MEMORY_RANGE_PCI_MEMORY           * PciMemoryMask
 136   );
 137
 138 struct _PEI_PLATFORM_MEMORY_RANGE_PPI {
 139   PEI_CHOOSE_RANGES ChooseRanges;
 140 };
 141
 142 extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;
 143
 144 #endif