4 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved
6 This program and the accompanying materials are licensed and made available under
7 the terms and conditions of the BSD License that accompanies this distribution.
8 The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 Interface definition details between ValleyView MRC and platform drivers during PEI phase.
25 #ifndef _VLV_POLICY_PPI_H_
26 #define _VLV_POLICY_PPI_H_
29 // MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}
31 #define VLV_POLICY_PPI_GUID \
33 0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \
37 // Extern the GUID for protocol users.
39 extern EFI_GUID gVlvPolicyPpiGuid
;
42 // PPI revision number
43 // Any backwards compatible changes to this PPI will result in an update in the revision number
44 // Major changes will require publication of a new PPI
46 #define MRC_PLATFORM_POLICY_PPI_REVISION 1
52 #define S3_TIMING_DATA_LEN 9
53 #define S3_READ_TRAINING_DATA_LEN 16
54 #define S3_WRITE_TRAINING_DATA_LEN 12
56 #ifndef S3_RESTORE_DATA_LEN
57 #define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)
58 #endif // S3_RESTORE_DATA_LEN
61 // MRC Platform Data Structure
64 UINT8 SpdAddressTable
[MAX_SOCKETS
];
65 UINT8 TSonDimmSmbusAddress
[MAX_SOCKETS
];
69 UINT32 WdbBaseAddress
; // Write Data Buffer area (WC caching mode)
82 UINT8 IgdDvmt50PreAlloc
;
86 UINT8 InternalGraphics
;
94 } MEMORY_CONFIGURATION
;
98 // MRC Platform Policiy PPI
100 typedef struct _VLV_POLICY_PPI
{
102 VLV_PLATFORM_DATA PlatformData
;
103 GT_CONFIGURATION GtConfig
;
104 MEMORY_CONFIGURATION MemConfig
;
105 VOID
*S3DataPtr
; // was called MRC_PARAMS_SAVE_RESTORE
106 UINT8 ISPEn
; //ISP (IUNIT) Device Enabled
107 UINT8 ISPPciDevConfig
; //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS
112 #endif // _VLV_POLICY_PPI_H_