Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvAccess.h

   1
   2 /*++
   3
   4 Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8
   9
  10 Module Name:
  11
  12   vlvAccess.h
  13
  14 Abstract:
  15
  16   Macros to simplify and abstract the interface to PCI configuration.
  17
  18 --*/
  19
  20 #ifndef _VLVACCESS_H_INCLUDED_
  21 #define _VLVACCESS_H_INCLUDED_
  22
  23 #include "Valleyview.h"
  24 #include "VlvCommonDefinitions.h"
  25 #include <Library/IoLib.h>
  26
  27 //
  28 // Memory Mapped IO access macros used by MSG BUS LIBRARY
  29 //
  30 #define MmioAddress( BaseAddr, Register ) \
  31   ( (UINTN)BaseAddr + \
  32     (UINTN)(Register) \
  33   )
  34
  35
  36 //
  37 // UINT32
  38 //
  39
  40 #define Mmio32Ptr( BaseAddr, Register ) \
  41   ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
  42
  43 #define Mmio32( BaseAddr, Register ) \
  44   *Mmio32Ptr( BaseAddr, Register )
  45
  46 #define Mmio32Or( BaseAddr, Register, OrData ) \
  47   Mmio32( BaseAddr, Register ) = \
  48     (UINT32) ( \
  49       Mmio32( BaseAddr, Register ) | \
  50       (UINT32)(OrData) \
  51     )
  52
  53 #define Mmio32And( BaseAddr, Register, AndData ) \
  54   Mmio32( BaseAddr, Register ) = \
  55     (UINT32) ( \
  56       Mmio32( BaseAddr, Register ) & \
  57       (UINT32)(AndData) \
  58     )
  59
  60 #define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \
  61   Mmio32( BaseAddr, Register ) = \
  62     (UINT32) ( \
  63       ( Mmio32( BaseAddr, Register ) & \
  64           (UINT32)(AndData) \
  65       ) | \
  66       (UINT32)(OrData) \
  67     )
  68
  69 //
  70 // UINT16
  71 //
  72
  73 #define Mmio16Ptr( BaseAddr, Register ) \
  74   ( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) )
  75
  76 #define Mmio16( BaseAddr, Register ) \
  77   *Mmio16Ptr( BaseAddr, Register )
  78
  79 #define Mmio16Or( BaseAddr, Register, OrData ) \
  80   Mmio16( BaseAddr, Register ) = \
  81     (UINT16) ( \
  82       Mmio16( BaseAddr, Register ) | \
  83       (UINT16)(OrData) \
  84     )
  85
  86 #define Mmio16And( BaseAddr, Register, AndData ) \
  87   Mmio16( BaseAddr, Register ) = \
  88     (UINT16) ( \
  89       Mmio16( BaseAddr, Register ) & \
  90       (UINT16)(AndData) \
  91     )
  92
  93 #define Mmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \
  94   Mmio16( BaseAddr, Register ) = \
  95     (UINT16) ( \
  96       ( Mmio16( BaseAddr, Register ) & \
  97           (UINT16)(AndData) \
  98       ) | \
  99       (UINT16)(OrData) \
 100     )
 101
 102 //
 103 // UINT8
 104 //
 105
 106 #define Mmio8Ptr( BaseAddr, Register ) \
 107   ( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) )
 108
 109 #define Mmio8( BaseAddr, Register ) \
 110   *Mmio8Ptr( BaseAddr, Register )
 111
 112 #define Mmio8Or( BaseAddr, Register, OrData ) \
 113   Mmio8( BaseAddr, Register ) = \
 114     (UINT8) ( \
 115       Mmio8( BaseAddr, Register ) | \
 116       (UINT8)(OrData) \
 117     )
 118
 119 #define Mmio8And( BaseAddr, Register, AndData ) \
 120   Mmio8( BaseAddr, Register ) = \
 121     (UINT8) ( \
 122       Mmio8( BaseAddr, Register ) & \
 123       (UINT8)(AndData) \
 124     )
 125
 126 #define Mmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \
 127   Mmio8( BaseAddr, Register ) = \
 128     (UINT8) ( \
 129       ( Mmio8( BaseAddr, Register ) & \
 130           (UINT8)(AndData) \
 131         ) | \
 132       (UINT8)(OrData) \
 133     )
 134
 135 //
 136 // MSG BUS API
 137 //
 138
 139 #define MSG_BUS_ENABLED     0x000000F0
 140 #define MSGBUS_MASKHI       0xFFFFFF00
 141 #define MSGBUS_MASKLO       0x000000FF
 142
 143 #define MESSAGE_BYTE_EN          BIT4
 144 #define MESSAGE_WORD_EN          BIT4 | BIT5
 145 #define MESSAGE_DWORD_EN         BIT4 | BIT5 | BIT6 | BIT7
 146
 147 #define SIDEBAND_OPCODE          0x78
 148 #define MEMREAD_OPCODE           0x00000000
 149 #define MEMWRITE_OPCODE          0x01000000
 150
 151
 152
 153 /***************************/
 154 //
 155 // Memory mapped PCI IO
 156 //
 157
 158 #define PciCfgPtr(Bus, Device, Function, Register )\
 159     (UINTN)(Bus << 20) + \
 160     (UINTN)(Device << 15) + \
 161     (UINTN)(Function << 12) + \
 162     (UINTN)(Register)
 163
 164 #define PciCfg32Read_CF8CFC(B,D,F,R) \
 165   (UINT32)(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoIn32(0xCFC))
 166
 167 #define PciCfg32Write_CF8CFC(B,D,F,R,Data) \
 168   (IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoOut32(0xCFC,Data))
 169
 170 #define PciCfg32Or_CF8CFC(B,D,F,R,O) \
 171   PciCfg32Write_CF8CFC(B,D,F,R, \
 172     (PciCfg32Read_CF8CFC(B,D,F,R) | (O)))
 173
 174 #define PciCfg32And_CF8CFC(B,D,F,R,A) \
 175   PciCfg32Write_CF8CFC(B,D,F,R, \
 176     (PciCfg32Read_CF8CFC(B,D,F,R) & (A)))
 177
 178 #define PciCfg32AndThenOr_CF8CFC(B,D,F,R,A,O) \
 179   PciCfg32Write_CF8CFC(B,D,F,R, \
 180     (PciCfg32Read_CF8CFC(B,D,F,R) & (A)) | (O))
 181
 182 //
 183 // Device 0, Function 0
 184 //
 185 #define McD0PciCfg64(Register)                              MmPci64           (0, MC_BUS, 0, 0, Register)
 186 #define McD0PciCfg64Or(Register, OrData)                    MmPci64Or         (0, MC_BUS, 0, 0, Register, OrData)
 187 #define McD0PciCfg64And(Register, AndData)                  MmPci64And        (0, MC_BUS, 0, 0, Register, AndData)
 188 #define McD0PciCfg64AndThenOr(Register, AndData, OrData)    MmPci64AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)
 189
 190 #define McD0PciCfg32(Register)                              MmPci32           (0, MC_BUS, 0, 0, Register)
 191 #define McD0PciCfg32Or(Register, OrData)                    MmPci32Or         (0, MC_BUS, 0, 0, Register, OrData)
 192 #define McD0PciCfg32And(Register, AndData)                  MmPci32And        (0, MC_BUS, 0, 0, Register, AndData)
 193 #define McD0PciCfg32AndThenOr(Register, AndData, OrData)    MmPci32AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)
 194
 195 #define McD0PciCfg16(Register)                              MmPci16           (0, MC_BUS, 0, 0, Register)
 196 #define McD0PciCfg16Or(Register, OrData)                    MmPci16Or         (0, MC_BUS, 0, 0, Register, OrData)
 197 #define McD0PciCfg16And(Register, AndData)                  MmPci16And        (0, MC_BUS, 0, 0, Register, AndData)
 198 #define McD0PciCfg16AndThenOr(Register, AndData, OrData)    MmPci16AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)
 199
 200 #define McD0PciCfg8(Register)                               MmPci8            (0, MC_BUS, 0, 0, Register)
 201 #define McD0PciCfg8Or(Register, OrData)                     MmPci8Or          (0, MC_BUS, 0, 0, Register, OrData)
 202 #define McD0PciCfg8And(Register, AndData)                   MmPci8And         (0, MC_BUS, 0, 0, Register, AndData)
 203 #define McD0PciCfg8AndThenOr( Register, AndData, OrData )   MmPci8AndThenOr   (0, MC_BUS, 0, 0, Register, AndData, OrData)
 204
 205
 206 //
 207 // Device 2, Function 0
 208 //
 209 #define McD2PciCfg64(Register)                              MmPci64           (0, MC_BUS, 2, 0, Register)
 210 #define McD2PciCfg64Or(Register, OrData)                    MmPci64Or         (0, MC_BUS, 2, 0, Register, OrData)
 211 #define McD2PciCfg64And(Register, AndData)                  MmPci64And        (0, MC_BUS, 2, 0, Register, AndData)
 212 #define McD2PciCfg64AndThenOr(Register, AndData, OrData)    MmPci64AndThenOr  (0, MC_BUS, 2, 0, Register, AndData, OrData)
 213
 214 #define McD2PciCfg32(Register)                              MmPci32           (0, MC_BUS, 2, 0, Register)
 215 #define McD2PciCfg32Or(Register, OrData)                    MmPci32Or         (0, MC_BUS, 2, 0, Register, OrData)
 216 #define McD2PciCfg32And(Register, AndData)                  MmPci32And        (0, MC_BUS, 2, 0, Register, AndData)
 217 #define McD2PciCfg32AndThenOr(Register, AndData, OrData)    MmPci32AndThenOr  (0, MC_BUS, 2, 0, Register, AndData, OrData)
 218
 219 #define McD2PciCfg16(Register)                              MmPci16           (0, MC_BUS, 2, 0, Register)
 220 #define McD2PciCfg16Or(Register, OrData)                    MmPci16Or         (0, MC_BUS, 2, 0, Register, OrData)
 221 #define McD2PciCfg16And(Register, AndData)                  MmPci16And        (0, MC_BUS, 2, 0, Register, AndData)
 222 #define McD2PciCfg16AndThenOr(Register, AndData, OrData)    MmPci16AndThenOr  (0, MC_BUS, 2, 0, Register, AndData, OrData)
 223
 224 #define McD2PciCfg8(Register)                               MmPci8            (0, MC_BUS, 2, 0, Register)
 225 #define McD2PciCfg8Or(Register, OrData)                     MmPci8Or          (0, MC_BUS, 2, 0, Register, OrData)
 226 #define McD2PciCfg8And(Register, AndData)                   MmPci8And         (0, MC_BUS, 2, 0, Register, AndData)
 227
 228 //
 229 // IO
 230 //
 231
 232 #ifndef IoIn8
 233
 234 #define IoIn8(Port) \
 235   IoRead8(Port)
 236
 237 #define IoIn16(Port) \
 238   IoRead16(Port)
 239
 240 #define IoIn32(Port) \
 241   IoRead32(Port)
 242
 243 #define IoOut8(Port, Data) \
 244   IoWrite8(Port, Data)
 245
 246 #define IoOut16(Port, Data) \
 247   IoWrite16(Port, Data)
 248
 249 #define IoOut32(Port, Data) \
 250   IoWrite32(Port, Data)
 251
 252 #endif
 253
 254 #endif