Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvCommonDefinitions.h

   1
   2 /*++
   3
   4 Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8
   9
  10 Module Name:
  11
  12   VlvCommonDefinitions.h
  13
  14 Abstract:
  15
  16   Macros to simplify and abstract the interface to PCI configuration.
  17
  18 --*/
  19
  20 ///
  21 /// PCI CONFIGURATION MAP REGISTER OFFSETS
  22 ///
  23 #ifndef PCI_VID
  24 #define PCI_VID             0x0000  ///< Vendor ID Register
  25 #define PCI_DID             0x0002  ///< Device ID Register
  26 #define PCI_CMD             0x0004  ///< PCI Command Register
  27 #define PCI_STS             0x0006  ///< PCI Status Register
  28 #define PCI_RID             0x0008  ///< Revision ID Register
  29 #define PCI_IFT             0x0009  ///< Interface Type
  30 #define PCI_SCC             0x000A  ///< Sub Class Code Register
  31 #define PCI_BCC             0x000B  ///< Base Class Code Register
  32 #define PCI_CLS             0x000C  ///< Cache Line Size
  33 #define PCI_PMLT            0x000D  ///< Primary Master Latency Timer
  34 #define PCI_HDR             0x000E  ///< Header Type Register
  35 #define PCI_BIST            0x000F  ///< Built in Self Test Register
  36 #define PCI_BAR0            0x0010  ///< Base Address Register 0
  37 #define PCI_BAR1            0x0014  ///< Base Address Register 1
  38 #define PCI_BAR2            0x0018  ///< Base Address Register 2
  39 #define PCI_PBUS            0x0018  ///< Primary Bus Number Register
  40 #define PCI_SBUS            0x0019  ///< Secondary Bus Number Register
  41 #define PCI_SUBUS           0x001A  ///< Subordinate Bus Number Register
  42 #define PCI_SMLT            0x001B  ///< Secondary Master Latency Timer
  43 #define PCI_BAR3            0x001C  ///< Base Address Register 3
  44 #define PCI_IOBASE          0x001C  ///< I/O base Register
  45 #define PCI_IOLIMIT         0x001D  ///< I/O Limit Register
  46 #define PCI_SECSTATUS       0x001E  ///< Secondary Status Register
  47 #define PCI_BAR4            0x0020  ///< Base Address Register 4
  48 #define PCI_MEMBASE         0x0020  ///< Memory Base Register
  49 #define PCI_MEMLIMIT        0x0022  ///< Memory Limit Register
  50 #define PCI_BAR5            0x0024  ///< Base Address Register 5
  51 #define PCI_PRE_MEMBASE     0x0024  ///< Prefetchable memory Base register
  52 #define PCI_PRE_MEMLIMIT    0x0026  ///< Prefetchable memory Limit register
  53 #define PCI_PRE_MEMBASE_U   0x0028  ///< Prefetchable memory base upper 32 bits
  54 #define PCI_PRE_MEMLIMIT_U  0x002C  ///< Prefetchable memory limit upper 32 bits
  55 #define PCI_SVID            0x002C  ///< Subsystem Vendor ID
  56 #define PCI_SID             0x002E  ///< Subsystem ID
  57 #define PCI_IOBASE_U        0x0030  ///< I/O base Upper Register
  58 #define PCI_IOLIMIT_U       0x0032  ///< I/O Limit Upper Register
  59 #define PCI_CAPP            0x0034  ///< Capabilities Pointer
  60 #define PCI_EROM            0x0038  ///< Expansion ROM Base Address
  61 #define PCI_INTLINE         0x003C  ///< Interrupt Line Register
  62 #define PCI_INTPIN          0x003D  ///< Interrupt Pin Register
  63 #define PCI_MAXGNT          0x003E  ///< Max Grant Register
  64 #define PCI_BRIDGE_CNTL     0x003E  ///< Bridge Control Register
  65 #define PCI_MAXLAT          0x003F  ///< Max Latency Register
  66 #endif
  67 //
  68 // Bit Difinitions
  69 //
  70 #ifndef BIT0
  71 #define BIT0                     0x0001
  72 #define BIT1                     0x0002
  73 #define BIT2                     0x0004
  74 #define BIT3                     0x0008
  75 #define BIT4                     0x0010
  76 #define BIT5                     0x0020
  77 #define BIT6                     0x0040
  78 #define BIT7                     0x0080
  79 #define BIT8                     0x0100
  80 #define BIT9                     0x0200
  81 #define BIT10                    0x0400
  82 #define BIT11                    0x0800
  83 #define BIT12                    0x1000
  84 #define BIT13                    0x2000
  85 #define BIT14                    0x4000
  86 #define BIT15                    0x8000
  87 #define BIT16                    0x00010000
  88 #define BIT17                    0x00020000
  89 #define BIT18                    0x00040000
  90 #define BIT19                    0x00080000
  91 #define BIT20                    0x00100000
  92 #define BIT21                    0x00200000
  93 #define BIT22                    0x00400000
  94 #define BIT23                    0x00800000
  95 #define BIT24                    0x01000000
  96 #define BIT25                    0x02000000
  97 #define BIT26                    0x04000000
  98 #define BIT27                    0x08000000
  99 #define BIT28                    0x10000000
 100 #define BIT29                    0x20000000
 101 #define BIT30                    0x40000000
 102 #define BIT31                    0x80000000
 103 #endif
 104
 105 #ifndef _PCIACCESS_H_INCLUDED_
 106 #define _PCIACCESS_H_INCLUDED_
 107 #ifndef PCI_EXPRESS_BASE_ADDRESS
 108  #define PCI_EXPRESS_BASE_ADDRESS 0xE0000000
 109 #endif
 110
 111 #ifndef MmPciAddress
 112 #define MmPciAddress( Segment, Bus, Device, Function, Register ) \
 113   ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \
 114     (UINTN)(Bus << 20) + \
 115     (UINTN)(Device << 15) + \
 116     (UINTN)(Function << 12) + \
 117     (UINTN)(Register) \
 118   )
 119 #endif
 120
 121 //
 122 // UINT64
 123 //
 124 #define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \
 125   ( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
 126
 127 #define MmPci64( Segment, Bus, Device, Function, Register ) \
 128   *MmPci64Ptr( Segment, Bus, Device, Function, Register )
 129
 130 #define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \
 131   MmPci64( Segment, Bus, Device, Function, Register ) = \
 132     (UINT64) ( \
 133       MmPci64( Segment, Bus, Device, Function, Register ) | \
 134       (UINT64)(OrData) \
 135     )
 136
 137 #define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \
 138   MmPci64( Segment, Bus, Device, Function, Register ) = \
 139     (UINT64) ( \
 140       MmPci64( Segment, Bus, Device, Function, Register ) & \
 141       (UINT64)(AndData) \
 142     )
 143
 144 #define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
 145   MmPci64( Segment, Bus, Device, Function, Register ) = \
 146     (UINT64) ( \
 147       ( MmPci64( Segment, Bus, Device, Function, Register ) & \
 148           (UINT64)(AndData) \
 149       ) | \
 150       (UINT64)(OrData) \
 151     )
 152
 153 //
 154 // UINT32
 155 //
 156
 157 #define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \
 158   ( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) )
 159
 160 #define MmPci32( Segment, Bus, Device, Function, Register ) \
 161   *MmPci32Ptr( Segment, Bus, Device, Function, Register )
 162
 163 #define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
 164   MmPci32( Segment, Bus, Device, Function, Register ) = \
 165     (UINT32) ( \
 166       MmPci32( Segment, Bus, Device, Function, Register ) | \
 167       (UINT32)(OrData) \
 168     )
 169
 170 #define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
 171   MmPci32( Segment, Bus, Device, Function, Register ) = \
 172     (UINT32) ( \
 173       MmPci32( Segment, Bus, Device, Function, Register ) & \
 174       (UINT32)(AndData) \
 175     )
 176
 177 #define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
 178   MmPci32( Segment, Bus, Device, Function, Register ) = \
 179     (UINT32) ( \
 180       ( MmPci32( Segment, Bus, Device, Function, Register ) & \
 181           (UINT32)(AndData) \
 182       ) | \
 183       (UINT32)(OrData) \
 184     )
 185
 186 //
 187 // UINT16
 188 //
 189
 190 #define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \
 191   ( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
 192
 193 #define MmPci16( Segment, Bus, Device, Function, Register ) \
 194   *MmPci16Ptr( Segment, Bus, Device, Function, Register )
 195
 196 #define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
 197   MmPci16( Segment, Bus, Device, Function, Register ) = \
 198     (UINT16) ( \
 199       MmPci16( Segment, Bus, Device, Function, Register ) | \
 200       (UINT16)(OrData) \
 201     )
 202
 203 #define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
 204   MmPci16( Segment, Bus, Device, Function, Register ) = \
 205     (UINT16) ( \
 206       MmPci16( Segment, Bus, Device, Function, Register ) & \
 207       (UINT16)(AndData) \
 208     )
 209
 210 #define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
 211   MmPci16( Segment, Bus, Device, Function, Register ) = \
 212     (UINT16) ( \
 213       ( MmPci16( Segment, Bus, Device, Function, Register ) & \
 214           (UINT16)(AndData) \
 215       ) | \
 216       (UINT16)(OrData) \
 217     )
 218
 219 //
 220 // UINT8
 221 //
 222
 223 #define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \
 224   ( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
 225
 226 #define MmPci8( Segment, Bus, Device, Function, Register ) \
 227   *MmPci8Ptr( Segment, Bus, Device, Function, Register )
 228
 229 #define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
 230   MmPci8( Segment, Bus, Device, Function, Register ) = \
 231     (UINT8) ( \
 232       MmPci8( Segment, Bus, Device, Function, Register ) | \
 233       (UINT8)(OrData) \
 234     )
 235
 236 #define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
 237   MmPci8( Segment, Bus, Device, Function, Register ) = \
 238     (UINT8) ( \
 239       MmPci8( Segment, Bus, Device, Function, Register ) & \
 240       (UINT8)(AndData) \
 241     )
 242
 243 #define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
 244   MmPci8( Segment, Bus, Device, Function, Register ) = \
 245     (UINT8) ( \
 246       ( MmPci8( Segment, Bus, Device, Function, Register ) & \
 247           (UINT8)(AndData) \
 248         ) | \
 249       (UINT8)(OrData) \
 250     )
 251
 252 #endif