Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/Mmc.h

   1 /*++
   2
   3 Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8 --*/
   9
  10
  11 /*++
  12
  13 Module Name:
  14
  15   MMC.h
  16
  17 Abstract:
  18
  19   Header file for Industry MMC 4.2 spec.
  20
  21 --*/
  22
  23 #ifndef _MMC_H
  24 #define _MMC_H
  25
  26 #pragma pack(1)
  27 //
  28 //Command definition
  29 //
  30
  31 #define  CMD0              0
  32 #define  CMD1              1
  33 #define  CMD2              2
  34 #define  CMD3              3
  35 #define  CMD4              4
  36 #define  CMD6              6
  37 #define  CMD7              7
  38 #define  CMD8              8
  39 #define  CMD9              9
  40 #define  CMD10             10
  41 #define  CMD11             11
  42 #define  CMD12             12
  43 #define  CMD13             13
  44 #define  CMD14             14
  45 #define  CMD15             15
  46 #define  CMD16             16
  47 #define  CMD17             17
  48 #define  CMD18             18
  49 #define  CMD19             19
  50 #define  CMD20             20
  51 #define  CMD23             23
  52 #define  CMD24             24
  53 #define  CMD25             25
  54 #define  CMD26             26
  55 #define  CMD27             27
  56 #define  CMD28             28
  57 #define  CMD29             29
  58 #define  CMD30             30
  59 #define  CMD35             35
  60 #define  CMD36             36
  61 #define  CMD38             38
  62 #define  CMD39             39
  63 #define  CMD40             40
  64 #define  CMD42             42
  65 #define  CMD55             55
  66 #define  CMD56             56
  67
  68
  69
  70 #define  GO_IDLE_STATE           CMD0
  71 #define  SEND_OP_COND            CMD1
  72 #define  ALL_SEND_CID            CMD2
  73 #define  SET_RELATIVE_ADDR       CMD3
  74 #define  SET_DSR                 CMD4
  75 #define  SWITCH                  CMD6
  76 #define  SELECT_DESELECT_CARD    CMD7
  77 #define  SEND_EXT_CSD            CMD8
  78 #define  SEND_CSD                CMD9
  79 #define  SEND_CID                CMD10
  80 #define  READ_DAT_UNTIL_STOP     CMD11
  81 #define  STOP_TRANSMISSION       CMD12
  82 #define  SEND_STATUS             CMD13
  83 #define  BUSTEST_R               CMD14
  84 #define  GO_INACTIVE_STATE       CMD15
  85 #define  SET_BLOCKLEN            CMD16
  86 #define  READ_SINGLE_BLOCK       CMD17
  87 #define  READ_MULTIPLE_BLOCK     CMD18
  88 #define  BUSTEST_W               CMD19
  89 #define  WRITE_DAT_UNTIL_STOP    CMD20
  90 #define  SET_BLOCK_COUNT         CMD23
  91 #define  WRITE_BLOCK             CMD24
  92 #define  WRITE_MULTIPLE_BLOCK    CMD25
  93 #define  PROGRAM_CID             CMD26
  94 #define  PROGRAM_CSD             CMD27
  95 #define  SET_WRITE_PROT          CMD28
  96 #define  CLR_WRITE_PROT          CMD29
  97 #define  SEND_WRITE_PROT         CMD30
  98 #define  ERASE_GROUP_START       CMD35
  99 #define  ERASE_GROUP_END         CMD36
 100 #define  ERASE                   CMD38
 101 #define  FAST_IO                 CMD39
 102 #define  GO_IRQ_STATE            CMD40
 103 #define  LOCK_UNLOCK             CMD42
 104 #define  APP_CMD                 CMD55
 105 #define  GEN_CMD                 CMD56
 106
 107 #define B_PERM_WP_DIS            0x10
 108 #define B_PWR_WP_EN              0x01
 109 #define US_PERM_WP_DIS           0x10
 110 #define US_PWR_WP_EN             0x01
 111
 112 #define FREQUENCY_OD            (400 * 1000)
 113 #define FREQUENCY_MMC_PP        (26 * 1000 * 1000)
 114 #define FREQUENCY_MMC_PP_HIGH   (52 * 1000 * 1000)
 115
 116 #define DEFAULT_DSR_VALUE        0x404
 117
 118 //
 119 //Registers definition
 120 //
 121
 122 typedef struct {
 123   UINT32  Reserved0:   7;  // 0
 124   UINT32  V170_V195:   1;  // 1.70V - 1.95V
 125   UINT32  V200_V260:   7;  // 2.00V - 2.60V
 126   UINT32  V270_V360:   9;  // 2.70V - 3.60V
 127   UINT32  Reserved1:   5;  // 0
 128   UINT32  AccessMode:  2;  // 00b (byte mode), 10b (sector mode)
 129   UINT32  Busy:        1;  // This bit is set to LOW if the card has not finished the power up routine
 130 } OCR;
 131
 132
 133 typedef struct {
 134   UINT8   NotUsed:     1; //  1
 135   UINT8   CRC:         7; //  CRC7 checksum
 136   UINT8   MDT;            //  Manufacturing date
 137   UINT32  PSN;            //  Product serial number
 138   UINT8   PRV;            //  Product revision
 139   UINT8   PNM[6];         //  Product name
 140   UINT16  OID;            //  OEM/Application ID
 141   UINT8   MID;            //  Manufacturer ID
 142 } CID;
 143
 144
 145 typedef struct {
 146   UINT8   NotUsed:            1; //  1 [0:0]
 147   UINT8   CRC:                7; //  CRC [7:1]
 148   UINT8   ECC:                2; //  ECC code [9:8]
 149   UINT8   FILE_FORMAT:        2; //  File format [11:10]
 150   UINT8   TMP_WRITE_PROTECT:  1; //  Temporary write protection [12:12]
 151   UINT8   PERM_WRITE_PROTECT: 1; //  Permanent write protection [13:13]
 152   UINT8   COPY:               1; //  Copy flag (OTP) [14:14]
 153   UINT8   FILE_FORMAT_GRP:    1; //  File format group [15:15]
 154   UINT16  CONTENT_PROT_APP:   1; //  Content protection application [16:16]
 155   UINT16  Reserved0:          4; //  0 [20:17]
 156   UINT16  WRITE_BL_PARTIAL:   1; //  Partial blocks for write allowed [21:21]
 157   UINT16  WRITE_BL_LEN:       4; //  Max. write data block length [25:22]
 158   UINT16  R2W_FACTOR:         3; //  Write speed factor [28:26]
 159   UINT16  DEFAULT_ECC:        2; //  Manufacturer default ECC [30:29]
 160   UINT16  WP_GRP_ENABLE:      1; //  Write protect group enable [31:31]
 161   UINT32  WP_GRP_SIZE:        5; //  Write protect group size [36:32]
 162   UINT32  ERASE_GRP_MULT:     5; //  Erase group size multiplier [41:37]
 163   UINT32  ERASE_GRP_SIZE:     5; //  Erase group size [46:42]
 164   UINT32  C_SIZE_MULT:        3; //  Device size multiplier [49:47]
 165   UINT32  VDD_W_CURR_MAX:     3; //  Max. write current @ VDD max [52:50]
 166   UINT32  VDD_W_CURR_MIN:     3; //  Max. write current @ VDD min [55:53]
 167   UINT32  VDD_R_CURR_MAX:     3; //  Max. read current @ VDD max [58:56]
 168   UINT32  VDD_R_CURR_MIN:     3; //  Max. read current @ VDD min [61:59]
 169   UINT32  C_SIZELow2:         2;//  Device size [73:62]
 170   UINT32  C_SIZEHigh10:       10;//  Device size [73:62]
 171   UINT32  Reserved1:          2; //  0 [75:74]
 172   UINT32  DSR_IMP:            1; //  DSR implemented [76:76]
 173   UINT32  READ_BLK_MISALIGN:  1; //  Read block misalignment [77:77]
 174   UINT32  WRITE_BLK_MISALIGN: 1; //  Write block misalignment [78:78]
 175   UINT32  READ_BL_PARTIAL:    1; //  Partial blocks for read allowed [79:79]
 176   UINT32  READ_BL_LEN:        4; //  Max. read data block length [83:80]
 177   UINT32  CCC:                12;//  Card command classes [95:84]
 178   UINT8   TRAN_SPEED          ; //  Max. bus clock frequency [103:96]
 179   UINT8   NSAC                ; //  Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
 180   UINT8   TAAC                ; //  Data read access-time 1 [119:112]
 181   UINT8   Reserved2:          2; //  0 [121:120]
 182   UINT8   SPEC_VERS:          4; //  System specification version [125:122]
 183   UINT8   CSD_STRUCTURE:      2; //  CSD structure [127:126]
 184 } CSD;
 185
 186 typedef struct {
 187   UINT8  Reserved133_0[134];     // [133:0] 0
 188   UINT8  SEC_BAD_BLOCK_MGMNT;    // [134] Bad Block Management mode
 189   UINT8  Reserved135;            // [135] 0
 190   UINT8  ENH_START_ADDR[4];      // [139:136] Enhanced User Data Start Address
 191   UINT8  ENH_SIZE_MULT[3];       // [142:140] Enhanced User Data Start Size
 192   UINT8  GP_SIZE_MULT_1[3];      // [145:143] GPP1 Size
 193   UINT8  GP_SIZE_MULT_2[3];      // [148:146] GPP2 Size
 194   UINT8  GP_SIZE_MULT_3[3];      // [151:149] GPP3 Size
 195   UINT8  GP_SIZE_MULT_4[3];      // [154:152] GPP4 Size
 196   UINT8  PARTITION_SETTING_COMPLETED; // [155] Partitioning Setting
 197   UINT8  PARTITIONS_ATTRIBUTES;  // [156] Partitions attributes
 198   UINT8  MAX_ENH_SIZE_MULT[3];   // [159:157] GPP4 Start Size
 199   UINT8  PARTITIONING_SUPPORT;   // [160] Partitioning Support
 200   UINT8  HPI_MGMT;               // [161] HPI management
 201   UINT8  RST_n_FUNCTION;         // [162] H/W reset function
 202   UINT8  BKOPS_EN;               // [163] Enable background operations handshake
 203   UINT8  BKOPS_START;            // [164] Manually start background operations
 204   UINT8  Reserved165;            // [165] 0
 205   UINT8  WR_REL_PARAM;           // [166] Write reliability parameter register
 206   UINT8  WR_REL_SET;             // [167] Write reliability setting register
 207   UINT8  RPMB_SIZE_MULT;         // [168] RPMB Size
 208   UINT8  FW_CONFIG;              // [169] FW configuration
 209   UINT8  Reserved170;            // [170] 0
 210   UINT8  USER_WP;                // [171] User area write protection
 211   UINT8  Reserved172;            // [172] 0
 212   UINT8  BOOT_WP;                // [173] Boot area write protection
 213   UINT8  Reserved174;            // [174] 0
 214   UINT8  ERASE_GROUP_DEF;        // [175] High density erase group definition
 215   UINT8  Reserved176;            // [176] 0
 216   UINT8  BOOT_BUS_WIDTH;         // [177] Boot bus width
 217   UINT8  BOOT_CONFIG_PROT;       // [178] Boot config protection
 218   UINT8  PARTITION_CONFIG;       // [179] Partition config
 219   UINT8  Reserved180;            // [180] 0
 220   UINT8  ERASED_MEM_CONT;        // [181] Erased Memory Content
 221   UINT8  Reserved182;            // [182] 0
 222   UINT8  BUS_WIDTH;              // [183] Bus Width Mode
 223   UINT8  Reserved184;            // [184] 0
 224   UINT8  HS_TIMING;              // [185] High Speed Interface Timing
 225   UINT8  Reserved186;            // [186] 0
 226   UINT8  POWER_CLASS;            // [187] Power Class
 227   UINT8  Reserved188;            // [188] 0
 228   UINT8  CMD_SET_REV;            // [189] Command Set Revision
 229   UINT8  Reserved190;            // [190] 0
 230   UINT8  CMD_SET;                // [191] Command Set
 231   UINT8  EXT_CSD_REV;            // [192] Extended CSD Revision
 232   UINT8  Reserved193;            // [193] 0
 233   UINT8  CSD_STRUCTURE;          // [194] CSD Structure Version
 234   UINT8  Reserved195;            // [195] 0
 235   UINT8  CARD_TYPE;              // [196] Card Type
 236   UINT8  Reserved197;            // [197] 0
 237   UINT8  OUT_OF_INTERRUPT_TIME;  // [198] Out-of-interrupt busy timing
 238   UINT8  PARTITION_SWITCH_TIME;  // [199] Partition switching timing
 239   UINT8  PWR_CL_52_195;          // [200] Power Class for 52MHz @ 1.95V
 240   UINT8  PWR_CL_26_195;          // [201] Power Class for 26MHz @ 1.95V
 241   UINT8  PWR_CL_52_360;          // [202] Power Class for 52MHz @ 3.6V
 242   UINT8  PWR_CL_26_360;          // [203] Power Class for 26MHz @ 3.6V
 243   UINT8  Reserved204;            // [204] 0
 244   UINT8  MIN_PERF_R_4_26;        // [205] Minimum Read Performance for 4bit @26MHz
 245   UINT8  MIN_PERF_W_4_26;        // [206] Minimum Write Performance for 4bit @26MHz
 246   UINT8  MIN_PERF_R_8_26_4_52;   // [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz
 247   UINT8  MIN_PERF_W_8_26_4_52;   // [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz
 248   UINT8  MIN_PERF_R_8_52;        // [209] Minimum Read Performance for 8bit @52MHz
 249   UINT8  MIN_PERF_W_8_52;        // [210] Minimum Write Performance for 8bit @52MHz
 250   UINT8  Reserved211;            // [211] 0
 251   UINT8  SEC_COUNT[4];           // [215:212] Sector Count
 252   UINT8  Reserved216;            // [216] 0
 253   UINT8  S_A_TIMEOUT;            // [217] Sleep/awake timeout
 254   UINT8  Reserved218;            // [218] 0
 255   UINT8  S_C_VCCQ;               // [219] Sleep current (VCCQ)
 256   UINT8  S_C_VCC;                // [220] Sleep current (VCC)
 257   UINT8  HC_WP_GRP_SIZE;         // [221] High-capacity write protect group size
 258   UINT8  REL_WR_SEC_C;           // [222] Reliable write sector count
 259   UINT8  ERASE_TIMEOUT_MULT;     // [223] High-capacity erase timeout
 260   UINT8  HC_ERASE_GRP_SIZE;      // [224] High-capacity erase unit size
 261   UINT8  ACC_SIZE;               // [225] Access size
 262   UINT8  BOOT_SIZE_MULTI;        // [226] Boot partition size
 263   UINT8  Reserved227;            // [227] 0
 264   UINT8  BOOT_INFO;              // [228] Boot information
 265   UINT8  SEC_TRIM_MULT;          // [229] Secure TRIM Multiplier
 266   UINT8  SEC_ERASE_MULT;         // [230] Secure Erase Multiplier
 267   UINT8  SEC_FEATURE_SUPPORT;    // [231] Secure Feature support
 268   UINT8  TRIM_MULT;              // [232] TRIM Multiplier
 269   UINT8  Reserved233;            // [233] 0
 270   UINT8  MIN_PERF_DDR_R_8_52;    // [234] Min Read Performance for 8-bit @ 52MHz
 271   UINT8  MIN_PERF_DDR_W_8_52;    // [235] Min Write Performance for 8-bit @ 52MHz
 272   UINT8  Reserved237_236[2];     // [237:236] 0
 273   UINT8  PWR_CL_DDR_52_195;      // [238] Power class for 52MHz, DDR at 1.95V
 274   UINT8  PWR_CL_DDR_52_360;      // [239] Power class for 52MHz, DDR at 3.6V
 275   UINT8  Reserved240;            // [240] 0
 276   UINT8  INI_TIMEOUT_AP;         // [241] 1st initialization time after partitioning
 277   UINT8  CORRECTLY_PRG_SECTORS_NUM[4]; // [245:242] Number of correctly programmed sectors
 278   UINT8  BKOPS_STATUS;           // [246] Background operations status
 279   UINT8  Reserved501_247[255];   // [501:247] 0
 280   UINT8  BKOPS_SUPPORT;          // [502] Background operations support
 281   UINT8  HPI_FEATURES;           // [503] HPI features
 282   UINT8  S_CMD_SET;              // [504] Sector Count
 283   UINT8  Reserved511_505[7];     // [511:505] Sector Count
 284 } EXT_CSD;
 285
 286
 287 //
 288 //Card Status definition
 289 //
 290 typedef struct {
 291   UINT32  Reserved0:           2; //Reserved for Manufacturer Test Mode
 292   UINT32  Reserved1:           2; //Reserved for Application Specific commands
 293   UINT32  Reserved2:           1; //
 294   UINT32  SAPP_CMD:            1; //
 295   UINT32  Reserved3:           1; //Reserved
 296   UINT32  SWITCH_ERROR:        1; //
 297   UINT32  READY_FOR_DATA:      1; //
 298   UINT32  CURRENT_STATE:       4; //
 299   UINT32  ERASE_RESET:         1; //
 300   UINT32  Reserved4:           1; //Reserved
 301   UINT32  WP_ERASE_SKIP:       1; //
 302   UINT32  CID_CSD_OVERWRITE:   1; //
 303   UINT32  OVERRUN:             1; //
 304   UINT32  UNDERRUN:            1; //
 305   UINT32  ERROR:               1; //
 306   UINT32  CC_ERROR:            1; //
 307   UINT32  CARD_ECC_FAILED:     1; //
 308   UINT32  ILLEGAL_COMMAND:     1; //
 309   UINT32  COM_CRC_ERROR:       1; //
 310   UINT32  LOCK_UNLOCK_FAILED:  1; //
 311   UINT32  CARD_IS_LOCKED:      1; //
 312   UINT32  WP_VIOLATION:        1; //
 313   UINT32  ERASE_PARAM:         1; //
 314   UINT32  ERASE_SEQ_ERROR:     1; //
 315   UINT32  BLOCK_LEN_ERROR:     1; //
 316   UINT32  ADDRESS_MISALIGN:    1; //
 317   UINT32  ADDRESS_OUT_OF_RANGE:1; //
 318 } CARD_STATUS;
 319
 320 typedef struct {
 321   UINT32  CmdSet:              3;
 322   UINT32  Reserved0:           5;
 323   UINT32  Value:               8;
 324   UINT32  Index:               8;
 325   UINT32  Access:              2;
 326   UINT32  Reserved1:           6;
 327 } SWITCH_ARGUMENT;
 328
 329 #define CommandSet_Mode          0
 330 #define SetBits_Mode             1
 331 #define ClearBits_Mode           2
 332 #define WriteByte_Mode           3
 333
 334
 335 #define  Idle_STATE              0
 336 #define  Ready_STATE             1
 337 #define  Ident_STATE             2
 338 #define  Stby_STATE              3
 339 #define  Tran_STATE              4
 340 #define  Data_STATE              5
 341 #define  Rcv_STATE               6
 342 #define  Prg_STATE               7
 343 #define  Dis_STATE               8
 344 #define  Btst_STATE              9
 345
 346
 347
 348 #pragma pack()
 349 #endif