Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchAccess.h

   1 /**
   2
   3 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9   @file
  10   PchAccess.h
  11
  12   @brief
  13   Macros that simplify accessing PCH devices's PCI registers.
  14
  15   ** NOTE ** these macros assume the PCH device is on BUS 0
  16
  17 **/
  18 #ifndef _PCH_ACCESS_H_
  19 #define _PCH_ACCESS_H_
  20
  21 #include "PchRegs.h"
  22 #include "PchCommonDefinitions.h"
  23
  24 #ifndef STALL_ONE_MICRO_SECOND
  25 #define STALL_ONE_MICRO_SECOND 1
  26 #endif
  27 #ifndef STALL_ONE_SECOND
  28 #define STALL_ONE_SECOND 1000000
  29 #endif
  30
  31 ///
  32 /// Memory Mapped PCI Access macros
  33 ///
  34 ///
  35 /// PCI Device MM Base
  36 ///
  37 #ifndef MmPciAddress
  38 #define MmPciAddress(Segment, Bus, Device, Function, Register) \
  39   ((UINTN) PatchPcdGet64 (PcdPciExpressBaseAddress) + \
  40    (UINTN) (Bus << 20) + \
  41    (UINTN) (Device << 15) + \
  42    (UINTN) (Function << 12) + \
  43    (UINTN) (Register) \
  44   )
  45 #endif
  46 ///
  47 /// Pch Controller PCI access macros
  48 ///
  49 #define PCH_RCRB_BASE ( \
  50   MmioRead32 (MmPciAddress (0, \
  51   DEFAULT_PCI_BUS_NUMBER_PCH, \
  52   PCI_DEVICE_NUMBER_PCH_LPC, \
  53   PCI_FUNCTION_NUMBER_PCH_LPC), \
  54   R_PCH_LPC_RCBA)) & B_PCH_LPC_RCBA_BAR \
  55   )
  56
  57 ///
  58 /// Device 0x1b, Function 0
  59 ///
  60 #define PchAzaliaPciCfg32(Register) \
  61   MmioRead32 ( \
  62   MmPciAddress (0, \
  63   DEFAULT_PCI_BUS_NUMBER_PCH, \
  64   PCI_DEVICE_NUMBER_PCH_AZALIA, \
  65   0, \
  66   Register) \
  67   )
  68
  69 #define PchAzaliaPciCfg32Or(Register, OrData) \
  70   MmioOr32 ( \
  71   MmPciAddress (0, \
  72   DEFAULT_PCI_BUS_NUMBER_PCH, \
  73   PCI_DEVICE_NUMBER_PCH_AZALIA, \
  74   0, \
  75   Register), \
  76   OrData \
  77   )
  78
  79 #define PchAzaliaPciCfg32And(Register, AndData) \
  80   MmioAnd32 ( \
  81   MmPciAddress (0, \
  82   DEFAULT_PCI_BUS_NUMBER_PCH, \
  83   PCI_DEVICE_NUMBER_PCH_AZALIA, \
  84   0, \
  85   Register), \
  86   AndData \
  87   )
  88
  89 #define PchAzaliaPciCfg32AndThenOr(Register, AndData, OrData) \
  90   MmioAndThenOr32 ( \
  91   MmPciAddress (0, \
  92   DEFAULT_PCI_BUS_NUMBER_PCH, \
  93   PCI_DEVICE_NUMBER_PCH_AZALIA, \
  94   0, \
  95   Register), \
  96   OrData \
  97   )
  98
  99 #define PchAzaliaPciCfg16(Register) \
 100   MmioRead16 ( \
 101   MmPciAddress (0, \
 102   DEFAULT_PCI_BUS_NUMBER_PCH, \
 103   PCI_DEVICE_NUMBER_PCH_AZALIA, \
 104   0, \
 105   Register) \
 106   )
 107
 108 #define PchAzaliaPciCfg16Or(Register, OrData) \
 109   MmioOr16 ( \
 110   MmPciAddress (0, \
 111   DEFAULT_PCI_BUS_NUMBER_PCH, \
 112   PCI_DEVICE_NUMBER_PCH_AZALIA, \
 113   0, \
 114   Register), \
 115   OrData \
 116   )
 117
 118 #define PchAzaliaPciCfg16And(Register, AndData) \
 119   MmioAnd16 ( \
 120   MmPciAddress (0, \
 121   DEFAULT_PCI_BUS_NUMBER_PCH, \
 122   PCI_DEVICE_NUMBER_PCH_AZALIA, \
 123   0, \
 124   Register), \
 125   AndData \
 126   )
 127
 128 #define PchAzaliaPciCfg16AndThenOr(Register, AndData, OrData) \
 129   MmioAndThenOr16 ( \
 130   MmPciAddress (0, \
 131   DEFAULT_PCI_BUS_NUMBER_PCH, \
 132   PCI_DEVICE_NUMBER_PCH_AZALIA, \
 133   0, \
 134   Register), \
 135   AndData, \
 136   OrData \
 137   )
 138
 139 #define PchAzaliaPciCfg8(Register)  MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_AZALIA, 0, Register))
 140
 141 #define PchAzaliaPciCfg8Or(Register, OrData) \
 142   MmioOr8 ( \
 143   MmPciAddress (0, \
 144   DEFAULT_PCI_BUS_NUMBER_PCH, \
 145   PCI_DEVICE_NUMBER_PCH_AZALIA, \
 146   0, \
 147   Register), \
 148   OrData \
 149   )
 150
 151 #define PchAzaliaPciCfg8And(Register, AndData) \
 152   MmioAnd8 ( \
 153   MmPciAddress (0, \
 154   DEFAULT_PCI_BUS_NUMBER_PCH, \
 155   PCI_DEVICE_NUMBER_PCH_AZALIA, \
 156   0, \
 157   Register), \
 158   AndData \
 159   )
 160
 161 #define PchAzaliaPciCfg8AndThenOr(Register, AndData, OrData) \
 162   MmioAndThenOr8 ( \
 163   MmPciAddress (0, \
 164   DEFAULT_PCI_BUS_NUMBER_PCH, \
 165   PCI_DEVICE_NUMBER_PCH_AZALIA, \
 166   0, \
 167   Register), \
 168   AndData, \
 169   OrData \
 170   )
 171
 172 ///
 173 /// Device 0x1f, Function 0
 174 ///
 175 #define PchLpcPciCfg32(Register)  MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
 176
 177 #define PchLpcMmioOr32 (Register, OrData) \
 178   MmioOr32 ( \
 179   MmPciAddress (0, \
 180   DEFAULT_PCI_BUS_NUMBER_PCH, \
 181   PCI_DEVICE_NUMBER_PCH_LPC, \
 182   0, \
 183   Register), \
 184   OrData \
 185   )
 186
 187 #define PchLpcPciCfg32And(Register, AndData) \
 188   MmioAnd32 ( \
 189   MmPciAddress (0, \
 190   DEFAULT_PCI_BUS_NUMBER_PCH, \
 191   PCI_DEVICE_NUMBER_PCH_LPC, \
 192   0, \
 193   Register), \
 194   AndData \
 195   )
 196
 197 #define PchLpcPciCfg32AndThenOr(Register, AndData, OrData) \
 198   MmioAndThenOr32 ( \
 199   MmPciAddress (0, \
 200   DEFAULT_PCI_BUS_NUMBER_PCH, \
 201   PCI_DEVICE_NUMBER_PCH_LPC, \
 202   0, \
 203   Register), \
 204   AndData, \
 205   OrData \
 206   )
 207
 208 #define PchLpcPciCfg16(Register)  MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
 209
 210 #define PchLpcPciCfg16Or(Register, OrData) \
 211   MmioOr16 ( \
 212   MmPciAddress (0, \
 213   DEFAULT_PCI_BUS_NUMBER_PCH, \
 214   PCI_DEVICE_NUMBER_PCH_LPC, \
 215   0, \
 216   Register), \
 217   OrData \
 218   )
 219
 220 #define PchLpcPciCfg16And(Register, AndData) \
 221   MmioAndThenOr16 ( \
 222   MmPciAddress (0, \
 223   DEFAULT_PCI_BUS_NUMBER_PCH, \
 224   PCI_DEVICE_NUMBER_PCH_LPC, \
 225   0, \
 226   Register), \
 227   AndData \
 228   )
 229
 230 #define PchLpcPciCfg16AndThenOr(Register, AndData, OrData) \
 231   MmioAndThenOr16 ( \
 232   MmPciAddress (0, \
 233   DEFAULT_PCI_BUS_NUMBER_PCH, \
 234   PCI_DEVICE_NUMBER_PCH_LPC, \
 235   0, \
 236   Register), \
 237   AndData, \
 238   OrData \
 239   )
 240
 241 #define PchLpcPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
 242
 243 #define PchLpcPciCfg8Or(Register, OrData) \
 244   MmioOr8 ( \
 245   MmPciAddress (0, \
 246   DEFAULT_PCI_BUS_NUMBER_PCH, \
 247   PCI_DEVICE_NUMBER_PCH_LPC, \
 248   0, \
 249   Register), \
 250   OrData \
 251   )
 252
 253 #define PchLpcPciCfg8And(Register, AndData) \
 254   MmioAnd8 ( \
 255   MmPciAddress (0, \
 256   DEFAULT_PCI_BUS_NUMBER_PCH, \
 257   PCI_DEVICE_NUMBER_PCH_LPC, \
 258   0, \
 259   Register), \
 260   AndData \
 261   )
 262
 263 #define PchLpcPciCfg8AndThenOr(Register, AndData, OrData) \
 264   MmioAndThenOr8 ( \
 265   MmPciAddress (0, \
 266   DEFAULT_PCI_BUS_NUMBER_PCH, \
 267   PCI_DEVICE_NUMBER_PCH_LPC, \
 268   0, \
 269   Register), \
 270   AndData, \
 271   OrData \
 272   )
 273
 274
 275 ///
 276 /// SATA device 0x13, Function 0
 277 ///
 278 #define PchSataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
 279
 280 #define PchSataPciCfg32Or(Register, OrData) \
 281   MmioOr32 ( \
 282   MmPciAddress (0, \
 283   DEFAULT_PCI_BUS_NUMBER_PCH, \
 284   PCI_DEVICE_NUMBER_PCH_SATA, \
 285   PCI_FUNCTION_NUMBER_PCH_SATA, \
 286   Register), \
 287   OrData \
 288   )
 289
 290 #define PchSataPciCfg32And(Register, AndData) \
 291   MmioAnd32 ( \
 292   MmPciAddress (0, \
 293   DEFAULT_PCI_BUS_NUMBER_PCH, \
 294   PCI_DEVICE_NUMBER_PCH_SATA, \
 295   PCI_FUNCTION_NUMBER_PCH_SATA, \
 296   Register), \
 297   AndData \
 298   )
 299
 300 #define PchSataPciCfg32AndThenOr(Register, AndData, OrData) \
 301   MmioAndThenOr32 ( \
 302   MmPciAddress (0, \
 303   DEFAULT_PCI_BUS_NUMBER_PCH, \
 304   PCI_DEVICE_NUMBER_PCH_SATA, \
 305   PCI_FUNCTION_NUMBER_PCH_SATA, \
 306   Register), \
 307   AndData, \
 308   OrData \
 309   )
 310
 311 #define PchSataPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
 312
 313 #define PchSataPciCfg16Or(Register, OrData) \
 314   MmioOr16 ( \
 315   MmPciAddress (0, \
 316   DEFAULT_PCI_BUS_NUMBER_PCH, \
 317   PCI_DEVICE_NUMBER_PCH_SATA, \
 318   PCI_FUNCTION_NUMBER_PCH_SATA, \
 319   Register), \
 320   OrData \
 321   )
 322
 323 #define PchSataPciCfg16And(Register, AndData) \
 324   MmioAndThenOr16 ( \
 325   MmPciAddress (0, \
 326   DEFAULT_PCI_BUS_NUMBER_PCH, \
 327   PCI_DEVICE_NUMBER_PCH_SATA, \
 328   PCI_FUNCTION_NUMBER_PCH_SATA, \
 329   Register), \
 330   AndData \
 331   )
 332
 333 #define PchSataPciCfg16AndThenOr(Register, AndData, OrData) \
 334   MmioAndThenOr16 ( \
 335   MmPciAddress (0, \
 336   DEFAULT_PCI_BUS_NUMBER_PCH, \
 337   PCI_DEVICE_NUMBER_PCH_SATA, \
 338   PCI_FUNCTION_NUMBER_PCH_SATA, \
 339   Register), \
 340   AndData, \
 341   OrData \
 342   )
 343
 344 #define PchSataPciCfg8(Register)  MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
 345
 346 #define PchSataPciCfg8Or(Register, OrData) \
 347   MmioOr8 ( \
 348   MmPciAddress (0, \
 349   DEFAULT_PCI_BUS_NUMBER_PCH, \
 350   PCI_DEVICE_NUMBER_PCH_SATA, \
 351   PCI_FUNCTION_NUMBER_PCH_SATA, \
 352   Register), \
 353   OrData \
 354   )
 355
 356 #define PchSataPciCfg8And(Register, AndData) \
 357   MmioAnd8 ( \
 358   MmPciAddress (0, \
 359   DEFAULT_PCI_BUS_NUMBER_PCH, \
 360   PCI_DEVICE_NUMBER_PCH_SATA, \
 361   PCI_FUNCTION_NUMBER_PCH_SATA, \
 362   Register), \
 363   AndData \
 364   )
 365
 366 #define PchSataPciCfg8AndThenOr(Register, AndData, OrData) \
 367   MmioAndThenOr8 ( \
 368   MmPciAddress (0, \
 369   DEFAULT_PCI_BUS_NUMBER_PCH, \
 370   PCI_DEVICE_NUMBER_PCH_SATA, \
 371   PCI_FUNCTION_NUMBER_PCH_SATA, \
 372   Register), \
 373   AndData, \
 374   OrData \
 375   )
 376
 377
 378 ///
 379 /// Root Complex Register Block
 380 ///
 381 #define PchMmRcrb32(Register)                           MmioRead32 (PCH_RCRB_BASE + Register)
 382
 383 #define PchMmRcrb32Or(Register, OrData)                 MmioOr32 (PCH_RCRB_BASE + Register, OrData)
 384
 385 #define PchMmRcrb32And(Register, AndData)               MmioAnd32 (PCH_RCRB_BASE + Register, AndData)
 386
 387 #define PchMmRcrb32AndThenOr(Register, AndData, OrData) MmioAndThenOr32 (PCH_RCRB_BASE + Register, AndData, OrData)
 388
 389 #define PchMmRcrb16(Register)                           MmioRead16 (PCH_RCRB_BASE + Register)
 390
 391 #define PchMmRcrb16Or(Register, OrData)                 MmioOr16 (PCH_RCRB_BASE + Register, OrData)
 392
 393 #define PchMmRcrb16And(Register, AndData)               MmioAnd16 (PCH_RCRB_BASE + Register, AndData)
 394
 395 #define PchMmRcrb16AndThenOr(Register, AndData, OrData) MmioAndThenOr16 (PCH_RCRB_BASE + Register, AndData, OrData)
 396
 397 #define PchMmRcrb8(Register)                            MmioRead8 (PCH_RCRB_BASE + Register)
 398
 399 #define PchMmRcrb8Or(Register, OrData)                  MmioOr8 (PCH_RCRB_BASE + Register, OrData)
 400
 401 #define PchMmRcrb8And(Register, AndData)                MmioAnd8 (PCH_RCRB_BASE + Register, AndData)
 402
 403 #define PchMmRcrb8AndThenOr(Register, AndData, OrData)  MmioAndThenOr8 (PCH_RCRB_BASE + Register, AndData, OrData)
 404
 405
 406 ///
 407 /// Message Bus
 408 ///
 409
 410 ///
 411 /// Message Bus Registers
 412 ///
 413 #define MC_MCR            0x000000D0 // Cunit Message Control Register
 414 #define MC_MDR            0x000000D4 // Cunit Message Data Register
 415 #define MC_MCRX           0x000000D8 // Cunit Message Control Register Extension
 416
 417 ///
 418 /// Message Bus API
 419 ///
 420 #define MSG_BUS_ENABLED   0x000000F0
 421 #define MSGBUS_MASKHI     0xFFFFFF00
 422 #define MSGBUS_MASKLO     0x000000FF
 423 #define MESSAGE_DWORD_EN  BIT4 | BIT5 | BIT6 | BIT7
 424
 425 #define PchMsgBusRead32(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \
 426 { \
 427   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
 428   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
 429   (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
 430 }
 431
 432 #define PchMsgBusAnd32(PortId, Register, Dbuff, AndData, ReadOpCode, WriteOpCode) \
 433 { \
 434   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
 435   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
 436   (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
 437   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
 438   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff & AndData)); \
 439   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
 440 }
 441
 442 #define PchMsgBusOr32(PortId, Register, Dbuff, OrData, ReadOpCode, WriteOpCode) \
 443 { \
 444   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
 445   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
 446   (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
 447   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
 448   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff | OrData)); \
 449   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
 450 }
 451
 452 #define PchMsgBusAndThenOr32(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \
 453 { \
 454   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
 455   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
 456   (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
 457   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
 458   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \
 459   MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
 460 }
 461
 462 typedef struct _PCH_MSG_BUS_TABLE_STRUCT {
 463   UINT32      PortId;
 464   UINT32      Address;
 465   UINT32      AndMask;
 466   UINT32      OrMask;
 467   UINT32      ReadOpCode;
 468   UINT32      WriteOpCode;
 469 } PCH_MSG_BUS_TABLE_STRUCT_TABLE_STRUCT;
 470
 471 #endif