Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchCommonDefinitions.h

   1 /*++
   2
   3 Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9 Module Name:
  10
  11   PchCommonDefinitions.h
  12
  13 Abstract:
  14
  15   This header file provides common definitions for PCH
  16
  17 --*/
  18 #ifndef _PCH_COMMON_DEFINITIONS_H_
  19 #define _PCH_COMMON_DEFINITIONS_H_
  20
  21 //
  22 //  MMIO access macros
  23 //
  24 #define PchMmioAddress(BaseAddr, Register)  ((UINTN) BaseAddr + (UINTN) (Register))
  25
  26 //
  27 // 32 bit MMIO access
  28 //
  29 #define PchMmio32Ptr(BaseAddr, Register)  ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register))
  30
  31 #define PchMmio32(BaseAddr, Register)     *PchMmio32Ptr (BaseAddr, Register)
  32
  33 #define PchMmio32Or(BaseAddr, Register, OrData) \
  34   PchMmio32 (BaseAddr, Register) = (UINT32) \
  35     (PchMmio32 (BaseAddr, Register) | (UINT32) (OrData))
  36
  37 #define PchMmio32And(BaseAddr, Register, AndData) \
  38   PchMmio32 (BaseAddr, Register) = (UINT32) \
  39     (PchMmio32 (BaseAddr, Register) & (UINT32) (AndData))
  40
  41 #define PchMmio32AndThenOr(BaseAddr, Register, AndData, OrData) \
  42   PchMmio32 (BaseAddr, Register) = (UINT32) \
  43     ((PchMmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
  44
  45 //
  46 // 16 bit MMIO access
  47 //
  48 #define PchMmio16Ptr(BaseAddr, Register)  ((volatile UINT16 *) PchMmioAddress (BaseAddr, Register))
  49
  50 #define PchMmio16(BaseAddr, Register)     *PchMmio16Ptr (BaseAddr, Register)
  51
  52 #define PchMmio16Or(BaseAddr, Register, OrData) \
  53   PchMmio16 (BaseAddr, Register) = (UINT16) \
  54     (PchMmio16 (BaseAddr, Register) | (UINT16) (OrData))
  55
  56 #define PchMmio16And(BaseAddr, Register, AndData) \
  57   PchMmio16 (BaseAddr, Register) = (UINT16) \
  58     (PchMmio16 (BaseAddr, Register) & (UINT16) (AndData))
  59
  60 #define PchMmio16AndThenOr(BaseAddr, Register, AndData, OrData) \
  61   PchMmio16 (BaseAddr, Register) = (UINT16) \
  62     ((PchMmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
  63
  64 //
  65 // 8 bit MMIO access
  66 //
  67 #define PchMmio8Ptr(BaseAddr, Register) ((volatile UINT8 *) PchMmioAddress (BaseAddr, Register))
  68
  69 #define PchMmio8(BaseAddr, Register)    *PchMmio8Ptr (BaseAddr, Register)
  70
  71 #define PchMmio8Or(BaseAddr, Register, OrData) \
  72   PchMmio8 (BaseAddr, Register) = (UINT8) \
  73     (PchMmio8 (BaseAddr, Register) | (UINT8) (OrData))
  74
  75 #define PchMmio8And(BaseAddr, Register, AndData) \
  76   PchMmio8 (BaseAddr, Register) = (UINT8) \
  77     (PchMmio8 (BaseAddr, Register) & (UINT8) (AndData))
  78
  79 #define PchMmio8AndThenOr(BaseAddr, Register, AndData, OrData) \
  80   PchMmio8 (BaseAddr, Register) = (UINT8) \
  81     ((PchMmio8 (BaseAddr, Register) & (UINT8) (AndData)) | (UINT8) (OrData))
  82
  83 //
  84 // Memory Mapped PCI Access macros
  85 //
  86 #define PCH_PCI_EXPRESS_BASE_ADDRESS  0xE0000000
  87 //
  88 // PCI Device MM Base
  89 //
  90 #define PchPciDeviceMmBase(Bus, Device, Function) \
  91     ( \
  92       (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \
  93         (Function << 12) \
  94     )
  95
  96 //
  97 // PCI Device MM Address
  98 //
  99 #define PchPciDeviceMmAddress(Segment, Bus, Device, Function, Register) \
 100     ( \
 101       (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \
 102         (Function << 12) + (UINTN) (Register) \
 103     )
 104
 105 //
 106 // 32 bit PCI access
 107 //
 108 #define PchMmPci32Ptr(Segment, Bus, Device, Function, Register) \
 109     ((volatile UINT32 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
 110
 111 #define PchMmPci32(Segment, Bus, Device, Function, Register)  *PchMmPci32Ptr (Segment, Bus, Device, Function, Register)
 112
 113 #define PchMmPci32Or(Segment, Bus, Device, Function, Register, OrData) \
 114   PchMmPci32 ( \
 115   Segment, \
 116   Bus, \
 117   Device, \
 118   Function, \
 119   Register \
 120   ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) | (UINT32) (OrData))
 121
 122 #define PchMmPci32And(Segment, Bus, Device, Function, Register, AndData) \
 123   PchMmPci32 ( \
 124   Segment, \
 125   Bus, \
 126   Device, \
 127   Function, \
 128   Register \
 129   ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData))
 130
 131 #define PchMmPci32AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
 132   PchMmPci32 ( \
 133   Segment, \
 134   Bus, \
 135   Device, \
 136   Function, \
 137   Register \
 138   ) = (UINT32) ((PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
 139
 140 //
 141 // 16 bit PCI access
 142 //
 143 #define PchMmPci16Ptr(Segment, Bus, Device, Function, Register) \
 144     ((volatile UINT16 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
 145
 146 #define PchMmPci16(Segment, Bus, Device, Function, Register)  *PchMmPci16Ptr (Segment, Bus, Device, Function, Register)
 147
 148 #define PchMmPci16Or(Segment, Bus, Device, Function, Register, OrData) \
 149   PchMmPci16 ( \
 150   Segment, \
 151   Bus, \
 152   Device, \
 153   Function, \
 154   Register \
 155   ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) | (UINT16) (OrData))
 156
 157 #define PchMmPci16And(Segment, Bus, Device, Function, Register, AndData) \
 158   PchMmPci16 ( \
 159   Segment, \
 160   Bus, \
 161   Device, \
 162   Function, \
 163   Register \
 164   ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData))
 165
 166 #define PchMmPci16AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
 167   PchMmPci16 ( \
 168   Segment, \
 169   Bus, \
 170   Device, \
 171   Function, \
 172   Register \
 173   ) = (UINT16) ((PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
 174
 175 //
 176 // 8 bit PCI access
 177 //
 178 #define PchMmPci8Ptr(Segment, Bus, Device, Function, Register) \
 179     ((volatile UINT8 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
 180
 181 #define PchMmPci8(Segment, Bus, Device, Function, Register) *PchMmPci8Ptr (Segment, Bus, Device, Function, Register)
 182
 183 #define PchMmPci8Or(Segment, Bus, Device, Function, Register, OrData) \
 184   PchMmPci8 ( \
 185   Segment, \
 186   Bus, \
 187   Device, \
 188   Function, \
 189   Register \
 190   ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) | (UINT8) (OrData))
 191
 192 #define PchMmPci8And(Segment, Bus, Device, Function, Register, AndData) \
 193   PchMmPci8 ( \
 194   Segment, \
 195   Bus, \
 196   Device, \
 197   Function, \
 198   Register \
 199   ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData))
 200
 201 #define PchMmPci8AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
 202   PchMmPci8 ( \
 203   Segment, \
 204   Bus, \
 205   Device, \
 206   Function, \
 207   Register \
 208   ) = (UINT8) ((PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) | (UINT8) (OrData))
 209
 210 #endif