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git.proxmox.com Git - mirror_edk2.git/blob - Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsLpss.h
3 Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
5 SPDX-License-Identifier: BSD-2-Clause-Patent
15 Register names for VLV Low Input Output (LPSS) module.
20 Definitions beginning with "R_" are registers
21 Definitions beginning with "B_" are bits within registers
22 Definitions beginning with "V_" are meaningful values of bits within the registers
23 Definitions beginning with "S_" are register sizes
24 Definitions beginning with "N_" are the bit position
25 - In general, PCH registers are denoted by "_PCH_" in register names
26 - Registers / bits that are different between PCH generations are denoted by
27 "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
28 - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
29 at the end of the register/bit names
30 - Registers / bits of new devices introduced in a PCH generation will be just named
31 as "_PCH_" without <generation_name> inserted.
34 #ifndef _PCH_REGS_LPSS_H_
35 #define _PCH_REGS_LPSS_H_
39 // Low Power Input Output (LPSS) Module Registers
44 // PCI Config Space Registers
46 #define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0 30
47 #define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1 24
48 #define PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC 0
50 #define R_PCH_LPSS_DMAC_DEVVENDID 0x00 // Device ID & Vendor ID
51 #define B_PCH_LPSS_DMAC_DEVVENDID_DID 0xFFFF0000 // Device ID
52 #define B_PCH_LPSS_DMAC_DEVVENDID_VID 0x0000FFFF // Vendor ID
54 #define R_PCH_LPSS_DMAC_STSCMD 0x04 // Status & Command
55 #define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // RMA
56 #define B_PCH_LPSS_DMAC_STSCMD_RCA BIT28 // RCA
57 #define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List
58 #define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status
59 #define B_PCH_LPSS_DMAC_STSCMD_INTRDIS BIT10 // Interrupt Disable
60 #define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable
61 #define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable
62 #define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable
64 #define R_PCH_LPSS_DMAC_REVCC 0x08 // Revision ID & Class Code
65 #define B_PCH_LPSS_DMAC_REVCC_CC 0xFFFFFF00 // Class Code
66 #define B_PCH_LPSS_DMAC_REVCC_RID 0x000000FF // Revision ID
68 #define R_PCH_LPSS_DMAC_CLHB 0x0C
69 #define B_PCH_LPSS_DMAC_CLHB_MULFNDEV BIT23
70 #define B_PCH_LPSS_DMAC_CLHB_HT 0x007F0000 // Header Type
71 #define B_PCH_LPSS_DMAC_CLHB_LT 0x0000FF00 // Latency Timer
72 #define B_PCH_LPSS_DMAC_CLHB_CLS 0x000000FF // Cache Line Size
74 #define R_PCH_LPSS_DMAC_BAR 0x10 // BAR
75 #define B_PCH_LPSS_DMAC_BAR_BA 0xFFFFC000 // Base Address
76 #define V_PCH_LPSS_DMAC_BAR_SIZE 0x4000
77 #define N_PCH_LPSS_DMAC_BAR_ALIGNMENT 14
78 #define B_PCH_LPSS_DMAC_BAR_SI 0x00000FF0 // Size Indicator
79 #define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable
80 #define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type
81 #define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space
83 #define R_PCH_LPSS_DMAC_BAR1 0x14 // BAR 1
84 #define B_PCH_LPSS_DMAC_BAR1_BA 0xFFFFF000 // Base Address
85 #define B_PCH_LPSS_DMAC_BAR1_SI 0x00000FF0 // Size Indicator
86 #define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable
87 #define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type
88 #define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space
90 #define R_PCH_LPSS_DMAC_SSID 0x2C // Sub System ID
91 #define B_PCH_LPSS_DMAC_SSID_SID 0xFFFF0000 // Sub System ID
92 #define B_PCH_LPSS_DMAC_SSID_SVID 0x0000FFFF // Sub System Vendor ID
94 #define R_PCH_LPSS_DMAC_ERBAR 0x30 // Expansion ROM BAR
95 #define B_PCH_LPSS_DMAC_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
97 #define R_PCH_LPSS_DMAC_CAPPTR 0x34 // Capability Pointer
98 #define B_PCH_LPSS_DMAC_CAPPTR_CPPWR 0xFF // Capability Pointer Power
100 #define R_PCH_LPSS_DMAC_INTR 0x3C // Interrupt
101 #define B_PCH_LPSS_DMAC_INTR_ML 0xFF000000 // Max Latency
102 #define B_PCH_LPSS_DMAC_INTR_MG 0x00FF0000
103 #define B_PCH_LPSS_DMAC_INTR_IP 0x00000F00 // Interrupt Pin
104 #define B_PCH_LPSS_DMAC_INTR_IL 0x000000FF // Interrupt Line
106 #define R_PCH_LPSS_DMAC_PCAPID 0x80 // Power Capability ID
107 #define B_PCH_LPSS_DMAC_PCAPID_PS 0xF8000000 // PME Support
108 #define B_PCH_LPSS_DMAC_PCAPID_VS 0x00070000 // Version
109 #define B_PCH_LPSS_DMAC_PCAPID_NC 0x0000FF00 // Next Capability
110 #define B_PCH_LPSS_DMAC_PCAPID_PC 0x000000FF // Power Capability
112 #define R_PCH_LPSS_DMAC_PCS 0x84 // PME Control Status
113 #define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status
114 #define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable
115 #define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset
116 #define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State
118 #define R_PCH_LPSS_DMAC_MANID 0xF8 // Manufacturer ID
119 #define B_PCH_LPSS_DMAC_MANID_MANID 0xFFFFFFFF // Manufacturer ID
124 // PCI Config Space Registers
126 #define PCI_DEVICE_NUMBER_PCH_LPSS_I2C 24
127 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0 1
128 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1 2
129 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2 3
130 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3 4
131 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4 5
132 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5 6
133 #define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6 7
135 #define R_PCH_LPSS_I2C_DEVVENDID 0x00 // Device ID & Vendor ID
136 #define B_PCH_LPSS_I2C_DEVVENDID_DID 0xFFFF0000 // Device ID
137 #define B_PCH_LPSS_I2C_DEVVENDID_VID 0x0000FFFF // Vendor ID
139 #define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command
140 #define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA
141 #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
142 #define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
143 #define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status
144 #define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable
145 #define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable
146 #define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
147 #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable
149 #define R_PCH_LPSS_I2C_REVCC 0x08 // Revision ID & Class Code
150 #define B_PCH_LPSS_I2C_REVCC_CC 0xFFFFFF00 // Class Code
151 #define B_PCH_LPSS_I2C_REVCC_RID 0x000000FF // Revision ID
153 #define R_PCH_LPSS_I2C_CLHB 0x0C
154 #define B_PCH_LPSS_I2C_CLHB_MULFNDEV BIT23
155 #define B_PCH_LPSS_I2C_CLHB_HT 0x007F0000 // Header Type
156 #define B_PCH_LPSS_I2C_CLHB_LT 0x0000FF00 // Latency Timer
157 #define B_PCH_LPSS_I2C_CLHB_CLS 0x000000FF // Cache Line Size
159 #define R_PCH_LPSS_I2C_BAR 0x10 // BAR
160 #define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address
161 #define V_PCH_LPSS_I2C_BAR_SIZE 0x1000
162 #define N_PCH_LPSS_I2C_BAR_ALIGNMENT 12
163 #define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator
164 #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable
165 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
166 #define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space
168 #define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1
169 #define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address
170 #define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator
171 #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable
172 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
173 #define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space
175 #define R_PCH_LPSS_I2C_SSID 0x2C // Sub System ID
176 #define B_PCH_LPSS_I2C_SSID_SID 0xFFFF0000 // Sub System ID
177 #define B_PCH_LPSS_I2C_SSID_SVID 0x0000FFFF // Sub System Vendor ID
179 #define R_PCH_LPSS_I2C_ERBAR 0x30 // Expansion ROM BAR
180 #define B_PCH_LPSS_I2C_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
182 #define R_PCH_LPSS_I2C_CAPPTR 0x34 // Capability Pointer
183 #define B_PCH_LPSS_I2C_CAPPTR_CPPWR 0xFF // Capability Pointer Power
185 #define R_PCH_LPSS_I2C_INTR 0x3C // Interrupt
186 #define B_PCH_LPSS_I2C_INTR_ML 0xFF000000 // Max Latency
187 #define B_PCH_LPSS_I2C_INTR_MG 0x00FF0000
188 #define B_PCH_LPSS_I2C_INTR_IP 0x00000F00 // Interrupt Pin
189 #define B_PCH_LPSS_I2C_INTR_IL 0x000000FF // Interrupt Line
191 #define R_PCH_LPSS_I2C_PCAPID 0x80 // Power Capability ID
192 #define B_PCH_LPSS_I2C_PCAPID_PS 0xF8000000 // PME Support
193 #define B_PCH_LPSS_I2C_PCAPID_VS 0x00070000 // Version
194 #define B_PCH_LPSS_I2C_PCAPID_NC 0x0000FF00 // Next Capability
195 #define B_PCH_LPSS_I2C_PCAPID_PC 0x000000FF // Power Capability
197 #define R_PCH_LPSS_I2C_PCS 0x84 // PME Control Status
198 #define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status
199 #define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable
200 #define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset
201 #define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State
203 #define R_PCH_LPSS_I2C_MANID 0xF8 // Manufacturer ID
204 #define B_PCH_LPSS_I2C_MANID_MANID 0xFFFFFFFF // Manufacturer ID
208 // Memory Space Registers
210 #define R_PCH_LPSS_I2C_MEM_RESETS 0x804 // Software Reset
211 #define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
212 #define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
216 // PCI Config Space Registers
218 #define PCI_DEVICE_NUMBER_PCH_LPSS_PWM 30
219 #define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0 1
220 #define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1 2
222 #define R_PCH_LPSS_PWM_DEVVENDID 0x00 // Device ID & Vendor ID
223 #define B_PCH_LPSS_PWM_DEVVENDID_DID 0xFFFF0000 // Device ID
224 #define B_PCH_LPSS_PWM_DEVVENDID_VID 0x0000FFFF // Vendor ID
226 #define R_PCH_LPSS_PWM_STSCMD 0x04 // Status & Command
227 #define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // RMA
228 #define B_PCH_LPSS_PWM_STSCMD_RCA BIT28 // RCA
229 #define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List
230 #define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status
231 #define B_PCH_LPSS_PWM_STSCMD_INTRDIS BIT10 // Interrupt Disable
232 #define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable
233 #define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable
234 #define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable
236 #define R_PCH_LPSS_PWM_REVCC 0x08 // Revision ID & Class Code
237 #define B_PCH_LPSS_PWM_REVCC_CC 0xFFFFFF00 // Class Code
238 #define B_PCH_LPSS_PWM_REVCC_RID 0x000000FF // Revision ID
240 #define R_PCH_LPSS_PWM_CLHB 0x0C
241 #define B_PCH_LPSS_PWM_CLHB_MULFNDEV BIT23
242 #define B_PCH_LPSS_PWM_CLHB_HT 0x007F0000 // Header Type
243 #define B_PCH_LPSS_PWM_CLHB_LT 0x0000FF00 // Latency Timer
244 #define B_PCH_LPSS_PWM_CLHB_CLS 0x000000FF // Cache Line Size
246 #define R_PCH_LPSS_PWM_BAR 0x10 // BAR
247 #define B_PCH_LPSS_PWM_BAR_BA 0xFFFFF000 // Base Address
248 #define V_PCH_LPSS_PWM_BAR_SIZE 0x1000
249 #define N_PCH_LPSS_PWM_BAR_ALIGNMENT 12
250 #define B_PCH_LPSS_PWM_BAR_SI 0x00000FF0 // Size Indicator
251 #define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable
252 #define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type
253 #define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space
255 #define R_PCH_LPSS_PWM_BAR1 0x14 // BAR 1
256 #define B_PCH_LPSS_PWM_BAR1_BA 0xFFFFF000 // Base Address
257 #define B_PCH_LPSS_PWM_BAR1_SI 0x00000FF0 // Size Indicator
258 #define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable
259 #define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type
260 #define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space
262 #define R_PCH_LPSS_PWM_SSID 0x2C // Sub System ID
263 #define B_PCH_LPSS_PWM_SSID_SID 0xFFFF0000 // Sub System ID
264 #define B_PCH_LPSS_PWM_SSID_SVID 0x0000FFFF // Sub System Vendor ID
266 #define R_PCH_LPSS_PWM_ERBAR 0x30 // Expansion ROM BAR
267 #define B_PCH_LPSS_PWM_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
269 #define R_PCH_LPSS_PWM_CAPPTR 0x34 // Capability Pointer
270 #define B_PCH_LPSS_PWM_CAPPTR_CPPWR 0xFF // Capability Pointer Power
272 #define R_PCH_LPSS_PWM_INTR 0x3C // Interrupt
273 #define B_PCH_LPSS_PWM_INTR_ML 0xFF000000 // Max Latency
274 #define B_PCH_LPSS_PWM_INTR_MG 0x00FF0000
275 #define B_PCH_LPSS_PWM_INTR_IP 0x00000F00 // Interrupt Pin
276 #define B_PCH_LPSS_PWM_INTR_IL 0x000000FF // Interrupt Line
278 #define R_PCH_LPSS_PWM_PCAPID 0x80 // Power Capability ID
279 #define B_PCH_LPSS_PWM_PCAPID_PS 0xF8000000 // PME Support
280 #define B_PCH_LPSS_PWM_PCAPID_VS 0x00070000 // Version
281 #define B_PCH_LPSS_PWM_PCAPID_NC 0x0000FF00 // Next Capability
282 #define B_PCH_LPSS_PWM_PCAPID_PC 0x000000FF // Power Capability
284 #define R_PCH_LPSS_PWM_PCS 0x84 // PME Control Status
285 #define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status
286 #define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable
287 #define B_PCH_LPSS_PWM_PCS_NSS BIT3 // No Soft Reset
288 #define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State
290 #define R_PCH_LPSS_PWM_MANID 0xF8 // Manufacturer ID
291 #define B_PCH_LPSS_PWM_MANID_MANID 0xFFFFFFFF // Manufacturer ID
295 // Memory Space Registers
297 #define R_PCH_LPSS_PWM_MEM_RESETS 0x804 // Software Reset
298 #define B_PCH_LPSS_PWM_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
299 #define B_PCH_LPSS_PWM_MEM_RESETS_APB BIT0 // APB Domain Reset
302 // LPSS HSUART Modules
303 // PCI Config Space Registers
305 #define PCI_DEVICE_NUMBER_PCH_LPSS_HSUART 30
306 #define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0 3
307 #define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1 4
309 #define R_PCH_LPSS_HSUART_DEVVENDID 0x00 // Device ID & Vendor ID
310 #define B_PCH_LPSS_HSUART_DEVVENDID_DID 0xFFFF0000 // Device ID
311 #define B_PCH_LPSS_HSUART_DEVVENDID_VID 0x0000FFFF // Vendor ID
313 #define R_PCH_LPSS_HSUART_STSCMD 0x04 // Status & Command
314 #define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // RMA
315 #define B_PCH_LPSS_HSUART_STSCMD_RCA BIT28 // RCA
316 #define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List
317 #define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status
318 #define B_PCH_LPSS_HSUART_STSCMD_INTRDIS BIT10 // Interrupt Disable
319 #define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable
320 #define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable
321 #define B_PCH_LPSS_HSUART_STSCMD_MSE BIT1 // Memory Space Enable
323 #define R_PCH_LPSS_HSUART_REVCC 0x08 // Revision ID & Class Code
324 #define B_PCH_LPSS_HSUART_REVCC_CC 0xFFFFFF00 // Class Code
325 #define B_PCH_LPSS_HSUART_REVCC_RID 0x000000FF // Revision ID
327 #define R_PCH_LPSS_HSUART_CLHB 0x0C
328 #define B_PCH_LPSS_HSUART_CLHB_MULFNDEV BIT23
329 #define B_PCH_LPSS_HSUART_CLHB_HT 0x007F0000 // Header Type
330 #define B_PCH_LPSS_HSUART_CLHB_LT 0x0000FF00 // Latency Timer
331 #define B_PCH_LPSS_HSUART_CLHB_CLS 0x000000FF // Cache Line Size
333 #define R_PCH_LPSS_HSUART_BAR 0x10 // BAR
334 #define B_PCH_LPSS_HSUART_BAR_BA 0xFFFFF000 // Base Address
335 #define V_PCH_LPSS_HSUART_BAR_SIZE 0x1000
336 #define N_PCH_LPSS_HSUART_BAR_ALIGNMENT 12
337 #define B_PCH_LPSS_HSUART_BAR_SI 0x00000FF0 // Size Indicator
338 #define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable
339 #define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type
340 #define B_PCH_LPSS_HSUART_BAR_MS BIT0 // Message Space
342 #define R_PCH_LPSS_HSUART_BAR1 0x14 // BAR 1
343 #define B_PCH_LPSS_HSUART_BAR1_BA 0xFFFFF000 // Base Address
344 #define B_PCH_LPSS_HSUART_BAR1_SI 0x00000FF0 // Size Indicator
345 #define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable
346 #define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type
347 #define B_PCH_LPSS_HSUART_BAR1_MS BIT0 // Message Space
349 #define R_PCH_LPSS_HSUART_SSID 0x2C // Sub System ID
350 #define B_PCH_LPSS_HSUART_SSID_SID 0xFFFF0000 // Sub System ID
351 #define B_PCH_LPSS_HSUART_SSID_SVID 0x0000FFFF // Sub System Vendor ID
353 #define R_PCH_LPSS_HSUART_ERBAR 0x30 // Expansion ROM BAR
354 #define B_PCH_LPSS_HSUART_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
356 #define R_PCH_LPSS_HSUART_CAPPTR 0x34 // Capability Pointer
357 #define B_PCH_LPSS_HSUART_CAPPTR_CPPWR 0xFF // Capability Pointer Power
359 #define R_PCH_LPSS_HSUART_INTR 0x3C // Interrupt
360 #define B_PCH_LPSS_HSUART_INTR_ML 0xFF000000 // Max Latency
361 #define B_PCH_LPSS_HSUART_INTR_MG 0x00FF0000
362 #define B_PCH_LPSS_HSUART_INTR_IP 0x00000F00 // Interrupt Pin
363 #define B_PCH_LPSS_HSUART_INTR_IL 0x000000FF // Interrupt Line
365 #define R_PCH_LPSS_HSUART_PCAPID 0x80 // Power Capability ID
366 #define B_PCH_LPSS_HSUART_PCAPID_PS 0xF8000000 // PME Support
367 #define B_PCH_LPSS_HSUART_PCAPID_VS 0x00070000 // Version
368 #define B_PCH_LPSS_HSUART_PCAPID_NC 0x0000FF00 // Next Capability
369 #define B_PCH_LPSS_HSUART_PCAPID_PC 0x000000FF // Power Capability
371 #define R_PCH_LPSS_HSUART_PCS 0x84 // PME Control Status
372 #define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status
373 #define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable
374 #define B_PCH_LPSS_HSUART_PCS_NSS BIT3 // No Soft Reset
375 #define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State
377 #define R_PCH_LPSS_HSUART_MANID 0xF8 // Manufacturer ID
378 #define B_PCH_LPSS_HSUART_MANID_MANID 0xFFFFFFFF // Manufacturer ID
381 // LPSS HSUART Module
382 // Memory Space Registers
384 #define R_PCH_LPSS_HSUART_MEM_PCP 0x800 // Private Clock Parameters
385 #define B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update
386 #define B_PCH_LPSS_HSUART_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider
387 #define B_PCH_LPSS_HSUART_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider
388 #define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN BIT0 // Clock Enable
390 #define R_PCH_LPSS_HSUART_MEM_RESETS 0x804 // Software Reset
391 #define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
392 #define B_PCH_LPSS_HSUART_MEM_RESETS_APB BIT0 // APB Domain Reset
396 // PCI Config Space Registers
398 #define PCI_DEVICE_NUMBER_PCH_LPSS_SPI 30
399 #define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI 5
401 #define R_PCH_LPSS_SPI_DEVVENDID 0x00 // Device ID & Vendor ID
402 #define B_PCH_LPSS_SPI_DEVVENDID_DID 0xFFFF0000 // Device ID
403 #define B_PCH_LPSS_SPI_DEVVENDID_VID 0x0000FFFF // Vendor ID
405 #define R_PCH_LPSS_SPI_STSCMD 0x04 // Status & Command
406 #define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // RMA
407 #define B_PCH_LPSS_SPI_STSCMD_RCA BIT28 // RCA
408 #define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List
409 #define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status
410 #define B_PCH_LPSS_SPI_STSCMD_INTRDIS BIT10 // Interrupt Disable
411 #define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable
412 #define B_PCH_LPSS_SPI_STSCMD_BME BIT2 // Bus Master Enable
413 #define B_PCH_LPSS_SPI_STSCMD_MSE BIT1 // Memory Space Enable
415 #define R_PCH_LPSS_SPI_REVCC 0x08 // Revision ID & Class Code
416 #define B_PCH_LPSS_SPI_REVCC_CC 0xFFFFFF00 // Class Code
417 #define B_PCH_LPSS_SPI_REVCC_RID 0x000000FF // Revision ID
419 #define R_PCH_LPSS_SPI_CLHB 0x0C
420 #define B_PCH_LPSS_SPI_CLHB_MULFNDEV BIT23
421 #define B_PCH_LPSS_SPI_CLHB_HT 0x007F0000 // Header Type
422 #define B_PCH_LPSS_SPI_CLHB_LT 0x0000FF00 // Latency Timer
423 #define B_PCH_LPSS_SPI_CLHB_CLS 0x000000FF // Cache Line Size
425 #define R_PCH_LPSS_SPI_BAR 0x10 // BAR
426 #define B_PCH_LPSS_SPI_BAR_BA 0xFFFFF000 // Base Address
427 #define V_PCH_LPSS_SPI_BAR_SIZE 0x1000
428 #define N_PCH_LPSS_SPI_BAR_ALIGNMENT 12
429 #define B_PCH_LPSS_SPI_BAR_SI 0x00000FF0 // Size Indicator
430 #define B_PCH_LPSS_SPI_BAR_PF BIT3 // Prefetchable
431 #define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type
432 #define B_PCH_LPSS_SPI_BAR_MS BIT0 // Message Space
434 #define R_PCH_LPSS_SPI_BAR1 0x14 // BAR 1
435 #define B_PCH_LPSS_SPI_BAR1_BA 0xFFFFF000 // Base Address
436 #define B_PCH_LPSS_SPI_BAR1_SI 0x00000FF0 // Size Indicator
437 #define B_PCH_LPSS_SPI_BAR1_PF BIT3 // Prefetchable
438 #define B_PCH_LPSS_SPI_BAR1_TYPE (BIT2 | BIT1) // Type
439 #define B_PCH_LPSS_SPI_BAR1_MS BIT0 // Message Space
441 #define R_PCH_LPSS_SPI_SSID 0x2C // Sub System ID
442 #define B_PCH_LPSS_SPI_SSID_SID 0xFFFF0000 // Sub System ID
443 #define B_PCH_LPSS_SPI_SSID_SVID 0x0000FFFF // Sub System Vendor ID
445 #define R_PCH_LPSS_SPI_ERBAR 0x30 // Expansion ROM BAR
446 #define B_PCH_LPSS_SPI_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address
448 #define R_PCH_LPSS_SPI_CAPPTR 0x34 // Capability Pointer
449 #define B_PCH_LPSS_SPI_CAPPTR_CPPWR 0xFF // Capability Pointer Power
451 #define R_PCH_LPSS_SPI_INTR 0x3C // Interrupt
452 #define B_PCH_LPSS_SPI_INTR_ML 0xFF000000 // Max Latency
453 #define B_PCH_LPSS_SPI_INTR_MG 0x00FF0000
454 #define B_PCH_LPSS_SPI_INTR_IP 0x00000F00 // Interrupt Pin
455 #define B_PCH_LPSS_SPI_INTR_IL 0x000000FF // Interrupt Line
457 #define R_PCH_LPSS_SPI_PCAPID 0x80 // Power Capability ID
458 #define B_PCH_LPSS_SPI_PCAPID_PS 0xF8000000 // PME Support
459 #define B_PCH_LPSS_SPI_PCAPID_VS 0x00070000 // Version
460 #define B_PCH_LPSS_SPI_PCAPID_NC 0x0000FF00 // Next Capability
461 #define B_PCH_LPSS_SPI_PCAPID_PC 0x000000FF // Power Capability
463 #define R_PCH_LPSS_SPI_PCS 0x84 // PME Control Status
464 #define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status
465 #define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable
466 #define B_PCH_LPSS_SPI_PCS_NSS BIT3 // No Soft Reset
467 #define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State
469 #define R_PCH_LPSS_SPI_MANID 0xF8 // Manufacturer ID
470 #define B_PCH_LPSS_SPI_MANID_MANID 0xFFFFFFFF // Manufacturer ID
474 // Memory Space Registers
476 #define R_PCH_LPSS_SPI_MEM_PCP 0x400 // Private Clock Parameters
477 #define B_PCH_LPSS_SPI_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update
478 #define B_PCH_LPSS_SPI_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider
479 #define B_PCH_LPSS_SPI_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider
480 #define B_PCH_LPSS_SPI_MEM_PCP_CLKEN BIT0 // Clock Enable
482 #define R_PCH_LPSS_SPI_MEM_RESETS 0x404 // Software Reset
483 #define B_PCH_LPSS_SPI_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
484 #define B_PCH_LPSS_SPI_MEM_RESETS_APB BIT0 // APB Domain Reset