Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h

   1 /**
   2
   3 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7
   8
   9   @file
  10   PchRegsPcie.h
  11
  12   @brief
  13   Register names for VLV PCI-E root port devices
  14
  15   Conventions:
  16
  17   - Prefixes:
  18     Definitions beginning with "R_" are registers
  19     Definitions beginning with "B_" are bits within registers
  20     Definitions beginning with "V_" are meaningful values of bits within the registers
  21     Definitions beginning with "S_" are register sizes
  22     Definitions beginning with "N_" are the bit position
  23   - In general, PCH registers are denoted by "_PCH_" in register names
  24   - Registers / bits that are different between PCH generations are denoted by
  25     "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
  26   - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
  27     at the end of the register/bit names
  28   - Registers / bits of new devices introduced in a PCH generation will be just named
  29     as "_PCH_" without <generation_name> inserted.
  30
  31 --*/
  32 #ifndef _PCH_REGS_PCIE_H_
  33 #define _PCH_REGS_PCIE_H_
  34
  35 #define PCH_PCIE_MAX_ROOT_PORTS                            4
  36
  37 ///
  38 /// VLV PCI Express Root Ports (D28:F0~F3)
  39 ///
  40 #define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS              28
  41 #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1           0
  42 #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2           1
  43 #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3           2
  44 #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4           3
  45
  46 #define R_PCH_PCIE_ID                                      0x00  // Identifiers
  47 #define B_PCH_PCIE_ID_DID                                  0xFFFF0000 // Device ID
  48 #define V_PCH_PCIE_DEVICE_ID_0                             0x0F48  // PCIE Root Port #1
  49 #define V_PCH_PCIE_DEVICE_ID_1                             0x0F4A  // PCIE Root Port #2
  50 #define V_PCH_PCIE_DEVICE_ID_2                             0x0F4C  // PCIE Root Port #3
  51 #define V_PCH_PCIE_DEVICE_ID_3                             0x0F4E  // PCIE Root Port #4
  52 #define B_PCH_PCIE_ID_VID                                  0x0000FFFF // Vendor ID
  53 #define V_PCH_PCIE_VENDOR_ID                               V_PCH_INTEL_VENDOR_ID
  54
  55
  56 #define R_PCH_PCIE_BNUM_SLT                                0x18  // Bus Numbers; Secondary Latency Timer
  57 #define B_PCH_PCIE_BNUM_SLT_SLT                            0xFF000000 // Secondary Latency Timer
  58 #define B_PCH_PCIE_BNUM_SLT_SBBN                           0x00FF0000 // Subordinate Bus Number
  59 #define B_PCH_PCIE_BNUM_SLT_SCBN                           0x0000FF00 // Secondary Bus Number
  60 #define B_PCH_PCIE_BNUM_SLT_PBN                            0x000000FF // Primary Bus Number
  61 #define R_PCH_PCIE_CAPP                                    0x34  // Capabilities List Pointer
  62 #define B_PCH_PCIE_CAPP                                    0xFF  // Capabilities Pointer
  63
  64 #define R_PCH_PCIE_SLCTL_SLSTS                             0x58  // Slot Control; Slot Status
  65 #define S_PCH_PCIE_SLCTL_SLSTS                             4
  66 #define B_PCH_PCIE_SLCTL_SLSTS_DLLSC                       BIT24 // Data Link Layer State Changed
  67 #define B_PCH_PCIE_SLCTL_SLSTS_PDS                         BIT22 // Presence Detect State
  68 #define B_PCH_PCIE_SLCTL_SLSTS_MS                          BIT21 // MRL Sensor State
  69 #define B_PCH_PCIE_SLCTL_SLSTS_PDC                         BIT19 // Presence Detect Changed
  70 #define B_PCH_PCIE_SLCTL_SLSTS_MSC                         BIT18 // MRL Sensor Changed
  71 #define B_PCH_PCIE_SLCTL_SLSTS_PFD                         BIT17 // Power Fault Detected
  72 #define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE                      BIT12 // Data Link Layer State Changed Enable
  73 #define B_PCH_PCIE_SLCTL_SLSTS_PCC                         BIT10 // Power Controller Control
  74 #define B_PCH_PCIE_SLCTL_SLSTS_HPE                         BIT5  // Hot Plug Interrupt Enable
  75 #define B_PCH_PCIE_SLCTL_SLSTS_CCE                         BIT4  // Command Completed Interrupt Enable
  76 #define B_PCH_PCIE_SLCTL_SLSTS_PDE                         BIT3  // Presence Detect Changed Enable
  77
  78 #define R_PCH_PCIE_SVID                                    0x94  // Subsystem Vendor IDs
  79 #define S_PCH_PCIE_SVID                                    4
  80 #define B_PCH_PCIE_SVID_SID                                0xFFFF0000 // Subsystem Identifier
  81 #define B_PCH_PCIE_SVID_SVID                               0x0000FFFF // Subsystem Vendor Identifier
  82
  83 #endif